TECH_I Vol.25 改訂新版PCIデバイス設計入門

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ありあさんきち
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1 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity n is port( ); end entity n; architecture RTL of nis begin when : process begin end process :process begin end process end RTL; 21

2 h 8000_0000h process 8000_0000h 8000_0000h PCICHK.EXE 22

3 23 process port

4 entity PCI_TGT1 is port( -- PCI ( 1 ) -- PCICLK : in std_logic; -- PCI RST_n : in std_logic; -- PCIAD : inout std_logic_vector(31 downto 0); -- / C_BE_n : in std_logic_vector(3 downto 0); -- PCI / FRAME_n : in std_logic; -- IRDY_n : in std_logic; -- DEVSEL_n : out std_logic; -- TRDY_n : out std_logic; LED LED_OUT : out std_logic ); end entity PCI_TGT1; architecture RTL of PCI_TGT1 is -- ********** / -- PCI //IDSEL -- signal PCI_BusCommand : std_logic_vector(3 downto 0); -- PCI signal PCI_Address : std_logic_vector(31 downto 0); -- PCI -- signal LOCAL_Bus_Start : std_logic; -- signal LOCAL_DTACK : std_logic; PCI signal PCIAD_HiZ : std_logic; -- AD signal PCIAD_Port : std_logic_vector(31 downto 0); -- AD signal DEVSEL_HiZ, DEVSEL_Port : std_logic; -- DEVSEL# / signal TRDY_HiZ, TRDY_Port : std_logic; -- TRDY# / -- PCI () constant PCI_MemWriteCycle : std_logic_vector(3 downto 0) := ( 0111); -- signal Hit_Device : std_logic; -- begin -- ********** -- PCIAD <= (others => Z) when PCIAD_HiZ = 1else PCIAD_Port; DEVSEL_n <= Zwhen DEVSEL_HiZ = 1else DEVSEL_Port; TRDY_n <= Zwhen TRDY_HiZ = 1 else TRDY_Port; in out out portout signal DEVSEL_HiZ 1 DEVSEL_nZ DEVSEL_HiZ 1DEVSEL_Port DEVSEL_nDEVSEL_n DEVSEL_ HiZDEVSEL_PorDEVSEL_n inout signal 24

5 BUS_IDLE PCI_Address portframe_n:in std_logic; portled_out:out std_logic; portdevsel_n:out std_logic; signalsignal DEVSEL_HiZ:std_logic; signalsignal DEVSEL_Port:std_logic; DEVSEL_n<='Z'when DEVSEL_HiZ='1' else DEVSEL_Port; portpciad:inout std_logic_vector(31 downto 0); signalsignal PCIAD_HiZ:std_logic; signalsignal PCIAD_Port:std_logic_ vector(31 downto 0); PCIAD<=(others=>'Z')when PCIAD_HiZ='1'else PCIAD_Port; BUS-IDLE TURN-AROUND ADRS-COMPARE ACC-COMPLETE BUS-BUSY Hit-Device Hit -Device WAIT-IRDY LOCAL-DTACK WAIT-LOCAL-ACK LOCAL-DTACK 25

6 -- ********** PCI PCI_TGT_Seq : process( PCICLK, RST_n ) -- PCI -- variable PCI_CURRENT_STATE : std_logic_vector (2 downto 0);-- variable PCI_NEXT_STATE : std_logic_vector (2 downto 0);-- -- PCI constant BUS_IDLE : std_logic_vector (2 downto 0) :="000"; constant ADRS_COMPARE : std_logic_vector (2 downto 0) :="010"; constant WAIT_IRDY : std_logic_vector (2 downto 0) :="011"; constant WAIT_LOCAL_ACK : std_logic_vector (2 downto 0) :="100"; constant ACC_COMPLETE : std_logic_vector (2 downto 0) :="101"; constant BUS_BUSY : std_logic_vector (2 downto 0) :="110"; constant TURN_AROUND : std_logic_vector (2 downto 0) :="111"; begin -- ********** ********** -- if (RST_n = '0') then -- PCI () PCI_CURRENT_STATE:= BUS_IDLE; -- IDLE PCI_NEXT_STATE := BUS_IDLE; -- IDLE LOCAL_Bus_Start <= '0'; -- PCI_BusCommand <= (others => '0'); -- PCI PCI_Address <= (others => '0'); -- PCI -- PCIAD_HiZ <= '1'; DEVSEL_HiZ <= '1'; DEVSEL_Port <= '1'; -- DEVSEL#="H" TRDY_HiZ <= '1'; TRDY_Port <= '1'; -- TRDY#="H" -- ********** PCI ********** -- elsif (PCICLK'event and PCICLK = '1') then PCI_CURRENT_STATE := PCI_NEXT_STATE;-- case PCI_CURRENT_STATE is -- ********** BUS_IDLE ********** -- when BUS_IDLE => -- if (FRAME_n = '0' and IRDY_n = '1') then -- PCI_BusCommand <= C_BE_n; -- PCI PCI_Address <= PCIAD; -- PCI_NEXT_STATE := ADRS_COMPARE; else -- PCI_NEXT_STATE := BUS_IDLE; BUS_IDLE -- ********** ADRS_COMPARE ********** -- when ADRS_COMPARE => -- if (Hit_Device = '1') then -- DEVSEL_Port <= '0'; DEVSEL_HiZ <= '0'; -- DEVLSEL# TRDY_HiZ <= '0'; -- TRDY# "H" PCI_NEXT_STATE := WAIT_IRDY; -- else -- ADR_COMPARE PCI_NEXT_STATE := BUS_BUSY; ********** BUS_BUSY ********** -- when BUS_BUSY => -- if (FRAME_n = '1' and IRDY_n = '1') then -- () PCI_NEXT_STATE := BUS_IDLE; -- else -- PCI_NEXT_STATE := BUS_BUSY; BUS_BUSY -- ********** WAIT_IRDY ********** -- when WAIT_IRDY => -- if (IRDY_n = '0') then-- LOCAL_Bus_Start <= '1';--! PCI_NEXT_STATE := WAIT_LOCAL_ACK;-- else -- PCI_NEXT_STATE := WAIT_IRDY; WAIT_IRDY 26

7 -- ********** WAIT_LOCAL_ACK ********** -- when WAIT_LOCAL_ACK => -- LOCAL_Bus_Start <= '0';-- if (LOCAL_DTACK = '1') then -- TRDY_Port <= '0';-- TRDY# PCI_NEXT_STATE := ACC_COMPLETE;-- else -- PCI_NEXT_STATE := WAIT_LOCAL_ACK; WAIT_LOCAL_ACK -- ********** ACC_COMPLETE ********** -- when ACC_COMPLETE => -- DEVSEL_Port <= '1';-- DEVSEL# TRDY_Port <= '1';-- TRDY# PCIAD_HiZ <= '1' ;-- PCIAD[31:0] PCI_NEXT_STATE := TURN_AROUND;-- -- ********** TURN_AROUND ********** -- when TURN_AROUND => -- DEVSEL_HiZ <= '1'; -- DEVSEL# TRDY_HiZ <= '1'; -- TRDY# PCI_NEXT_STATE := BUS_IDLE;-- ACC_COMPLETE TURN_AROUND -- ****************************************** -- when others => null; -- end case; end process PCI_TGT_Seq; h 27

8 PCI_BusCommand ADRS_COMPARE PCI_NEXT_STATE else Hit_ Device WAIT_IRDY Hit_Device BUS_BUSY BUS_BUSY ADRS_COMPARE BUS_IDLE ADRS_COMPARE BUS_IDLE ADRS_COMPARE 28

9 BUS_IDLE WAIT_IRDY 29

10 WAIT_IRDY WAIT_IRDY LOCAL_Bus_Start LOCAL_Bus_Start WAIT_LOCAL_ACK WAIT_IRDY LOCAL_Bus_Start LOCAL_ DTACK LOCAL_DTACK ACC_COMPLETE WAIT_LOCAL_ACK ACC_COMPLETE BUS_IDLE TURN_ AROUND TURN_AROUND ACC_ COMPLETE BUS_IDLE ACC_COMPLETE ACC_COMPLETEBUS_ IDLEBUS_IDLE 30

11 BUS_IDLE TURN_AROUND WAIT_LOCAL_ACK ACC_COMPLETE TURN_ AROUND BUS_IDLE ADRS_COMPARE BUS_BUSYWAIT_ IRDY TURN_AROUND BUS_IDLE ADRS_COMPARE Hit_Device PCI_Address PCI_ BusCommand 8000_0000h BUS_IDLE Hit_Device 31

12 -- ********** Address_Compare : process ( PCI_Address, -- PCI PCI_BusCommand -- ) constant MEMORY_BASE_ADDRESS : std_logic_vector(31 downto 0) := X" " ; -- begin -- if ( PCI_BusCommand(3 downto 0) = PCI_MemWriteCycle-- ) and ( PCI_Address = MEMORY_BASE_ADDRESS-- ) then Hit_Device <= '1'; -- else Hit_Device <= '0'; end process Address_Compare ; PCI-Address h PCI-BusCommand Hit-Device V cc LED_OUT LOCAL-IDLE LOCAL-Bus-Start LOCAL-Bus-Start LOCAL-STATE-COMP LOCAL-MEM-ACCESS 32

13 -- ********** LOCAL_BUS_Seq : process( PCICLK, RST_n ) variable LOCAL_CURRENT_STATE : std_logic_vector (1 downto 0);-- variable LOCAL_NEXT_STATE : std_logic_vector (1 downto 0);-- -- constant LOCAL_IDLE : std_logic_vector(1 downto 0) := "00"; constant LOCAL_MEM_ACCESS : std_logic_vector(1 downto 0) := "01"; constant LOCAL_STATE_COMP : std_logic_vector(1 downto 0) := "11"; begin -- ********** ********** -- if ( RST_n = '0' ) then-- PCI -- LOCAL_CURRENT_STATE := LOCAL_IDLE; -- LOCAL_NEXT_STATE := LOCAL_IDLE; -- LOCAL_DTACK <= '0' ;-- LED_OUT <= '1'; -- LED -- ********** ********** -- elsif (PCICLK'event and PCICLK = '1') then LOCAL_CURRENT_STATE := LOCAL_NEXT_STATE ; case LOCAL_CURRENT_STATE is -- ********** LOCAL_IDLE ********** -- when LOCAL_IDLE =>-- if (LOCAL_Bus_Start = '1' ) then --! LOCAL_NEXT_STATE := LOCAL_MEM_ACCESS;-- else-- LOCAL_NEXT_STATE := LOCAL_IDLE; -- ********** LOCAL_MEM_ACCESS ********** -- when LOCAL_MEM_ACCESS => -- LED_OUT <= not PCIAD(0); -- LED LOCAL_DTACK <= '1' ;-- LOCAL_NEXT_STATE := LOCAL_STATE_COMP; -- ********** LOCAL_STATE_COMP ********** -- when LOCAL_STATE_COMP => -- LOCAL_DTACK <= '0' ;-- LOCAL_NEXT_STATE := LOCAL_IDLE; LOCAL_IDLE LOCAL_MEM_ACCESS LOCAL_STATE_COMP -- ********************************************** -- when others => null; -- end case; end process LOCAL_BUS_Seq ; LOCAL_Bus_Start LOCAL_MEM_ ACCESS LED_OUT LED_OUT LOCAL_DTACK LOCAL_STATE_COMP LOCAL_DTACK 33

14 LOCAL_ IDLE MEMORY. COM >MEMORY FFh 8000_0000h FF 00 FFh s s s 34

if clear = 1 then Q <= " "; elsif we = 1 then Q <= D; end rtl; regs.vhdl clk 0 1 rst clear we Write Enable we 1 we 0 if clk 1 Q if rst =

if clear = 1 then Q <= ; elsif we = 1 then Q <= D; end rtl; regs.vhdl clk 0 1 rst clear we Write Enable we 1 we 0 if clk 1 Q if rst = VHDL 2 1 VHDL 1 VHDL FPGA VHDL 2 HDL VHDL 2.1 D 1 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; regs.vhdl entity regs is clk, rst : in std_logic; clear : in std_logic; we