A0~A13 BA0, BA1 0~35 CS FN PD, L, U L, U V DD V SS V D V SSQ V REF NC TMS, TDI, TCK, TDO (+2.5 V) ( ) (+1.5V / +1.8 V) ( ) ( ) ( ) /65

Size: px
Start display at page:

Download "A0~A13 BA0, BA1 0~35 CS FN PD, L, U L, U V DD V SS V D V SSQ V REF NC TMS, TDI, TCK, TDO (+2.5 V) ( ) (+1.5V / +1.8 V) ( ) ( ) ( ) 2005-11-08 2/65"

Transcription

1 TC59LM836DKG-33,-40 MOS CMOS 288M FCRAM2 2,097, TC59LM836DKG CMOS 301,989,888 (FCRAM TM ) TC59LM836DKG 2,097, bit / 600M / FCRAM TM DDR SDRAM TC59LM836DKG t CK ( ) TC59LM836DKG ns 5.0 ns CL = ns 4.5 ns CL = ns 4.0 ns t RC / ( ) 22.5 ns 25 ns t RAC ( ) 22.5 ns 25 ns I DD1S ( ) ) 360 ma 340 ma l DD2P ( ) ) 95 ma 90 ma l DD6 ( ) 15 ma 15 ma (DDR) /( / ) / ( & ) CS FN ( & ) : 300 MHz : 600 M / 4 & ( 3.9 µs) = CAS 1 CAS / CAS = 4, 5, 6 = 2, 4 : 2,097, VDD: 2.5 V ± 0.125V VD: 1.4 V ~ 1.9 V : SSTL_18 (Half strength driver) / HSTL JTAG : 144Ball BGA, 1mm 0.8mm Ball pitch (P-TFBGA BZ) : FCRAM ( ) /65

2 A0~A13 BA0, BA1 0~35 CS FN PD, L, U L, U V DD V SS V D V SSQ V REF NC TMS, TDI, TCK, TDO (+2.5 V) ( ) (+1.5V / +1.8 V) ( ) ( ) ( ) /65

3 ( ) ball pitch=1.0 x 0.8mm Index 0.8mm A V DD V SS V SS V DD V DD V SS V SS V DD B V D V D V D 0 1 V D 1mm C V SSQ V SSQ V SSQ 2 3 V SSQ D V D V D V D 4 5 V D E V SSQ V SSQ V SSQ 6 7 V SSQ F V D L 9 V D V D 8 L V D G V SSQ V REF V SSQ V SSQ A13 FN V SSQ H V SS PD V SS V SS CS NC V SS J V DD A12 A11 V DD V DD BA1 BA0 V DD K V SS A9 A8 V SS V SS A0 A10 V SS L V DD A7 A6 V DD V DD A2 A1 V DD M V D A5 A4 V D V D NC A3 V D N V SSQ U 26 V SSQ V SSQ 27 U V SSQ P V D V D V D V D R V SSQ V SSQ V SSQ V SSQ T V D V D V D V D U V SSQ V SSQ V SSQ V SSQ V TMS TCK V SS V DD V DD V SS TDO TDI : Depopulated ball /65

4 PD CS FN A0~A13 BA0, BA1 DLL #1 #0 #3 #2 / L L U U 0~17 18~35 : TC59LM836DKG /65

5 V DD 0.3~ 3.3 V V D ( ) 0.3~V DD V V IN 0.3~V DD V V OUT ( ) 0.3~V D V V REF 0.3~V DD V T opr ( ) 0~85 C T stg 55~150 C T solder (10 ) 260 C P D 2.5 W I OUT ±50 ma : DC, AC ( : 1)(T CASE = 0~85 C) V DD V V D ( ) V V REF V D /2 95% V D /2 V D /2 105% V 2 V IH (DC) V IL (DC) V ICK (DC) V ID (DC) V IH (AC) V IL (AC) V ID (AC) V X (AC) V ISO (AC) (DC) V REF V D V 5 (DC) 0.1 V REF V 5 DC 0.1 V D V 10 (DC) 0.4 V D V 7, 10 (AC) V REF V D V 3, 6 (AC) 0.1 V REF 0.2 V 4, 6 (AC) 0.55 V D V 7, 10 (AC) V D / V D / V 8, 10 (AC) V D / V D / V 9, /65

6 : (1) VSS VSSQ (2) VREF VD (DC) VREF VREF (DC) ±2% (3) : 5 ns VIH (max) = VD V (4) : 5 ns VIL (min) = 0.7 V (5) VIH (DC) VIL (DC) (6) VIH (AC) VIL (AC) (7) VID (8) VX (AC) VD/2 (9) VISO {VICK () + VICK ( )} /2 (10) V SS V ID (AC) V x V x V x V x V x V ICK V ICK V ICK V ICK V ID (AC) 0 V Differential V ISO V ISO (min) V ISO (max) V SS (11) (VTT) VREF (DC) ± 0.04 V (V DD = 2.5V, V D = 1.8 V, f = 1 MHz, Ta = 25 C) (MAX) C IN C INC C I/O (, ) pf (, ) pf (, L, U, L, U) pf C NC NC 1.5 pf : /65

7 (V DD = 2.5V ± 0.125V, V D = 1.4V ~ 1.9V, T CASE = 0 ~ 85 C) TC59LM836DKG-33, I DD1S I DD2N I DD2P I DD4W I DD4R I DD5B I DD6 / t CK = min I RC = min I OUT = 0mA Burst Length = 4 CAS Latency = 6 Free running mode 0 V V IN V IL (AC) (max) V IH (AC) (min) V IN V D I RC : t CK = min CS = V IH PD = V IH 0 V V IN V IL (AC) (max) V IH (AC) (min) V IN V D 4 t CK , , 2 ( ) : t CK = min PD = V IL ( ) CAS Latency = 6 Free running mode 0 V V IN V IL (AC) (max), V IH (AC) (min) V IN V D 4 t CK 1 (V D /2) , 2 (4 ) 4 t CK = min, I RC = min ma Burst Length = 4 CAS Latency = 6 Free running mode 0 V V IN V IL (AC) (max) V IH (AC) (min) V IN V D , 2 (4 ) 4 t CK = min I RC = min I OUT = 0mA Burst Length = 4 CAS Latency = 6 Free running mode 0 V V IN V IL (AC) (max) V IH (AC) (min) V IN V D , 2 t CK = min I REFC = min CAS Latency = 6 Free running mode 0 V V IN V IL (AC) (max) V IH (AC) (min) V IN V D I REFC , 2, 3 PD = 0.2 V (V D /2) (V D /2) 2 : 1. t CK t RC I RC 2. V DD V SS 3. I DD5B t REFI /65

8 (V DD = 2.5V ± 0.125V, V D = 1.4V ~ 1.9V, T CASE = 0 ~ 85 C) ( ) I LI I LO ( 0 V V IN V D 0 V) ( 0 V V OUT V D ) 5 5 µa 5 5 µa I REF V REF 5 5 µa I OH (DC) Normal Output V OH = V 5.6 I OL (DC) Driver V OL = V 5.6 I OH (DC) Strong Output V OH = V 9.8 I OL (DC) Driver (V D = 1.7V~1.9V) V OL = V 9.8 ma 1 I OH (DC) Weak V OH = V 2.8 I OL (DC) Output Driver V OL = V 2.8 I OH (DC) Normal Output V OH = V D 0.4V 4 I OL (DC) Driver V OL = 0.4V 4 I OH (DC) Strong Output V OH = V D 0.4V 8 I OL (DC) Driver (V D = 1.4V~1.6V) V OL = 0.4V 8 ma 1 I OH (DC) Weak Output I OL (DC) Driver : /65

9 AC ( : 1, 2) (V DD = 2.5 ± 0.125V, V D = V, T CASE = 0 85 C) t RC C L = t CK C L = C L = t RAC t CH 0.45 t CK 0.45 t CK 3 t CL 0.45 t CK 0.45 t CK 3 t CK , 8, 10 t Q t QA ( ) t AC , 8, 10 t OH , 8 t HP t P Min(t CH, (t CH t CL ) t CL ) min(t CH, t CL ) 3 ( ) t HP t QHS t HP t QHS 4, 8 t QV t HP t QHS t HP t QHS 4, 8 t QHS t SS t PRE t, CK t CK ( ) ns 0.8 t CK 1.2 t CK 0.8 t CK 1.2 t CK 3 ( ) 0.4 t CK 0.4 t CK 4 t PRES 1st t PREH 1st 0.3 t CK 0.3 t CK 3 t P 0.45 t CK 0.55 t CK 0.45 t CK 0.55 t CK 4 t S t PST t PSTH C L = , 4 ( ) C L = , 4 C L = , 4 ( ) 0.45 t CK 0.45 t CK 4 C L = , 4 ( ) C L = , 4 C L = , 4 t SK U L 0.4 t CK 0.4 t CK 0.4 t CK 0.4 t CK t , 11 t DH , 11 t IS t IH / / /65

10 AC ( : 1, 2) ( ) t LZ t HZ , 6, , 7, 8 t QPDH PD 0 0 t PDEX ns 3 t T t FPDL / PD ( ) 0.5 t CK t CK 5 t REFI µs t PAUSE I RC I RCD I RAS I RBD C L = / ( ) C L = C L = RDA/WRA LAL ( ) C L = LAL RDA/WRA C L = 5 ( ) 5 5 C L = ( ) 3 I RWD I WRD I RSC I PD I PDA I PDV I REFC I CKD I LOCK B L = RDA LAL WRA ( ) B L = WRA LAL RDA ( ) 1 1 C L = C L = C L = PD 2 2 PD 1 1 C L = REF C L = C L = C L = C L = C L = REF I REFC I REFC ( ) DLL (RDA ) cycle /65

11 AC V IH (min) V IL (max) (AC) V REF V (AC) V REF 0.2 V V REF V D /2 V V TT V REF V V SWING 0.8 V Vr V X (AC) V V ID (AC), 1.0 V SLEW 2.5 V/ns V OTR V D /2 V 9 V D V SWING V IH min (AC) V REF Output 25 Ω V TT V IL max (AC) V SS T T SLEW = (V IH min (AC) V IL max (AC))/ T Measurement point AC Test Load : (1) VIH min (DC) VIL max (DC) (2) Cycle tck 2 ( : tss = 0.8 tck, tck = 3.3 ns, ns = 2.64 ns 2.7 ns.) (3) ( ) AC (4) VREF (5) trefi (max) trefi (min) trefi (min) 8 400ns 3.2 µs (8 400 ns) (6) VD/2 ± 0.1 V (7) (8) (9) Normal Output Driver VD = 1.4V~1.6V Strong Output Driver (10) tck 6.0ns tck 6.0ns Speed version tck (MIN/MAX) = 0.6ns / 0.6ns, tac (MIN/MAX) = 0.65ns / 0.65ns (11) VD = 1.7V~1.9V VD = 1.4V~1.6V Speed version t(min) = 0.4ns, tdh(min) = 0.4ns /65

12 (1) (VDD VD) PD ( 0.2 V) (2) VD VDD VDD (3) VREF VD VD (4) ( ) 200 µs (5) NOP(DESL) PD (6) EMRS DLL ( 1) (7) MRS CAS (CL) (BT) (BL) ( 1) (8) 2 ( 1) (9) EMRS 200 : (1) (6) (7) (8) (2) (3) V DD 2.5V(TYP) 1.5V or 1.8V(TYP) V D 1/2 V D (TYP) V REF t PDEX 200us(min) l RSC l RSC l REFC l REFC PD l PDA l LOCK = 200clock cycle(min) Command DESL RDA MRS DESL RDA MRS DESL WRA REF DESL WRA REF DESL Address op-code EMRS op-code MRS (Input) L/U (Uni- mode) L/U (Free Running mode) EMRS MRS Auto Refresh cycle Normal Operation /65

13 t CK t CK t CH t CL t IS t IH t IS t IH CS 1st 2nd t IS t IH t IS t IH FN 1st 2nd t IS t IH t IS t IH A0~A13 BA0, BA1 UA, BA LA L/U t t DH t tdh n t t DH t t DH m, t CH t CL V IH V IH (AC) V IL (AC) V IL t CK t T t T V IH V ID (AC) V X V X V X V IL /65

14 (Burst Length = 4) Unidirectional / mode t CH t CL t CK Input (control & addresses) t IS t IH LAL (after RDA) DESL (Input) CAS latency = 4 t CK t P t P t CK t CK L t QA t QA t LZ t QV t QV t Q t HZ t Q t Q L t AC t AC t AC Q0 Q1 Q2 Q3 t QA t QA t OH t CK t P t P t CK U t QA t QA t QV t Q t HZ U t LZ t AC Q0 Q1 Q2 Q3 t AC t AC t OH CAS latency = 5 t CK t P t P t CK t CK L t QA t QA t LZ t Q t Q t QV t Q t QV t HZ L t AC t AC t AC Q0 Q1 Q2 Q3 t QA t QA t OH t CK t CK t P t P U t QA t QA t QV t Q t HZ U t LZ t AC Q0 Q1 Q2 Q3 t AC t AC t OH /65

15 (Burst Length = 4) Unidirectional / mode t CH t CL t CK Input (control & addresses) t IS t IH LAL (after RDA) DESL (Input) CAS latency = 6 L L U t QA t LZ t Q t CK t CK t Q t P t P t CK t QV t Q t QV t HZ t AC t AC t AC Q0 Q1 Q2 Q3 t QA t CK t QA t QA t P t P t OH t CK t QA t QA t QV t Q t HZ U t LZ t AC Q0 Q1 Q2 Q3 t AC t AC t OH : L U L U 0~17 18~ /65

16 (Burst Length = 4) Unidirectional /Free Running mode t CH t CL t CK Input (control & addresses) t IS t IH LAL (after RDA) DESL (Input) CAS latency = 4 L L U t QA t LZ t Q t CK t P t P t CK t Q t CK t QV t QV t Q t HZ t AC t AC t AC Q0 Q1 Q2 Q3 t QA t QA t QA t OH t CK t P t P t CK t QA t QA t QV t Q t HZ U t LZ t AC Q0 Q1 Q2 Q3 t AC t AC t OH CAS latency = 5 t CK t P t P t CK t CK L t QA t QA t LZ t Q t Q t QV t Q t QV t HZ L tac t AC t AC Q0 Q1 Q2 Q3 t QA t QA t OH t CK t CK t P t P U t QA t QA t QV t Q t HZ U t LZ t AC Q0 Q1 Q2 Q3 t AC t AC t OH /65

17 (Burst Length = 4) Unidirectional /Free Running mode t CH t CL t CK Input (control & addresses) t IS t IH LAL (after RDA) DESL (Input) CAS latency = 6 L L U t QA t LZ t Q t CK t CK t Q t P t P t CK t QV t Q t QV t HZ t AC t AC t AC Q0 Q1 Q2 Q3 t QA t CK t QA t QA t P t P t OH t CK t QA t QA t QV t Q t HZ U t LZ t AC Q0 Q1 Q2 Q3 t AC t AC t OH : L U L 0~17 U 18~ /65

18 (Burst Length = 4) Unidirectional / mode, Unidirectional /Free Running mode TC59LM836DKG-33,-40 t CH t CL t CK Input (control & addresses) t IS t IH LAL (after WRA) DESL t SS t PSTH t PRES t S CAS latency = 4 L/U CAS latency = 5 L/U t PREH t P t P t P t PST Preamble t S Postamble t PRE t t DH t t DH t t DH D0 D1 D2 D3 t SS t S t PRES t S t PSTH t t P PREH t P t P t PST Preamble Postamble t PRE t t DH t t t DH t DH D0 D1 D2 D3 t SS t SS t S CAS latency = 6 L/U t PRES t S t PSTH t PREH t P t P t P t PST Preamble Postamble t PRE t t t t DH t DH t DH D0 D1 D2 D3 t SS t SS L/U (Uni-) L/U (Free Runninig) : L U L U 0~17 18~ /65

19 trefi, tpause, IXXXX t REFI, t PAUSE, I XXXX t IS t IH t IS t IH Input (control & addresses) Command Command : I XXXX I RC I RCD I RAS /65

20 ( : 1, 2, 3) ( : 4) 1st CS FN BA1~BA0 A13~A10 A9~A8 A7 A6~A0 DESL Device Deselect H RDA Read with Auto-close L H BA UA UA UA UA WRA Write with Auto-close L L BA UA UA UA UA 2nd BA1~ CS FN BA0 A13~ A12 A11~ A10 A9 A8 A7 A6~A0 LAL er Address Latch H V LA REF Auto-Refresh L MRS Mode Register Set L V L L L L V V : 1. L = Logic, H = Logic High, = either L or H, V = Valid (specified value), BA = Address, UA = Upper Address, LA = er Address SELFX PDEX ( ) CS FN BA1~BA0 A13~A10 A9~A8 A7 A6~A0 NOTES RDA (1st) L H BA UA UA UA UA LAL (2nd) H LA ( ) CS FN BA1~ BA0 A13 A12 A11 A10 A9~A8 A7 A6~A0 WRA (1st) L L BA UA UA UA UA UA UA UA LAL (2nd) H VW0 VW1 LA : 5. A13~ A12 (VW) VW0 VW1 BL=2 Write All Words L Write First One Word H Reserved L L BL=4 Write All Words H L Write First Two Words L H Write First One Word H H /65

21 ( ) ( ) CS FN BA1~BA0 A13~A9 A8 A7 A6~A0 NOTES RDA (1st) L H MRS (2nd) L V V V V V 6 : 6. PD ( ) n 1 n CS FN BA1~BA0 A13~A9 A8 A7 A6~A0 NOTES Active WRA (1st) Standby H H L L Auto-Refresh REF (2nd) Active H H L PD ( ) n 1 n CS FN BA1~BA0 A13~A9 A8 A7 A6~A0 NOTES Active WRA (1st) Standby H H L L Self-Refresh Entry REF (2nd) Active H L L 7, 8 Self-Refresh Continue Self-Refresh L L Self-Refresh Exit SELFX Self-Refresh L H H 9 PD ( ) n 1 n CS FN BA1~BA0 A13~A9 A8 A7 A6~A0 NOTES Power Down Entry PDEN Standby H L H 8 Power Down Continue Power Down L L Power Down Exit PDEX Power Down L H H 9 : 7. PD REF t FPDL 8. PD 9. PD /65

22 Idle ( ) PD n 1 n CS FN Row Active for Read Row Active for Write Read Write Auto-Refreshing Mode Register Accessing Power Down Self-Refreshing : H H H DESL NOP H H L H BA, UA RDA Row activate for Read H H L L BA, UA WRA Row activate for Write H L H PDEN Power Down Entry 10 H L L Illegal L Refer to Power Down State H H H LA LAL Begin Read H H L Op-code MRS/EMRS Access to Mode Register H L H PDEN Illegal H L L MRS/EMRS Illegal L Invalid H H H LA LAL Begin Write H H L REF Auto-Refresh H L H PDEN Illegal H L L REF (self) Self-Refresh Entry L Invalid H H H DESL Continue Burst Read to End H H L H BA, UA RDA Illegal 11 H H L L BA, UA WRA Illegal 11 H L H PDEN Illegal H L L Illegal L Invalid H H H DESL Data Write&Continue Burst Write to End H H L H BA, UA RDA Illegal 11 H H L L BA, UA WRA Illegal 11 H L H PDEN Illegal H L L Illegal L Invalid H H H DESL NOP Idle after I REFC H H L H BA, UA RDA Illegal H H L L BA, UA WRA Illegal H L H PDEN Self-Refresh Entry 12 H L L Illegal L Refer to Self-Refreshing State H H H DESL NOP Idle after I RSC H H L H BA, UA RDA Illegal H H L L BA, UA WRA Illegal H L H PDEN Illegal H L L Illegal L Invalid H Invalid L L Maintain Power Down Mode L H H PDEX Exit Power Down Mode Idle after t PDEX L H L Illegal H Invalid L L Maintain Self-Refresh L H H SELFX Exit Self-Refresh Idle after I REFC L H L Illegal t FPDL /65

23 MRS ( ) ( : 1) ADDRESS BA1 *1 BA0 *1 A13~A8 A7 *3 A6~A4 A3 A2~A0 Register TE CL BT BL A7 TEST MODE (TE) A3 BURST TYPE (BT) 0 Regular (default) 0 Sequential 1 Test Mode Entry 1 Interleave A6 A5 A4 CAS LATENCY (CL) A2 A1 A0 BURST LENGTH (BL) 0 0 Reserved * Reserved * Reserved * Reserved * Reserved * Reserved *2 EMRS ( ) ( : 4) ADDRESS BA1 *4 BA0 *4 A13~A7 A6~A5 A4~A3 A2~A1 A0 *5 Register SS DIC () DIC () A6 A5 STROBE SELECT A4 A3 A2 A1 OUTPUT DRIVE IMPEDANCE CONTROL (DIC) 0 0 Reserved * Normal Output Driver 0 1 Reserved * Strong Output Driver 1 0 Unidirectional / Weak Output Driver 1 1 Unidirectional /Free Running Reserved A0 DLL SWITCH () 0 DLL Enable 1 DLL Disable : 1. BA0 = 0 BA1 = 0 2. Reserved 3. A7 0 ( ) 4. BA0 = 1 BA1 = 0 5. A0 "0"( ) /65

24 SELF- REFRESH POWER DOWN SELFX ( PD = H) PDEX ( PD = H) PD = L PDEN ( PD = L) PD = H STANDBY (IDLE) AUTO- REFRESH MODE REGISTER WRA RDA REF MRS ACTIVE (RESTORE) ACTIVE LAL LAL WRITE (BUFFER) READ Command input Automatic return 2 RDA WRA /65

25 () I RC = 5 cycles I RC = 5 cycles I RC = 5 cycles Command RDA LAL DESL RDA LAL DESL RDA LAL DESL RDA I RCD =1 cycle I RAS = 4 cycles I RCD =1 cycle I RAS = 4 cycles I RCD =1 cycle I RAS = 4 cycles Address UA LA UA LA UA LA UA Add. #0 #0 #0 #0 Unidirectional / mode BL = 2 Q0 Q1 Q0 Q1 Q0 BL = 4 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q0 Unidirectional /Free Running mode BL = 2 Q0 Q1 Q0 Q1 Q0 BL = 4 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q /65

26 (CL = 5) I RC = 6 cycles I RC = 6 cycles Command RDA LAL DESL RDA LAL DESL RDA LAL DESL I RCD =1 cycle I RAS = 5 cycles I RCD =1 cycle I RAS = 5 cycles I RCD =1 cycle Address UA LA UA LA UA LA Add. #0 #0 #0 Unidirectional / mode BL = 2 CL = 5 CL = 5 Q0 Q1 Q0 Q1 BL = 4 CL = 5 CL = 5 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Unidirectional /Free Running mode BL = 2 CL = 5 CL = 5 Q0 Q1 Q0 Q1 BL = 4 CL = 5 CL = 5 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q /65

27 (CL = 6) I RC = 7 cycles I RC = 7 cycles Command RDA LAL DESL RDA LAL DESL RDA LAL I RCD =1 cycle I RAS = 6 cycles I RCD =1 cycle I RAS = 6 cycles I RCD =1 cycle Address UA LA UA LA UA LA Add. #0 #0 #0 Unidirectional / mode BL = 2 CL = 6 CL = 6 Q0 Q1 Q0 Q1 BL = 4 CL = 6 CL = 6 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Unidirectional /Free Running mode BL = 2 CL = 6 CL = 6 Q0 Q1 Q0 Q1 BL = 4 CL = 6 CL = 6 Q0 Q1 Q2 Q3 Q0 Q1 Q /65

28 () I RC = 5 cycles I RC = 5 cycles I RC = 5 cycles Command WRA LAL DESL WRA LAL DESL WRA LAL DESL WRA I RCD =1 cycle I RAS = 4 cycles I RCD =1 cycle I RAS = 4 cycles I RCD =1 cycle I RAS = 4 cycles Address UA LA UA LA UA LA UA Add. #0 #0 #0 #0 Unidirectional / mode BL = 2 WL = 3 WL = 3 WL = 3 D0 D1 D0 D1 D0 D1 BL = 4 WL = 3 WL = 3 WL = 3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 Unidirectional /Free Running mode BL = 2 WL = 3 WL = 3 WL = 3 D0 D1 D0 D1 D0 D1 BL = 4 WL = 3 WL = 3 WL = 3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D /65

29 (CL = 5) I RC = 6 cycles I RC = 6 cycles Command WRA LAL DESL WRA LAL DESL WRA LAL DESL I RCD =1 cycle I RAS = 5 cycles I RCD =1 cycle I RAS = 5 cycles I RCD =1 cycle Address UA LA UA LA UA LA Add. #0 #0 #0 Unidirectional / mode BL = 2 WL = 4 WL = 4 D0 D1 D0 D1 BL = 4 WL = 4 WL = 4 D0 D1 D2 D3 D0 D1 D2 D3 Unidirectional /Free Running mode BL = 2 BL = 4 WL = 4 WL = 4 D0 D1 WL = 4 WL = 4 D0 D1 D2 D3 D0 D1 D0 D1 D2 D /65

30 (CL = 6) I RC = 7 cycles I RC = 7 cycles Command WRA LAL DESL WRA LAL DESL WRA LAL I RCD =1 cycle I RAS = 6 cycles I RCD =1 cycle I RAS = 6 cycles I RCD =1 cycle Address UA LA UA LA UA LA Add. #0 #0 #0 Unidirectional / mode BL = 2 WL = 5 WL = 5 D0 D1 D0 D1 BL = 4 WL = 5 WL = 5 D0 D1 D2 D3 D0 D1 D2 D3 Unidirectional /Free Running mode BL = 2 BL = 4 WL = 5 WL = 5 D0 D1 D0 D1 WL = 5 WL = 5 D0 D1 D2 D3 D0 D1 D2 D /65

31 / () I RC = 5 cycles I RC = 5 cycles I RC = 5 cycles Command RDA LAL DESL WRA LAL DESL RDA LAL DESL WRA Address UA LA UA LA UA LA UA Add. #0 #0 #0 #0 Unidirectional / mode BL = 2 WL = 3 Q0 Q1 D0 D1 Q0 BL = 4 WL = 3 Q0 Q1 Q2 Q3 D0 D1 D2 D3 Q0 Unidirectional /Free Running mode BL = 2 WL = 3 Q0 Q1 D0 D1 Q0 BL = 4 WL = 3 Q0 Q1 Q2 Q3 D0 D1 D2 D3 Q0 Read data Write data /65

32 / (CL = 5) I RC = 6 cycles I RC = 6 cycles Command RDA LAL DESL WRA LAL DESL RDA LAL DESL Address UA LA UA LA UA LA Add. #0 #0 #0 Unidirectional / mode BL = 2 CL = 5 WL = 4 Q0 Q1 D0 D1 BL = 4 CL = 5 WL = 4 Q0 Q1 Q2 Q3 D0 D1 D2 D3 Unidirectional /Free Running mode BL = 2 CL = 5 WL = 4 Q0 Q1 D0 D1 BL = 4 CL = 5 WL = 4 Q0 Q1 Q2 Q3 D0 D1 D2 D3 Read data Write data /65

33 / (CL = 6) I RC = 7 cycles I RC = 7 cycles Command RDA LAL DESL WRA LAL DESL RDA LAL Address UA LA UA LA UA LA Add. #0 #0 #0 Unidirectional / mode BL = 2 CL = 6 WL = 5 Q0 Q1 D0 D1 BL = 4 CL = 6 WL = 5 Q0 Q1 Q2 Q3 D0 D1 D2 D3 Unidirectional /Free Running mode BL = 2 CL = 6 WL = 5 Q0 Q1 D0 D1 BL = 4 CL = 6 WL = 5 Q0 Q1 Q2 Q3 D0 D1 D2 D3 Read data Write data /65

34 () I RBD = 2 cycles I RBD = 2 cycles I RBD = 2 cyclesi RBD = 2 cycles I RBD = 2 cycles Command RDA LAL RDA LAL DESL RDA LAL RDA LAL RDA LAL RDA LAL RDA LAL RDA Address UA LA UA LA UA LA UA LA UA LA UA LA UA LA UA Add. "a" "b" "a" "b" "c" "d" "a" "b" I RC ("a") = 5 cycles I RC ("b") = 5 cycles Unidirectional / mode BL = 2 Qa0Qa1 Qb0Qb1 Qa0Qa1 Qb0 Qb1 Qc0Qc1 BL = 4 Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 Qa0Qa1Qa2 Qa3 Qb0 Qb1 Qb2 Qb3Qc0Qc1Qc2 Unidirectional /Free Running mode BL = 2 Qa0Qa1 Qb0Qb1 Qa0Qa1 Qb0 Qb1 Qc0Qc1 BL = 4 Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 Qa0Qa1Qa2 Qa3 Qb0 Qb1 Qb2 Qb3Qc0Qc1Qc2 : l RC /65

35 (CL = 5) I RBD = 2 cycles I RBD = 2 cycles I RBD = 2 cycles I RBD = 2 cycles I RBD = 2 cycles Command RDA LAL RDA LAL DESL RDA LAL RDA LAL RDA LAL RDA LAL RDA LAL Address UA LA UA LA UA LA UA LA UA LA UA LA UA LA Add. "a" "b" "a" "b" "c" "d" "a" I RC ("a") = 6 cycles Unidirectional / mode BL = 2 I RC ("b") = 6 cycles CL = 5 CL = 5 Qa0Qa1 Qb0Qb1 Qa0 Qa1 Qb0Qb1 BL = 4 CL = 5 CL = 5 Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 Qa0 Qa1 Qa2 Qa3Qb0Qb1Qb2 Unidirectional /Free Running mode BL = 2 CL = 5 CL = 5 Qa0Qa1 Qb0Qb1 Qa0 Qa1 Qb0Qb1 BL = 4 CL = 5 CL = 5 Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 : l RC Qa0 Qa1 Qa2 Qa3Qb0Qb1Qb /65

36 (CL = 6) I RBD = 2 cycles I RBD = 2 cycles I RBD = 2 cycles I RBD = 2 cycles I RBD = 2 cycles Command RDA LAL RDA LAL DESL RDA LAL RDA LAL RDA LAL RDA LAL RDA Address UA LA UA LA UA LA UA LA UA LA UA LA UA Add. "a" "b" "a" "b" "c" "d" "a" I RC ("a") = 7 cycles Unidirectional / mode BL = 2 I RC ("b") = 7 cycles CL = 6 CL = 6 Qa0Qa1 Qb0Qb1 Qa0Qa1 BL = 4 CL = 6 CL = 6 Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 Qa0Qa1Qa2 Unidirectional /Free Running mode BL = 2 CL = 6 CL = 6 Qa0Qa1 Qb0Qb1 Qa0Qa1 BL = 4 CL = 6 CL = 6 Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 Qa0Qa1Qa /65

37 () I RBD = 2 cycles I RBD = 2 cycles I RBD = 2 cycles I RBD = 2 cycles I RBD = 2 cycles Command WRA LAL WRA LAL DESL WRA LAL WRA LAL WRA LAL WRA LAL WRA LAL WRA Address UA LA UA LA UA LA UA LA UA LA UA LA UA LA UA Add. "a" "b" "a" "b" "c" "d" "a" "b" I RC ("a") = 5 cycles I RC ("b") = 5 cycles Unidirectional / mode BL = 2 WL = 3 WL = 3 Da0 Da1 Db0Db1 Da0Da1 Db0Db1 Dc0 Dc1 Dd0Dd1 BL = 4 WL = 3 WL = 3 Da0 Da1Da2Da3Db0Db1Db2Db3 Da0Da1Da2Da3Db0Db1 Db2 Db3 Dc0 Dc1 Dc2Dc3Dd0Dd1 Unidirectional /Free Running mode BL = 2 WL = 3 WL = 3 Da0 Da1 Db0Db1 Da0Da1 Db0Db1 Dc0 Dc1 Dd0Dd1 BL = 4 WL = 3 WL = 3 Da0 Da1Da2Da3Db0Db1Db2Db3 Da0Da1Da2Da3Db0Db1 Db2 Db3 Dc0 Dc1 Dc2Dc3Dd0Dd1 : l RC /65

38 (CL = 5) I RBD = 2 cycles I RBD = 2 cycles I RBD = 2 cycles I RBD = 2 cycles I RBD = 2 cycles Command WRA LAL WRA LAL DESL WRA LAL WRA LAL WRA LAL WRA LAL WRA LAL Address UA LA UA LA UA LA UA LA UA LA UA LA UA LA Add. Unidirectional / mode BL = 2 "a" "b" I RC ("a") = 6 cycles WL = 4 WL = 4 "a" I RC ("b") = 6 cycles Da0Da1 "b" "c" "d" "a" Db0Db1 Da0Da1 Db0 Db1 Dc0Dc1 BL = 4 WL = 4 WL = 4 Da0Da1Da2Da3Db0Db1Db2Db3 Da0Da1 Da2 Da3 Db0 Db1 Db2Db3Dc0Dc1 Unidirectional /Free Running mode BL = 2 BL = 4 WL = 4 WL = 4 Da0Da1 Db0Db1 Da0Da1 Db0 Db1 Dc0Dc1 WL = 4 WL = 4 Da0Da1Da2Da3Db0Db1Db2Db3 Da0Da1 Da2 Da3 Db0 Db1 Db2Db3Dc0Dc1 : l RC /65

39 (CL = 6) I RBD = 2 cycles I RBD = 2 cycles I RBD = 2 cycles I RBD = 2 cycles I RBD = 2 cycles Command WRA LAL WRA LAL DESL WRA LAL WRA LAL WRA LAL WRA LAL WRA Address UA LA UA LA UA LA UA LA UA LA UA LA UA Add. Unidirectional / mode BL = 2 "a" "b" I RC ("a") = 7 cycles WL = 5 WL = 5 "a" I RC ("b") = 7 cycles Da0Da1 "b" "c" "d" "a" Db0Db1 Da0 Da1 Db0Db1 BL = 4 WL = 5 WL = 5 Da0Da1Da2Da3Db0Db1Db2Db3 Da0 Da1 Da2Da3Db0Db1 Unidirectional /Free Running mode BL = 2 BL = 4 WL = 5 WL = 5 Da0Da1 Db0Db1 Da0 Da1 Db0Db1 WL = 5 WL = 5 Da0Da1Da2Da3Db0Db1Db2Db3 : l RC Da0 Da1 Da2Da3Db0Db /65

40 / (BL = 2) I RBD = 2 cycles Command WRA LAL RDA LAL DESL WRA LAL RDA LAL DESL WRA LAL RDA LAL DESL WRA I WRD = 1 cycle I RWD = 2 cycles I WRD = 1 cycle I RWD = 2 cycles Address UA LA UA LA UA LA UA LA UA LA UA LA UA Add. Unidirectional / mode WL = 3 Da0 Da1 Qb0 Qb1 Dc0 Dc1 Qd0 Qd1 Da0 Da1 CL = 5 CL = 6 "a" "b" WL = 4 WL = 5 Unidirectional /Free Running mode "c" "d" I RC ("a") I RC ("b") CL = 5 CL = 6 "a" "b" "c" Da0 Da1 Qb0 Qb1 Dc0 Dc1 Qd0 Qd1 Da0 Da1 Da0 Da1 Qb0 Qb1 Dc0 Dc1 Qd0 Qd1 WL = 3 Da0 Da1 Qb0 Qb1 Dc0 Dc1 Qd0 Qd1 Da0 Da1 CL = 5 CL = 6 WL = 4 WL = 5 CL = 5 Da0 Da1 Qb0 Qb1 Dc0 Dc1 Qd0 Qd1 Da0 Da1 CL = 6 Da0 Da1 Qb0 Qb1 Dc0 Dc1 Qd0 Qd1 : l RC /65

41 / (BL = 4) I RBD = 2 cycles Command WRA LAL RDA LAL DESL WRA LAL RDA LAL DESL WRA LAL RDA I WRD = 1 cycle I RWD = 3 cycles I WRD = 1 cycle I RWD = 3 cycles I WRD = 1 cycle LAL Address UA LA UA LA UA LA UA LA UA LA UA LA Add. Unidirectional / mode CL = 5 CL = 6 "a" "b" WL = 3 WL = 4 WL = 5 "c" I RC ("a") CL = 5 CL = 6 "d" I RC ("b") "a" "b" Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 Dc0 Dc1 Dc2 Dc3 Qd0 Qd1 Qd2 Qd3 Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 Dc0 Dc1 Dc2 Dc3 Qd0 Qd1 Qd2Qd3 Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 Dc0 Dc1 Dc2 Dc3 Qd0 Qd1 CL = 5 WL = 3 Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 Dc0 Dc1 Dc2 Dc3 Qd0 Qd1 Qd2 Qd3 WL = 4 CL = 5 Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 Dc0 Dc1 Dc2 Dc3 Qd0 Qd1 Qd2 Qd3 WL = 5 CL = 6 Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 Dc0 Dc1 Dc2 Dc3 Qd0Qd1 : l RC /65

42 (VW) () TC59LM836DKG-33, BL = 2, SEQUENTIAL MODE Command WRA LAL DESL WRA LAL DESL Address UA LA=#3 VW=All UA LA=#1 VW=1 VW0 = VW1 = don't care VW0 = High VW1 = don't care Add. "a" "a" BL = 4, SEQUENTIAL MODE D0 D1 er Address #3 #2 #1 (#0) D0 Last one data is masked. Command WRA LAL DESL WRA LAL DESL WRA LAL DESL Address UA LA=#3 VW=All UA LA=#1 VW=1 UA LA=#2 VW=2 VW0 = High VW1 = VW0 = High VW1 = High VW0 = VW1 = High Add. "a" "a" "a" D0 D1 D2 D3 D0 er Address #3 #0 #1 #2 #1(#2)(#3)(#0) Last three data are masked. D0 D1 #2 #3 (#0)(#1) Last two data are masked. : MRS /65

43 (, BL = 4) TC59LM836DKG-33, n-2 n-1 n n+1 n+2 I PDA Command RDA LAL DESL DESL RDA or WRA Address UA LA UA t IH t IS I PD = 2 cycle PD Unidirectional / mode t QPDH l RC(min), t REFI(max) t PDEX Q0 Q1 Q2 Q3 Unidirectional /Free Running mode Q0 Q1 Q2 Q3 Power Down Entry Power Down Exit : PD PD t REFI (max.) PD PD l PDA /65

44 (, BL = 4) TC59LM836DKG-33, n-2 n-1 n n+1 n+2 I PDA Command WRA LAL DESL DESL RDA or WRA Address UA LA UA t IH t IS I PD = 2 cycle PD WL = 3 2 clock cycles l RC(min), t REFI(max) t PDEX Unidirectional / mode WL = 3 D0 D1 D2 D3 Unidirectional /Free Running mode WL = 3 D0 D1 D2 D3 : PD LAL WL+2 PD t REFI (max.) PD PD l PDA /65

45 (, BL = 2) I RSC = 7 cycles 15 Command RDA LAL DESL RDA MRS DESL RDA or WRA LAL Address UA LA Valid (opcode) UA LA Add. BA BA0="0" BA1="0" BA CL + BL/2 Unidirectional / mode Q0 Q1 Unidirectional /Free Running mode Q0 Q1 : RDA LAL MRS RDA CL+BL/ /65

46 (, BL = 4) TC59LM836DKG-33, I RSC = 7 cycles 15 Command WRA LAL DESL RDA MRS DESL RDA or WRA LAL Address UA LA Valid (opcode) UA LA Add. BA BA0="0" BA1="0" BA WL+BL/2 Unidirectional / mode D0 D1 D2 D3 Unidirectional /Free Running mode D0 D1 D2 D3 : WRA LAL MRS RDA WL+BL/ /65

47 (, BL = 2) TC59LM836DKG-33, I RSC = 7 cycles 15 Command RDA LAL DESL RDA MRS DESL RDA or WRA LAL Address UA LA Valid (opcode) UA LA Add. BA BA0="1" BA1="0" BA CL + BL/2 Unidirectional / mode Q0 Q1 Unidirectional /Free Running mode Q0 Q1 : RDA LAL EMRS RDA CL+BL/2 EMRS l RSC DLL EMRS DLL /65

48 (, BL = 4) TC59LM836DKG-33, I RSC = 7 cycles 15 Command WRA LAL DESL RDA MRS DESL RDA or WRA LAL Address UA LA Valid (opcode) UA LA Add. BA BA0="1" BA1="0" BA WL+BL/2 Unidirectional / mode D0 D1 D2 D3 Unidirectional /Free Running mode D0 D1 D2 D3 : WRA LAL EMRS RDA WL+BL/2 EMRS l RSC DLL EMRS DLL /65

49 (, BL = 4) Unidirectional / mode n 1 n n + 1 n + 2 I RC = 5 cycles I REFC = 19 cycles Command RDA LAL DESL WRA REF DESL RDA or WRA LAL or MRS or REF, Address, UA LA I RCD = 1 cycle I RAS = 4 cycles I RCD = 1 cycle Q0 Q1 Q2 Q3 Unidirectional /Free Running mode I RC = 5 cycles I REFC = 19 cycles Command RDA LAL DESL WRA REF DESL RDA or WRA LAL or MRS or REF, Address, UA LA I RCD = 1 cycle I RAS = 4 cycles I RCD = 1 cycle : Q0 Q1 Q2 Q3 I REFC 19 t REFI t REFI 8 t 1 t 2 t 3 t 7 t 8 WRA REF WRA REF WRA REF WRA REF WRA REF t REFI = Total time of 8 Refresh cycle 8 8 Refresh cycle t 1 + t 2 + t 3 + t 4 + t 5 + t 6 + t 7 + t 8 = 8 t REFI /65

50 Unidirectional / mode m 1 m m + 1 I RCD = 1 cycle I REFC Command WRA REF DESL t FPDL (min) t FPDL (max) Auto Refresh PD t QPDH Self Refresh Entry I *2 PDV I CKD Qx : PD t FPDL (min) t FPDL (max) l PDV PD t FPDL (max) l PDV 3. PD REF l CKD 4. WRA LAL REF (WL)+2 Unidirectional / mode m 1 m m + 1 m + 2 n 1 n n + 1 p 1 p Command *2 I REFC I REFC Command (1st) *5 Command (2nd) *5 DESL *3 WRA *4 REF *4 DESL RDA *6 LAL *6 I RCD = 1 cycle I RCD = 1 cycle PD t PDEX I LOCK Self-Refresh Exit 2. PD : PD I REFC DESL I REFC 6. (RDA + LAL) I LOCK /65

51 Unidirectional /Free Running mode m 1 m m + 1 I RCD = 1 cycle I REFC Command WRA REF DESL PD t FPDL (min) t FPDL (max) t QPDH Auto Refresh Self Refresh Entry I *2 PDV I CKD Qx : PD t FPDL (min) t FPDL (max) l PDV PD t FPDL (max) l PDV 3. PD REF l CKD Unidirectional /Free Running mode m 1 m m + 1 m + 2 n 1 n n + 1 p 1 p Command *2 I REFC I REFC Command (1st) *5 Command (2nd) *5 DESL *3 WRA *4 REF *4 DESL RDA *6 LAL *6 I RCD = 1 cycle I RCD = 1 cycle PD t PDEX I LOCK 2. PD Self-Refresh Exit : PD I REFC DESL I REFC 6. (RDA + LAL) I LOCK 7. DLL /65

52 Network FCRAM TM FCRAM TM Fast Cycle Random Access Memory FCRAM TM : & CS FN : PD PD PD SDRAM CKE PD & : CS & FN CS FN FCRAM TM CS FN 2 : BA0 & BA1 BA0 BA1 RDA WRA (MRS EMRS) BA0 BA1 #0 0 0 #1 1 0 #2 0 1 #3 1 1 : A0~A13 RDA WRA LAL A0~A13 I/O 36 A0~A13 A0~A /65

53 : 0~35 TC59LM836DKG-33, / 0 35 / : L U L U L L 0 17 U U (1) Unidirectional / / / NOP (2) Unidirectional / Free running / / Pin to pin : VDD VD VSS VSSQ VDD VSS VD VSSQ : VREF VREF /65

54 TC59LM836DKG (1 + 2 = RDA + LAL) / RDA RDA ( ) LAL / ( ) LAL CAS CAS RDA lrc (1 + 2 = WRA + LAL) / WRA WRA ( ) LAL / ( ) LAL CAS 1 LAL (VW) CAS WRA lrc (1 + 2 = WRA + REF) TC59LM836DKG SDRAM WRA REF WRA WRA ( ) LAL REF lrefc 3.9µs 8 400ns 3.2µs(8 400ns) 8 (1 + 2 = WRA + REF with PD = L ) WRA REF tfpdl PD 3.9µs lrefc DESL lckd PD PD DESL High DESL lrefc lrefc 1 ( PD = L ) PD PD PD High lpda DESL /65

55 (1 + 2 = RDA + MRS) TC59LM836DKG-33,-40 RDA MRS RDA RDA ( ) LAL MRS A0~A13 BA0 BA1 TC59LM836DKG MRS BA0 BA1 4 4 (R-1) (R-2) (R-3) CAS (R-4) 3 (E-1) DLL / DLL (E-2) (E-3) MRS OFF / (BA0, BA1) MRS MRS BA1 BA0 Mode Register Set 0 0 Regular MRS 0 1 Extended MRS 1 Reserved (R-1) (A2 A0) A2 A0 2 4 A2 A1 A0 BURST LENGTH Reserved words words Reserved 1 Reserved (R-2) (A3) A3 0 A A3 BURST TYPE 0 Sequential 1 Interleave /65

56 (+1) CAS Latency = 4 (Free Running mode) Command RDA LAL Data 0 Data 1 Data 2 Data 3 Addressing sequence for Sequential mode DATA ACCESS ADDRESS BURST LENGTH Data 0 n Data 1 n + 1 Data 2 n + 2 Data 3 n ( LA0) LA0 LA1 4 ( LA1, LA0) LA1 LA2 Addressing sequence for Interleave mode DATA ACCESS ADDRESS BURST LENGTH Data 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 1 A8 A7 A6 A5 A4 A3 A2 A1 A 0 Data 2 A8 A7 A6 A5 A4 A3 A2 A 1 A0 Data 3 A8 A7 A6 A5 A4 A3 A2 A 1 A (R-3) CAS (A6 A4) RDA LAL CAS LAL CAS 1 A6 A5 A4 CAS LATENCY Reserved Reserved Reserved Reserved Reserved (R-4) (A7) 0 (R-5) (A8 A13) /65

57 (E-1) DLL (A0) DLL A0 0 DLL (E-2) (A1 A4) 3 A2 A1 A4 A3 A4 A3 A2 A1 OUTPUT DRIVER IMPEDANCE CONTROL Normal Output Driver Strong Output Driver Weak Output Driver Reserved (E-3) (A6 / A5) 2 (1) Unidirectional / (2) Unidirectional / Free running A6 A5 STROBE SELECT 0 0 Reserved 0 1 Reserved 1 0 Unidirectional / mode 1 1 Unidirectional /Free running mode (E-4) (A7 A13) /65

58 IEEE TAP (the serial boundary scan test access port) TAP TCK VSS VDD (TCK ) TCK TMS TDI TDO TCK TAP TCK V SS V DD TCK TMS Test-Logic-Reset TDI TCK TAP TDI TDI ( ) TCK TDO IR [ 2 : 0 ] 3 5 (EXTEST Sample-Z Sample Bypass ID code). ID IDR [ 31 : 0 ] 32 Revision TOSHIBA ID BR 1 TDI TDO BSR [ 62 : 0 ] 63 (BSC) TDI TDO TAP IR2 IR1 IR EXTEST BSC ID CODE ID code SAMPLE Z BSC RESERVED SAMPLE BSC BSC RESERVED RESERVED BYPASS TDI TDO : TDI (IR0) /65

59 ID BIT # TOSHIBA ID BIT BIT 0 U B U B T B T C R C R D P P D N E N11 U 39 E M3 A4 40 F M11 A3 41 F2 L 12 L10 A2 42 G3 / 13 L11 A1 43 H3 14 K10 A0 44 H2 /PD 15 K11 A10 45 J2 A12 16 J10 BA1 46 J3 A11 17 J11 BA0 47 K2 A9 18 G10 A13 48 K3 A8 19 G11 FN 49 L2 A7 20 H10 /CS 50 L3 A6 21 F11 L 51 M2 A5 22 F N2 U 23 E N E P D P D R C C R B T T U U /65

60 TMS = 1 Test Logic - Reset TMS = 0 TMS = 0 TMS = 1 TMS = 1 TMS = 1 Run Test / Idle Select DR - Scan Select IR - Scan TMS = 0 TMS = 0 Capture - DR TMS = 1 Capture - IR TMS = 0 TMS = 1 TMS = 0 TMS = 0 Shift - DR Shift - IR TMS = 0 TMS = 1 TMS = 1 TMS = 1 Exit1 - DR Exit1 - IR TMS = 1 TMS = 0 TMS = 0 TMS = 0 Pause - DR Pause - IR TMS = 0 TMS = 1 TMS = 1 TMS = 0 Exit2 - DR TMS = 0 Exit2 - IR TMS = 1 TMS = 1 Update - DR Update - IR TMS = 1 TMS = 1 TMS = 0 TMS = 0 : 1. Test-Logic-Reset TMS 5 High 2. TDO (Shift-DR Shift-IR) /65

61 TAP DC I LO I I V IH V IL (TDO ) (TCK TMS TDI ) (TCK TMS TDI ) (TCK TMS TDI ) µa V OUT =0 to V DD V IN = 1.7V to V DD µa V IN = 0 to 0.7V µa V REF +0.4 V DD +0.2 V 0.1 V REF 0.4 V V OH V OL (TDO ) I OH = 2 ma 1.5 V DD V (TDO ) I OL = 2 ma 0.45 V TAP AC ( VDD = 2.5V ± 0.125V, VD = 1.4V ~ 1.9V, T CASE = 0 ~ 85 C) t THTH TCK 50 t THTL TCK 20 t TLTH TCK 20 t MVTH TMS 10 t THMX TMS 10 t CS 10 t CH 10 ns t DVTH TDI 10 t THDX TDI 10 t TLQV TCK 20 t TLQX TCK 0 t TLQLZ TCK 5 t TLQHZ TCK /65

62 TAP AC TDO Z = 50 Ω 1.8V / 0.0V 2ns R L = 50 Ω V L = 0.9V 0.9V 0.9V TAP t THTH t THTL t TLTH TCK t MVTH t THMX TMS t DVTH t THDX TDI t CS t CH Capture Data t TLQLZ t TLQX t TLQV t TLQHZ TDO /65

63 P-TFBGA BZ SA SB S S 0.1 S SAB 1.2MAX MIN INDEX A B C D E F G A H J K L M N P R T U V B : 0.30g ( ) /65

64 Rev.1.3 ( ) TC59LM836DMB ( ) -30 ( 333MHz clock / 666Mbps )version /65

65 030519TBA /65

( ) PIN A0~A14 NAME TC59LM814CFT TC59LM806CFT BA0, BA1 0~7 ( 8) 0~15 ( 16) CS FN PD, ( 8) U/L ( 16) V DD V SS V D V SSQ V REF NC 1, NC VD VD 5 N

( ) PIN A0~A14 NAME TC59LM814CFT TC59LM806CFT BA0, BA1 0~7 ( 8) 0~15 ( 16) CS FN PD, ( 8) U/L ( 16) V DD V SS V D V SSQ V REF NC 1, NC VD VD 5 N MOS CMOS 256M FCRAM1 4,194,304 4 16 8,388,608 4 8 TC59LM814/06CFT CMOS 268,435,456 (FCRAM TM ) 2 TC59LM814CFT 4,194,304 4 16 TC59LM806CFT 8,388,608 4 8 400M / FCRAM TM DDR SDRAM TC59LM814/06CFT t CK t

More information

R1LV0416Dシリーズ データシート

R1LV0416Dシリーズ データシート Wide Temperature Range Version 4M SRAM (256-kword 16-bit) RJJ03C0237-0100 Rev. 1.00 2007.05.24 262,144 16 4M RAM TFT 44 TSOP II 48 CSP 0.75mm 3.0V 2.7V 3.6V 55/70ns max 3µW typ V CC =3.0V 2CS 40 +85 C

More information

R1RW0408D シリーズ

R1RW0408D シリーズ お客様各位 カタログ等資料中の旧社名の扱いについて 2010 年 4 月 1 日を以って NEC エレクトロニクス株式会社及び株式会社ルネサステクノロジが合併し 両社の全ての事業が当社に承継されております 従いまして 本資料中には旧社名での表記が残っておりますが 当社の資料として有効ですので ご理解の程宜しくお願い申し上げます ルネサスエレクトロニクスホームページ (http://www.renesas.com)

More information

R1LV1616H-I シリーズ

R1LV1616H-I シリーズ お客様各位 カタログ等資料中の旧社名の扱いについて 2010 年 4 月 1 日を以って NEC エレクトロニクス株式会社及び株式会社ルネサステクノロジが合併し 両社の全ての事業が当社に承継されております 従いまして 本資料中には旧社名での表記が残っておりますが 当社の資料として有効ですので ご理解の程宜しくお願い申し上げます ルネサスエレクトロニクスホームページ (http://www.renesas.com)

More information

R1RW0416DI シリーズ

R1RW0416DI シリーズ お客様各位 カタログ等資料中の旧社名の扱いについて 2010 年 4 月 1 日を以って NEC エレクトロニクス株式会社及び株式会社ルネサステクノロジが合併し 両社の全ての事業が当社に承継されております 従いまして 本資料中には旧社名での表記が残っておりますが 当社の資料として有効ですので ご理解の程宜しくお願い申し上げます ルネサスエレクトロニクスホームページ (http://www.renesas.com)

More information

R1RP0416D シリーズ

R1RP0416D シリーズ お客様各位 カタログ等資料中の旧社名の扱いについて 2010 年 4 月 1 日を以って NEC エレクトロニクス株式会社及び株式会社ルネサステクノロジが合併し 両社の全ての事業が当社に承継されております 従いまして 本資料中には旧社名での表記が残っておりますが 当社の資料として有効ですので ご理解の程宜しくお願い申し上げます ルネサスエレクトロニクスホームページ (http://www.renesas.com)

More information

MSM56V16160F

MSM56V16160F 1 電子デバイス MSM56V16160F 2-Bank 524,288-Word 16-Bit SYNCHRONOUS DYNAMIC RAM 2001 2 2001 1 MSM56V16160F CMOS 2 524,288 16 RAM 3.3V LVTTL 4 CMOS 1 2 524,288 16 3.3V 0.3V LVTTL LVTTL 4096 /64ms Latency 1 2 3

More information

R1EV5801MBシリーズ データシート

R1EV5801MBシリーズ データシート 1M EEPROM (128-kword 8-bit) Ready/Busy and function R10DS0209JJ0100 Rev.1.00 131072 8 EEPROM ROM MONOS CMOS 128 2.7V 5.5V 150ns (max) @ Vcc=4.5V 5.5V 250ns(max) @ Vcc=2.7V 5.5V 20mW/MHz (typ) 110µW (max)

More information

HN58V256Aシリーズ/HN58V257Aシリーズ データシート

HN58V256Aシリーズ/HN58V257Aシリーズ データシート HN58V256A HN58V257A 256k EEPROM (32-kword 8-bit) Ready/Busy and RES function (HN58V257A) RJJ03C0132-0600 Rev. 6.00 2007. 05. 24 HN58V256A HN58V257A 32768 8 EEPROM ROM MNOS CMOS 64 3V 2.7 5.5V 120ns (max)

More information

HN58C256A シリーズ/HN58C257A シリーズ データシート

HN58C256A シリーズ/HN58C257A シリーズ データシート HN58C256A HN58C257A 256k EEPROM (32-kword 8-bit) Ready/Busy and RES function (HN58C257A) RJJ03C0133-0600Z Rev. 6.00 2006. 10. 26 HN58C256A HN58C257A 32768 8 EEPROM ROM MNOS CMOS 64 5V±10% 85ns/100ns (max)

More information

XAPP858 - High-Performance DDR2 SDRAM Interface In Virtex-5 Devices

XAPP858 - High-Performance DDR2 SDRAM Interface In Virtex-5 Devices XAPP858 (v1.1) 2007 1 9 : Virtex-5 FPGA Virtex-5 DDR2 SDRAM : Karthi Palanisamy Maria George (v1.1) DDR2 SDRAM Virtex -5 I/O ISERDES (Input Serializer/Deserializer) ODDR (Output Double Data Rate) DDR2

More information

MAX IIデバイスのIEEE (JTAG)バウンダリ・スキャン・テスト

MAX IIデバイスのIEEE (JTAG)バウンダリ・スキャン・テスト 3. MAX II IEEE 49. JTAG MII54-.6 PCB PCB Bed-of-nails PCB 98 Joint Test Action Group JTAG IEEE Std. 49. BST PCB BST 3 3. IEEE Std. 49. Serial Data In Boundary-Scan Cell IC Pin Signal Serial Data Out Core

More information

N12866N2P-H.PDF

N12866N2P-H.PDF 16Mx64bits PC133 SDRAM SO DIMM Based on 16Mx16 SDRAM with LVTTL, 4 banks & 8K Refresh (16M x 16bit) /. / 1 A0 ~ A12 BA0, BA1 CK0, CK1 CKE0 /S0 /RAS /CAS /WE DQM0 ~ DQM7 DQ0 ~ DQ63 SA0~2 SDA SCL VCC 3.3

More information

MSM51V18165F

MSM51V18165F OKI 2008 10 1 OKI OKI OKI 2008 10 1 OKI 193-8550 550-1 http://www.okisemi.com/jp/ OKI MSM51V18165F FJDD51V18165F-03 2005 6 3 1,048,576-Word 16-Bit DYNAMIC RAM : EDO MSM51V18165F CMOS 1,048,576 16 4 2 CMOS

More information

MSM514400E/EL

MSM514400E/EL 1 1,08,576-Word x -BiYNAMIC RAM : 2001 1 CMOS 1,08,576 2 CMOS 26/20 SOJ 26/20 TSOP L!"1,08,576!"5V 10%!" : TTL!" : TTL!" : 1,02 16ms 1,02 128ms L-!"!"CAS RAS RAS!"!" : 26/20 300mil SOJ (SOJ26/20-P-300-1.27)

More information

PIN S 5 K 0 K 1 K 2 K 3 K 4 V DD V 0 V 1 V 2 V SS OSC SEG 32 SEG 31 SEG 30 SEG 29 SEG 28 SEG 27 SEG 26 SEG 25 SEG 24 SEG 23 SEG 22 SEG 21 SEG 20 SEG 1

PIN S 5 K 0 K 1 K 2 K 3 K 4 V DD V 0 V 1 V 2 V SS OSC SEG 32 SEG 31 SEG 30 SEG 29 SEG 28 SEG 27 SEG 26 SEG 25 SEG 24 SEG 23 SEG 22 SEG 21 SEG 20 SEG 1 1/3 1/4 LCD NJU6535 LCD 1/3 1/4 LCD key(scan 6 Scan 5) CPU 3 4 42 41 1/3 126 1/4 164 LED NJU6535FH1 LCD 42 126 164 30 Scan 6 Scan 5 1/2, 1/3 LED 4 (,,, CS) (8 ) 4.5 ~ 5.5V 5.5V QFP64-H1 CMOS ( :P) -1-

More information

R1RP0416DIシリーズデータシート

R1RP0416DIシリーズデータシート Wide Temperature Version 4M High Speed SRAM (256-kword 16-bit) データシート RJJ03C0097-0201 Rev.2.01 概要 R1RP0416DI シリーズは 256k ワード 16 ビット構成の 4M ビット高速スタティック RAM です CMOS(6 トランジスタメモリセル ) プロセス技術を採用し, 高密度, 高性能, 低消費電力を実現しました

More information

Arria GXデバイスのIEEE (JTAG)バウンダリ・スキャン・テスト

Arria GXデバイスのIEEE (JTAG)バウンダリ・スキャン・テスト 3. Arria GX IEEE 49. (JTAG) AGX523-. PCB PCB Bed-of-nails PCB 98 Joint Test Action Group (JTAG) IEEE Std. 49. (BST) PCB BST 3 3. IEEE Std. 49. Serial Data In Boundary-Scan Cell IC Pin Signal Serial Data

More information

AN6591FJM

AN6591FJM IC AN6591FJM PHS, PLL IC AN6591FJMPHSIF PLL IC QFN (Quad flat non-leaded PKG) (0.63) 34 44 R0.30 6.20±0.10 (6.00) 33 23 1 11 (0.63) 22 12 3-C 0.50 (6.00) 6.20±0.10 0.20±0.10 0.80 max Unit : mm, PLL,, APC

More information

Test

Test 1 39 41 199 Data Sheet Rev. 1.0 11.02.2003 200-pin DDR SDRAM Module SO-DIMM 1024MB DDR PC 2100 in COB 200-64- Small Outline Dual-In-Line. DRAM DDR- SDRAM : MICRON MT 46V 64M8 T17B V DD 2,5V ±0.2V, V DD

More information

IEEE (JTAG) Boundary-Scan Testing for Stratix II & Stratix II GX Devices

IEEE (JTAG) Boundary-Scan Testing for Stratix II & Stratix II GX Devices 4. Stratix II Stratix II GX IEEE 49. (JTAG) SII529-3. PCB PCB Bed-of-nails PCB 98 Joint Test Action Group (JTAG) IEEE Std. 49. (BST) PCB BST 4-4-. IEEE Std. 49. Serial Data In Boundary-Scan Cell IC Pin

More information

R1LV0816ASB データシート

R1LV0816ASB データシート R1LV0816ASB 5SI, 7SI 8Mb Advanced LPSRAM (512k word x 16bit) RJJ03C0292-0100 Rev.1.00 2009.11.30 概 要 R1LV0816ASB は シリコンゲート 0.15µm CMOS プロセス 技 術 を 用 いた 524,288 語 16 ビット 構 成 を 持 ち 単 一 電 源 で 動 作 する 非 同 期

More information

RMLV0816BGBG Datasheet

RMLV0816BGBG Datasheet 8Mbit 低 消 費 電 力 SRAM (512k word 16bit) R10DS0229JJ0200 Rev.2.00 概 要 RMLV0816BGBG は 524,288 ワード 16 ビット 構 成 の 8M ビットスタティック RAM です Advanced LPSRAM 技 術 を 採 用 し 高 密 度 高 性 能 低 消 費 電 力 を 実 現 しております したがって RMLV0816BGBG

More information

RMWV3216A Series Datasheet

RMWV3216A Series Datasheet 32Mbit 低 消 費 電 力 SRAM (2M word 16bit) R10DS0259JJ0100 Rev.1.00 概 要 RMWV3216A シリーズは 2,097,152 ワード 16 ビット 構 成 の 32M ビットスタティック RAM です Advanced LPSRAM 技 術 を 採 用 し 高 密 度 高 性 能 低 消 費 電 力 を 実 現 しております したがって RMWV3216A

More information

Untitled

Untitled R1LV0816ABG -5SI, 7SI 8Mb Advanced LPSRAM (512k word x 16bit) RJJ03C0295-0100 Rev.1.00 2009.12.14 R1LV0816ABG 0.15µm CMOS 524,288 16 RAM TFT R1LV0816ABG R1LV0816ABG 7.5mm 8.5mm BGA (f-bga [0.75mm, 48 ])

More information

Cyclone IIIデバイスのI/O機能

Cyclone IIIデバイスのI/O機能 7. Cyclone III I/O CIII51003-1.0 2 Cyclone III I/O 1 I/O 1 I/O Cyclone III I/O FPGA I/O I/O On-Chip Termination OCT Quartus II I/O Cyclone III I/O Cyclone III LAB I/O IOE I/O I/O IOE I/O 5 Cyclone III

More information

mbed祭りMar2016_プルアップ.key

mbed祭りMar2016_プルアップ.key 1 2 4 5 Table 16. Static characteristics (LPC1100, LPC1100L series) continued T amb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ [1] Max Unit Standard port pins, RESET

More information

R1WV6416R データシート

R1WV6416R データシート 64Mb Advanced LPSRAM (4M word x 16bit / 8M word x 8bit) 概要 RJJ03C0287-0100 Rev.1.00 2009.05.07 は シリコンゲート 0.15µm CMOS プロセス技術を用いた 4,194,304 語 16 ビット構成を持ち 単一電源で動作する非同期式のスタティク RAM です メモリセルに新規 TFT 技術を用い 高密度かつ低消費電力を実現したデバイスです

More information

橡EN1165.PDF

橡EN1165.PDF G780(7ZMMP-KK F1C) BIOS Setup 1 G780(7ZMMP-KK F1C) 2 G780(7ZMMP-KK F1C) 3 G780(7ZMMP-KK F1C) 4 G780(7ZMMP-KK F1C) 1st Boot Device 2nd Boot Device 3rd Boot Device S.M.A.R.T. for Hard Disks BootUp Num-Lock

More information

NJU3555 NJU

NJU3555 NJU 1/16 LCD NJU6573 NJU6573 16 100 LCD 16 100 1/16 1600 LCD NJU6573 LCD CMOS 16 100 1/5 2MHz Max. CR, 16 V DD = 2.4V3.6V P-Sub LQFP144 20.0mm x 20.0mm t=1.7mm(max) 0.50mm pitch - 1 - NJU3555 NJU6573-2 - NJU3555

More information

AN 100: ISPを使用するためのガイドライン

AN 100: ISPを使用するためのガイドライン ISP AN 100: In-System Programmability Guidelines 1998 8 ver.1.01 Application Note 100 ISP Altera Corporation Page 1 A-AN-100-01.01/J VCCINT VCCINT VCCINT Page 2 Altera Corporation IEEE Std. 1149.1 TCK

More information

R1LV3216R データシート

R1LV3216R データシート お客様各位 カタログ等資料中の旧社名の扱いについて 2010 年 4 月 1 日を以って NEC エレクトロニクス株式会社及び株式会社ルネサステクノロジが合併し 両社の全ての事業が当社に承継されております 従いまして 本資料中には旧社名での表記が残っておりますが 当社の資料として有効ですので ご理解の程宜しくお願い申し上げます ルネサスエレクトロニクスホームページ (http://www.renesas.com)

More information

MSM51V18165F

MSM51V18165F 1 電子デバイス MSM51V1165F 1,04,576-Word 16-Bit DYNAMIC RAM : EDO 機能付き高速ページモード 2000 10 MSM51V1165F CMOS 1,04,576 16 4 2 CMOS 42 SOJ 50/44 TSOP 1,04,576 16 3.3V 0.3V LVTTL LVTTL 1024 /16ms EDO!"# $"# $"# 42 400mil

More information

RMLV0416E Series Datasheet

RMLV0416E Series Datasheet 4Mbit 低消費電力 SRAM (256-kword 16-bit) R10DS0205JJ0100 Rev.1.00 概要 は 262,144 ワード 16 ビット構成の 4M ビットスタティック RAM です Advanced LPSRAM 技術を採用し 高密度 高性能 低消費電力を実現しております したがって RMLV0416E シリーズは バッテリバックアップシステムに最適です パッケージの種類は

More information

16-Bit, Serial Input Multiplying Digital-to-Analog Converter (Rev. B

16-Bit, Serial Input Multiplying Digital-to-Analog Converter (Rev. B DAC8811 www.tij.co.jp ± ± µ ± µ ± V REF CS Power-On Reset DAC8811 D/A Converter 16 DAC Register 16 R FB I OUT CLK SDI Shift Register GND DAC8811C ±1 ±1 MSOP-8 (DGK) 4to 85 D11 DAC8811ICDGKT DAC8811C ±1

More information

XC9500 ISP CPLD JTAG Port 3 JTAG Controller In-System Programming Controller 8 36 Function Block Macrocells to 8 /GCK /GSR /GTS 3 2 or 4 Blocks FastCO

XC9500 ISP CPLD JTAG Port 3 JTAG Controller In-System Programming Controller 8 36 Function Block Macrocells to 8 /GCK /GSR /GTS 3 2 or 4 Blocks FastCO - 5ns - f CNT 25MHz - 800~6,400 36~288 5V ISP - 0,000 / - / 36V8-90 8 - IEEE 49. JTAG 24mA 3.3V 5V PCI -5-7 -0 CMOS 5V FastFLASH XC9500 XC9500CPLD 0,000 / IEEE49. JTAG XC9500 36 288 800 6,400 2 XC9500

More information

untitled

untitled : SOU1AP2011003 2011/12/25 & Copyright 2010, Toshiba Corporation. : SOU1AP2011003 1. 2.CMOS 3.CMOS 4.CMOS 5.CMOS 6. 2 : SOU1AP2011003 3 : SOU1AP2011003 NAND,OR,, IC 1A 1 1B 2 14 13 V CC 4B 1Y 2A 2B 3 4

More information

untitled

untitled COPAL ELECTRONICS 32 (DP) DP INC 2 3 3 RH RL RWB 32 C S U/D INC U/D CS 2 2 DP7114 32 SOIC CMOS 2.5 V - 6.0 V / 10 kω 50 kω 100 kω TSSOP MSOP /BFR INC / U/D RH RoHS GND RWB RL CS VCC 2017 6 15 1 : R = 2

More information

DS90LV V or 5V LVDS Driver/Receiver (jp)

DS90LV V or 5V LVDS Driver/Receiver (jp) DS90LV019 DS90LV019 3.3V or 5V LVDS Driver/Receiver Literature Number: JAJS563 DS90LV019 LVDS 1 / DS90LV019 Low Voltage Differential Signaling (LVDS) 1 CMOS / DS90LV019 EIA-644 IEEE1596.3 (SCI LVDS) 2

More information

AD8212: 高電圧の電流シャント・モニタ

AD8212: 高電圧の電流シャント・モニタ 7 V typ 7 0 V MSOP : 40 V+ V SENSE DC/DC BIAS CIRCUIT CURRENT COMPENSATION I OUT COM BIAS ALPHA 094-00 V PNP 0 7 V typ PNP PNP REV. A REVISION 007 Analog Devices, Inc. All rights reserved. 0-9 -- 0 40

More information

R1LP5256E Series Datashet

R1LP5256E Series Datashet 256Kb Advanced LPSRAM (32k word x 8bit) R10DS0070JJ0100 Rev.1.00 概要 R1LP5256E シリーズは シリコンゲート 0.15µm CMOS プロセス技術を用いた 32,768 語 8 ビット構成を持ち 単一電源で動作する非同期式のスタティク RAM です メモリセルに TFT 技術を用い 高密度かつ低消費電力を実現したデバイスです

More information

HN58X2402SFPIAG/HN58X2404SFPIAG

HN58X2402SFPIAG/HN58X2404SFPIAG お客様各位 カタログ等資料中の旧社名の扱いについて 2010 年 4 月 1 日を以って NEC エレクトロニクス株式会社及び株式会社ルネサステクノロジが合併し 両社の全ての事業が当社に承継されております 従いまして 本資料中には旧社名での表記が残っておりますが 当社の資料として有効ですので ご理解の程宜しくお願い申し上げます ルネサスエレクトロニクスホームページ (http://www.renesas.com)

More information

Microsoft Word - AK2300-MS0997-J-00_ doc

Microsoft Word - AK2300-MS0997-J-00_ doc AK2300 A-Law -law14bitpcm(16bit ) A/D D/A A-law/μ-law GST VFTN VR AMPT AAF SMF A/D CODEC Core D/A PCM I/F DIF0 DIF1 MUTEN DX DR FS BCLK VREF BGREF Internal Main Clock PLLC VDD VSS LVDD Power Down AK2300

More information

RNA51xxシリーズ データシート

RNA51xxシリーズ データシート RNxx CMOS system RESET IC R0DS0090JJ000 Rev..00 0.0.0 RNxx. V,.6 V,.7 V,.8 V,.9 V,.0 V,. V,. V,. V,.6 V,.0 V, ±% CMOS, (0.7 μ),, ( MΩ) (RNxx) CMOS (RNBxx). V,.6 V,.7 V,.8 V,.9 V,.0 V,. V,. V,. V,.6 V,.0

More information

DAC121S101/DAC121S101Q 12-Bit Micro Power, RRO Digital-to-Analog Converter (jp)

DAC121S101/DAC121S101Q 12-Bit Micro Power, RRO Digital-to-Analog Converter (jp) DAC121S101 DAC121S101/DAC121S101Q 12-Bit Micro Power, RRO Digital-to-Analog Converter Literature Number: JAJSA89 DAC121S101 12 D/A DAC121S101 12 D/A (DAC) 2.7V 5.5V 3.6V 177 A 30MHz 3 SPI TM QSPI MICROWIRE

More information

HN58X2502/HN58X2504I

HN58X2502/HN58X2504I お客様各位 カタログ等資料中の旧社名の扱いについて 2010 年 4 月 1 日を以って NE エレクトロニクス株式会社及び株式会社ルネサステクノロジが合併し 両社の全ての事業が当社に承継されております 従いまして 本資料中には旧社名での表記が残っておりますが 当社の資料として有効ですので ご理解の程宜しくお願い申し上げます ルネサスエレクトロニクスホームページ (http://www.renesas.com)

More information

LM9822 3 Channel 42-Bit Color Scanner Analog Front End (jp)

LM9822 3 Channel 42-Bit Color Scanner Analog Front End (jp) LM9822 LM9822 3 Channel 42-Bit Color Scanner Analog Front End Literature Number: JAJS680 LM9822 3 42 LM9822 AFE CIS CCD CDS / LM9822 14 6MHz ADC 600 / CCD CDS CCD CIS TTL/CMOS 14 6MHz 5V 5% I/O 3.3V 10%

More information

untitled

untitled 1.0 1. Display Format 8*2 Character 2. Power Supply 3.3V 3. Overall Module Size 30.0mm(W) x 19.5mm(H) x max 5.5mm(D) 4. Viewing Aera(W*H) 27.0mm(W) x 10.5mm(H) 5. Dot Size (W*H) 0.45mm(W) x 0.50mm(H) 6.

More information

2

2 REVISION 2.85(6).I 2 3 4 5 8 24 32 37 83 87 88 88 89 90 1 91 1 6 7 8 KDC200 ユーザーマニュアル 1.1 同梱物 本機のパッケージには 以下の物が同梱されています 1 2 3 4 本体 バーコード Data Collector 1 台 USB ケーブル 1本 ネックストラップ 1 本 ソフトウェアとユーザーマニュアルを含む CD-ROM

More information

untitled

untitled H Phase & Enable (UVLO) V DD =2.55.5V =3.08.0V Io=400mA I DD =200uA typ. (Mode Select) 2 Phase & Enable (ALL L ) STB L (UVLO) Alarm CMOS SSOP20-C3 - - (Ta=25 C) (Ta=25) - 2 - - 3 - - 4 - - 5 - OUTA IN2B

More information

PDW-75MD

PDW-75MD 3-270-633-02(1) PDW-75MD 2007 Sony Corporation m a b c 2 ... 2 6 6... 8... 8 1... 10... 10... 12... 13... 13... 19... 23 2... 25... 26... 27... 27... 28... 29... 29... 29... 30... 31... 33 3... 34... 34...

More information

DS90CP04 1.5 Gbps 4x4 LVDS Crosspoint Switch (jp)

DS90CP04 1.5 Gbps 4x4 LVDS Crosspoint Switch (jp) 1.5 Gbps 4x4 LVDS Crosspoint Switch Literature Number: JAJS984 1.5Gbps 4 4 LVDS 4 4 (LVDS) ( ) 4 4:1 4 1 MODE 4 42.5Gb/s LVDS 20010301 33020 23900 11800 ds200287 2007 12 Removed preliminary. Removed old

More information

1 138

1 138 5 1 2 3 4 5 6 7 8 1 138 BIOS Setup Utility MainAdvancedSecurityPowerExit Setup Warning Item Specific Help Setting items on this menu to incorrect values may cause your system to malfunction. Select 'Yes'

More information

R1LV1616Rシリーズ

R1LV1616Rシリーズ お客様各位 カタログ等資料中の旧社名の扱いについて 2 年 4 月 1 日を以って NEC エレクトロニクス株式会社及び株式会社ルネサステクノロジが合併し 両社の全ての事業が当社に承継されております 従いまして 本資料中には旧社名での表記が残っておりますが 当社の資料として有効ですので ご理解の程宜しくお願い申し上げます ルネサスエレクトロニクスホームページ (http://www.renesas.com)

More information

...5...6...7...8...9...10...12...12...12...18...21...23...23...23...24...24...24...24...25...26...26...26...27...33...33...33...33...33...34...35...36

...5...6...7...8...9...10...12...12...12...18...21...23...23...23...24...24...24...24...25...26...26...26...27...33...33...33...33...33...34...35...36 REVISION 2.85(6).H ...5...6...7...8...9...10...12...12...12...18...21...23...23...23...24...24...24...24...25...26...26...26...27...33...33...33...33...33...34...35...36...36...36...37...38...39 2 ...39...42...42...42...43...43...44...45...46...46...47...48...48...49...50...51...52...53...55...56...56...58...60...62...64...66...68...68...69...71...71...71...71...72...72...73...74...74...74...74

More information

ADC121S Bit, ksps, Diff Input, Micro Pwr Sampling ADC (jp)

ADC121S Bit, ksps, Diff Input, Micro Pwr Sampling ADC (jp) ADC121S625 ADC121S625 12-Bit, 50 ksps to 200 ksps, Differential Input, Micro Power Sampling A/D Converter Literature Number: JAJSAB8 ADC121S625 12 50kSPS 200kSPS A/D ADC121S625 50kSPS 200kSPS 12 A/D 500mV

More information

HardCopy IIIデバイスの外部メモリ・インタフェース

HardCopy IIIデバイスの外部メモリ・インタフェース 7. HardCopy III HIII51007-1.0 Stratix III I/O HardCopy III I/O R3 R2 R SRAM RII+ RII SRAM RLRAM II R HardCopy III Stratix III LL elay- Locked Loop PLL Phase-Locked Loop On-Chip Termination HR 4 36 HardCopy

More information

電源監視回路

電源監視回路 TPS3820-xx,TPS3823-xx TPS3824-xx,TPS3825-xx TPS3828-xx www.tij.co.jp µ TYPICAL APPLICATION TPS3820, TPS3823, TPS3828: DBV PACKAGE (TOP VIEW) GND MR 1 2 3 5 4 VDD WDI TPS3824: DBV PACKAGE (TOP VIEW) 1 5

More information

REVISION 2.85(6).I 1

REVISION 2.85(6).I 1 REVISION 2.85(6).I 1 2 3 4 5 6 7 8 KDC300 ユーザーマニュアル 1.1 同梱物 本機のパッケージには 以下の物が同梱されています 1 2 3 4 本体 バーコード Data Collector 1 台 USB ケーブル 1本 ネックストラップ 1 本 ソフトウェアとユーザーマニュアルを含む CD-ROM 1枚 KTSync - XP, Vista,Windows7,

More information

TN-46-13

TN-46-13 はじめに テクニカルノート 高速 DDR SDRAM の互換性 はじめに このテクニカルノートでは DDR SDRAM デバイスの速度タイミングの違いを考察し Micron の高速グレード部品と低速グレード部品との互換性について説明します Micron DDR デバイスのタイミングは 異なる速度グレードの部品との互換性を最大限維持するように最適化されています そのため Micron のデータシートに記載されているタイミング特性は

More information

DS90LV011A 3V LVDS 1 回路入り高速差動出力ドライバ

DS90LV011A 3V LVDS 1 回路入り高速差動出力ドライバ 3V LVDS Single High Speed Differential Driver Literature Number: JAJS962 Single High Speed Differential Driver 19961015 23685 ds200149 Input Voltage changed to 3.6V from 5V Updated DC and AC typs basic

More information

HD74HCT564, HD74HCT574

HD74HCT564, HD74HCT574 ご注意 安全設計に関するお願い 1. 弊社は品質 信頼性の向上に努めておりますが 半導体製品は故障が発生したり 誤動作する場合があります 弊社の半導体製品の故障又は誤動作によって結果として 人身事故 火災事故 社会的損害などを生じさせないような安全性を考慮した冗長設計 延焼対策設計 誤動作防止設計などの安全設計に十分ご留意ください 本資料ご利用に際しての留意事項 1. 本資料は お客様が用途に応じた適切なルネサステクノロジ製品をご購入いただくための参考資料であり

More information

LT 低コスト、シャットダウン機能付き デュアルおよびトリプル300MHz 電流帰還アンプ

LT 低コスト、シャットダウン機能付き デュアルおよびトリプル300MHz 電流帰還アンプ µ µ LT1398/LT1399 V IN A R G 00Ω CHANNEL A SELECT EN A R F 3Ω B C 97.6Ω CABLE V IN B R G 00Ω EN B R F 3Ω 97.6Ω V OUT OUTPUT (00mV/DIV) EN C V IN C 97.6Ω R G 00Ω R F 3Ω 1399 TA01 R F = R G = 30Ω f = 30MHz

More information

LTC ビット、200ksps シリアル・サンプリングADC

LTC ビット、200ksps シリアル・サンプリングADC µ CBUSY ANALOG INPUT 10V TO 10V 2. 2. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 V DIG V ANA PWRD BUSY CS R/C TAG SB/BTC DATA EXT/INT DATACLK DGND SY 28 27 26 25 24 23 22 21 20 19 18 17 16 15 10µF 0.1µF SERIAL INTERFACE

More information

RNA52A10MM データシート

RNA52A10MM データシート RNAA0MM Dual CMOS system RESET IC R0DS009JJ000 (Previous code: RJJ0D0-000) Rev..00 0..9 RNAA0MM. CMOS. μa (typ) H MΩ o CMOS. ± 0 m % typ.. μa typ. CR MMPAK- 0 C ( ) RNAA0MMEL MMPAK- PLSP000JC-A MM EL (,000

More information

Triple 2:1 High-Speed Video Multiplexer (Rev. C

Triple 2:1 High-Speed Video Multiplexer (Rev. C www.tij.co.jp OPA3875 µ ± +5V µ RGB Channel OPA3875 OPA3875 (Patented) RGB Out SELECT ENABLE RED OUT GREEN OUT BLUE OUT 1 R G B RGB Channel 1 R1 G1 B1 X 1 Off Off Off 5V Channel Select EN OPA875 OPA4872

More information

5 1 2 3 4 5 6 7 8 9 10 1 Quick Boot 1st Boot Device 2nd Boot Device 3rd Boot Device Network Boot Initial Display Mode S.M.A.R.T. for Hard Disks BootUp Num-Lock Password Check CPU Serial Number System BIOS

More information

4

4 I/O 2AO 0/4-20mA / DC6-18V 16Bit Ver. 1.0.0 2 750-563 Copyright 2006 by WAGO Kontakttechnik GmbH All rights reserved. 136-0071 1-5-7 ND TEL 03-5627-2059 FAX 03-5627-2055 http://www.wago.co.jp/io/ WAGO

More information

AD5302/AD5312/AD5322: 2.5 ~ 5.5 V 電源、230 μA 消費電流、デュアル、レール to レール電圧出力の 8 / 10 / 12 ビット D/A コンバータ

AD5302/AD5312/AD5322: 2.5 ~ 5.5 V 電源、230 μA 消費電流、デュアル、レール to レール電圧出力の 8 / 10 / 12 ビット D/A コンバータ 2.5 5.5V 23µA to8/1/12 D/A AD532 18DAC 2 A 1LSB INL B.5LSB INL AD5312 11DAC 2 A 4LSB INL B 2LSB INL AD5322 112DAC 2 A 16LSB INL B 8LSB INL 1MSOP 3µA@5V 2nA@5V 5nA@3V 2.5 5.5V V REF V LDAC DAC to 1MSOP

More information

4

4 I/O 2AO DC0-10V/ 10V 16Bit Ver. 1.0.0 2 750-562 Copyright 2006 by WAGO Kontakttechnik GmbH All rights reserved. 136-0071 1-5-7 ND TEL 03-5627-2059 FAX 03-5627-2055 http://www.wago.co.jp/io/ WAGO Kontakttechnik

More information

DELPHINUS EQUULEUS 2019 NASA SLS FPGA ( ) DELPHINUS 2

DELPHINUS EQUULEUS 2019 NASA SLS FPGA ( ) DELPHINUS 2 30 1631158 1 29 () 1 DELPHINUS EQUULEUS 2019 NASA SLS FPGA ( 0.010.1 ) DELPHINUS 2 1 4 1.1............................................ 4 1.2 (Lunar Impact Flush)............................. 4 1.3..............................................

More information

Unidirectional Measurement Current-Shunt Monitor with Dual Comparators (Rev. B

Unidirectional Measurement Current-Shunt Monitor with Dual Comparators (Rev. B www.tij.co.jp INA206 INA207 INA208 INA206-INA208 INA206-INA208 V S 1 14 V IN+ V S 1 10 V IN+ OUT CMP1 IN /0.6V REF 2 3 1.2V REF 13 12 V IN 1.2V REF OUT OUT CMP1 IN+ 2 3 9 8 V IN CMP1 OUT CMP1 IN+ 4 11

More information

S1F77330 シリーズテクニカルマニュアル Rev.2.1

S1F77330 シリーズテクニカルマニュアル Rev.2.1 シリーズテクニカルマニュアル Rev.2.1 本資料のご使用につきましては 次の点にご留意願います 本資料の内容については 予告無く変更することがあります 1. 本資料の一部 または全部を弊社に無断で転載 または 複製など他の目的に使用することは堅くお断りいたします 2. 本資料に掲載される応用回路 プログラム 使用方法等はあくまでも参考情報であり これらに起因する第三者の知的財産権およびその他の権利侵害あるいは損害の発生に対し

More information

OPA134/2134/4134('98.03)

OPA134/2134/4134('98.03) OPA OPA OPA OPA OPA OPA OPA OPA OPA TM µ Ω ± ± ± ± + OPA OPA OPA Offset Trim Offset Trim Out A V+ Out A Out D In +In V+ Output In A +In A A B Out B In B In A +In A A D In D +In D V NC V +In B V+ V +In

More information

Stratix IIIデバイスの外部メモリ・インタフェース

Stratix IIIデバイスの外部メモリ・インタフェース 8. Stratix III SIII51008-1.1 Stratix III I/O R3 SRAM R2 SRAM R SRAM RII+ SRAM RII SRAM RLRAM II 400 MHz R Stratix III I/O On-Chip Termination OCT / HR 4 36 R ouble ata RateStratix III FPGA Stratix III

More information

MAX191 EV J

MAX191 EV J -0; Rev ; / µ µ PART TEMP. RANGE BOARD TYPE MAXEVSYS-DIP 0 C to +0 C Through-Hole MAXEVKIT-DIP 0 C to +0 C Through-Hole 0CMODULE-DIP 0 C to +0 C Through-Hole Evaluates: MAX Maxim Integrated Products Evaluates:

More information

ザイリンクス XAPP454 『Spartan-3 FPGA の DDR2 SDRAM メモリ インターフェイス』

ザイリンクス XAPP454 『Spartan-3 FPGA の DDR2 SDRAM メモリ インターフェイス』 : Spartan-3 FPGA XAPP454 (v1.1.1) 2007 6 11 Spartan-3 FPGA DD2 SDAM : Karthikeyan Palanisamy Spartan -3 DD2 SDAM Micron DD2 SDAM DD2 SDAM DD2 SDAM DD2 SDAM DD2 SDAM DD SDAM DD2 SDAM DD SDAM DD2 SDAM SSTL

More information

EVI-D100/D100P

EVI-D100/D100P A-AYS-100-11(1) EVI-D100/D100P 2001 Sony Corporation ... 3... 4... 5... 7... 18 D30/D31... 40... 46... 48... 49 2 3 VIDEO S S S VIDEO VISCA 1 VISCA IN VISCA OUT RS-232C EVI-D100/P VISCA IN AC DC IN 12V

More information

NL-22/NL-32取扱説明書_操作編

NL-22/NL-32取扱説明書_操作編 MIC / Preamp ATT NL-32 A C ATT AMP 1 AMP 2 AMP 3 FLAT FLAT CAL.SIG. OVER LOAD DET. AMP 4 AMP 5 A/D D/A CONV. AMP 6 AMP 7 A/D CONV. Vref. AMP 8 AMP 10 DC OUT AMP 9 FILTER OUT AC DC OUT AC OUT KEY SW Start

More information

ANJ_1092A

ANJ_1092A Application Note SBAA066 ± ± ± ± µ ± ± ± ± 24 Bits 20/24MSB 2 s f S 768 khz 25 MHz (1) V IH 2.0 5.0 V (1) V IL 0 0.8 V (2) V IH 3.0 0 V (2) V IL 5.0 4.2 V (1) I IH V IH = V DD ±10 µa (1) I IL V IL = 0V

More information

EQUIUM EQUIUM S5010 1

EQUIUM EQUIUM S5010 1 EQUIUM EQUIUM S5010 1 1 1 2 3 4 2 1 2 3 2 3 1 2 3 4 5 6 7 4 1 2 5 1 2 6 1 7 1 2 3 4 5 6 7 1 2 3 4 5 6 3 7 8 9 1 2 3 4 4 5 6 7 8 1 1 2 3 4 10 1 11 12 1 13 14 1 15 16 1 1 2 3 17 1 2 3 18 4 5 6 1 19 1 2 3

More information

R1EX24256BSAS0I/R1EX24256BTAS0I データシート

R1EX24256BSAS0I/R1EX24256BTAS0I データシート R1EX24256BSAS0I R1EX24256BTAS0I Two-wire serial interface 256k EEPROM (32-kword 8-bit) R10DS0003JJ0400 Rev.4.00 R1EX24xxx 2 EEPROM ROM MONOS CMOS 64 1.8V 5.5V 2 (I 2 C ) 400kHz 2.0μA (max) 1.0mA (max)

More information

Stratix IIデバイス・ハンドブック Volume 1

Stratix IIデバイス・ハンドブック Volume 1 3. & SII51003-4.0 IEEE Std. 1149.1 JTAG Stratix II IEEE Std. 1149.1 JTAG BST JTAG Stratix II Quartus II Jam.jam Jam Byte-Code.jbc JTAG Stratix II JTAG BST IOE I/O JTAG CONFIG_IO I/O Stratix II JTAG Stratix

More information

ADC082S021 2 Channel, 50 ksps to 200 ksps, 8-Bit A/D Converter (jp)

ADC082S021 2 Channel, 50 ksps to 200 ksps, 8-Bit A/D Converter (jp) 2 Channel, 50 ksps to 200 ksps, 8-Bit A/D Converter Literature Number: JAJSAA2 2 200KSPS 8 A/D 2 8 CMOS A/D 50kSPS 200kSPS / IN1 IN2 1 2 SPI QSPI MICROWIRE DSP 2.7V 5.25V 3V 1.6mW 5V 5.8mW 3V 0.12 W 5V

More information

NL-20取扱説明書_操作編

NL-20取扱説明書_操作編 MIC / Preamp A C AMP 1 AMP 2 AMP 3 FLAT FLAT CAL.SIG. OVER LOAD DET. AMP 4 AMP 5 A/D D/A CONV. V ref. AMP 8 AMP 10 DC OUT AC OUT AC DC OUT DATA BUS CPU ADDRESS BUS DSP Start Pause Stop Store Mode Cont

More information

TM-m30 詳細取扱説明書

TM-m30 詳細取扱説明書 M00094101 Rev. B Seiko Epson Corporation 2015-2016. All rights reserved. 2 3 4 5 6 7 8 Bluetooth 9 Bluetooth 10 1 11 Bluetooth 12 1 13 1 2 6 5 4 3 7 14 1 1 2 3 4 5 15 16 ONF 1 N O O N O N N N O F N N F

More information

DS

DS FUJITSU SEMICONDUCTOR DATA SHEET DS4 272 1 ASSP (AC / DC ) BIPOLAR, IC,, 2 ma, 5 V SOP 16 1 AC/DC Copyright 1986-211 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 211.5 (TOP VIEW) IN1 1 16 IN2 IN1

More information

HA1631S01/02/03/04シリーズ データシート

HA1631S01/02/03/04シリーズ データシート H1631S1/2/3/4 CMOS (/ ) R3DS85JJ5 Rev.5. 215.7.1 H1631S1/2/3/4 CMOS IC 1.8V H1631S1/2 H1631S3/4 CMPK-5 SOP-8 1/8 H1631S1/3 : I DDtyp = 5μ () H1631S2/4 : I DDtyp = 5μ () : V DD = 1.8 5.5V : V IOmax = 5mV

More information

LTC 単一5VAppleTalk トランシーバ

LTC 単一5VAppleTalk トランシーバ LTC µ µ µ µ TYPICAL APPLICATI O LTC 0.µF CHARGE PMP CPEN EN EN O O 0 DO 0 V µf 0.µF µf D D = Ω TO 0Ω Ω TO 0Ω 00pF LTC TA0 - LTC ABSOLTE AXI RATI GS Supply Voltage ( )... V Input Voltage Logic Inputs...

More information

RM-P1000 (B)

RM-P1000 (B) RM-P1000 (B) HDR /HDR LST0502-001B A AB AB AB AB A B AB A B AB 2 _ _ 3 A B 4 J I H G F E D C B A HDR K L M N O P Q / HDR b a R STU V W X Y Z A A B B A AB C AB A : A B A D A : E A B A B F E G A A 5 J I

More information

ADC78H90 8-Channel, 500 kSPS, 12-Bit A/D Converter (jp)

ADC78H90 8-Channel, 500 kSPS, 12-Bit A/D Converter (jp) 8-Channel, 500 ksps, 12-Bit A/D Converter Literature Number: JAJSA63 8 500kSPS 12 A/D 8 12 CMOS A/D 500kSPS / AIN1 AIN8 8 SPI QSPI MICROWIRE DSP (AV DD ) 2.7V 5.25V (DV DD ) 2.7V AV DD 3V 1.5mW 5V 8.3mW

More information

DS90LV047A

DS90LV047A 3V LVDS 4 CMOS 4 CMOS Low Voltage Differential Signaling (LVDS) 400Mbps (200MHz) TLL/CMOS 350mV TRI-STATE 13mW ( ) PCB ENABLE ENABLE* AND TRI- STATE 4 DS90LV04 A (DS90LV048A ) ECL 1 1 Dual-In-Line 3V LVDS

More information

AD725: 輝度トラップ・ポートを備えた低コスト RGB-NTSC / PAL エンコーダ

AD725: 輝度トラップ・ポートを備えた低コスト RGB-NTSC / PAL エンコーダ AD725 NTSC/PAL HSYNC VSYNC 4FSC CLOCK XNOR CSYNC 4FSC CSYNC BURST NTSC/PAL 4FSC FSC 90 C FSC 0 C CSYNC FSC 90 C/270 C CLOCK AT 8FSC RED DC CLAMP Y X2 GREEN BLUE DC CLAMP DC CLAMP U V NTSC/PAL X2 X2 STND

More information

untitled

untitled CMOS 376-851511 0277 (30) 1788 0277 (30)1707 e-mail: k_haruo@el.gunma-u.ac.jp AD AD AD [] AD AD AD [] ISSCC 2007 TSMC ISSCC2007 ISSCC2007 /DAC (regulation) (AGC) ADC/DAC AD AD AD [] AD CMOS SAR ADC Gr),,

More information

TM-T88VI 詳細取扱説明書

TM-T88VI 詳細取扱説明書 M00109801 Rev. B 2 3 4 5 6 7 8 9 10 Bluetooth 11 12 Bluetooth 13 14 1 15 16 Bluetooth Bluetooth 1 17 1 2 3 4 10 9 8 7 12 5 6 11 18 1 19 1 3 4 2 5 6 7 20 1 21 22 1 23 24 1 25 SimpleAP Start SSID : EPSON_Printer

More information

TM-m30 詳細取扱説明書

TM-m30 詳細取扱説明書 M00094100 Rev. A Seiko Epson Corporation 2015. All rights reserved. 2 3 4 5 6 Bluetooth 7 Bluetooth 8 1 9 Bluetooth 10 1 11 1 2 6 5 4 3 7 12 1 13 14 ONF 1 N O O N O N N N O F N N F N N N N N N F F O O

More information

DS04-21361-4

DS04-21361-4 Cypress () FUJITSU SEMICONDUCTOR DATA SHEET DS4 236 4 ASSPDTS Bi-CMOS PLL (. GHz PLL) MB5F7SL MB5F7SL,, MHz 2 PLL (Phase Locked Loop) LSI Bi CMOS, 5 ma (VCC 2.7 V), VCC 2.4 V,.5 ma, 6 ma 2, MB5F7SL,, MHz

More information

midicontrolsurfaces60_J.book

midicontrolsurfaces60_J.book Pro Tools Version 6.x for TDM or LE Systems on Windows or Macintosh 932911839-01 REV A MNL,MIDI CTRL SURF 6.1,JPN .............................. 1...........................................................

More information

AN5637

AN5637 IC SECAM IC SECAM IC 1 SECAM Unit : mm 19.2±0.3 16 9 1 8 (0.71) 0.5±0.1 Seating plane 2.54 1.22±0.25 DIP016-P-0300D 6.2±0.3 5.20±0.25 1.10±0.25 3.05±0.25 7.62±0.25 3 to 15 0.30 +0.10 ) (DIP016- P-0300M)

More information

c 2014 2 t WC 1 2: SRAM 1.2 DRAM DRAM DRAM DRAM 3 4M 1 DRAM 22 1 A0 A10 11 DRAM 22 DIN DOUT 1 DRAM

c 2014 2 t WC 1 2: SRAM 1.2 DRAM DRAM DRAM DRAM 3 4M 1 DRAM 22 1 A0 A10 11 DRAM 22 DIN DOUT 1 DRAM 2014/4/22 1 1.1 SRAM SRAM 1 128K 1M 128K 8 17 8 SRAM CS 1 OE 2 WE 3 CS OE WE V CC V SS 1: SRAM SRAM 2 2 (a) t ACC t RC 1 2 (b) t CSW CS 1 chip select 2 output enable 3 write enable 1 c 2014 2 t WC 1 2:

More information