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1 Data Sheet Rev pin DDR SDRAM Module SO-DIMM 1024MB DDR PC 2100 in COB Small Outline Dual-In-Line. DRAM DDR- SDRAM : MICRON MT 46V 64M8 T17B V DD 2,5V ±0.2V, V DD Q 2,5V ±0.2V CAS latency, (CBR) : 8K / 64ms 2.5V I/O ( SSTL_2 ) EEPROM Gold- DDR SO-DIMM JEDEC PC2700 JEDEC- MO 224. ( ) 31, , R2.0 Ø1,8 1,8 11,4 R0,5 3,5 4,2 TOP 0,6 67,6 63,6 47,4 Figure 1: (mm) 0,25max C C y 10% - 90% PSI ( ft.) -40 C - 70 C 5% - 95% 1682 PSI ( 5000 ft.) 50 C Industriestrasse 4-8 Fon: +41 (0) Page 1 1CH-9552 Bronschhofen, Switzerland Fax: +41 (0) sales@swissbit.com of 12

5V I/O ( SSTL_2 ) EEPROM Gold- DDR SO-DIMM JEDEC PC2700 JEDEC- MO 224. ( www.jedec.org ) 31,75 20.0 2,15 6.0 R2.

2 200 8 DRAM Dual-in-Line (SO-DIMM) 128M X 64 COB ( ) 1GB 1.25 EEPROM SPD( ), Two pin I2C 128byte 128byte DDR. Column ( mm ) 128M x 64 16x 64Mx8 13 BA0, BA1 11 8k x31.75x3.80 / Latency SDN12864P1B12MT MB 2.1 GB/s 7.5ns/266MT/s 2533 SDN12864P1B12MT MB 2.7 GB/s 6.0ns/333MT/s 2533 A0-9, A11 A12 A10/AP BA0, BA /RAS /CAS /WE 0 1 CK0 CK2 /CK0 /CK2 0-7 / ( ) Row Column / / Industriestrasse 4-8 Fon: +41 (0) Page 2 2CH-9552 Bronschhofen, Switzerland Fax: +41 (0) sales@swissbit.com of 12

5ns/266MT/s 2533 SDN12864P1B12MT-60 1024MB 2.7 GB/s 6.

3 /S0, /S1 V DD V DDQ V DDID V DDSPD V REF Vss SCL SDA NC Power (2.5V± 0.2V) Power (2.5V±0.2V VDD, VDDQ SPD / PIN # PIN # PIN # PIN # 1 VREF 2 VREF 101 A9 102 A8 3 VSS 4 VSS 103 VSS 104 VSS A7 106 A A5 108 A4 9 VDD 10 VDD 109 A3 110 A A1 112 A VDD 114 VDD 15 VSS 16 VSS 115 A10/AP 116 BA BA0 118 /RAS 19 DQ /WE 120 /CAS 21 VDD 22 VDD 121 /S0 122 /S1 23 DQ DU 124 DU VSS 126 VSS 27 VSS 28 VSS VDD 132 VDD 33 VDD 34 VDD CK0 36 VDD /CK0 38 VSS 137 VSS 138 VSS 39 VSS 40 VSS VDD 144 VDD 45 VDD 46 VDD VSS 150 VSS 51 VSS 52 VSS Industriestrasse 4-8 Fon: +41 (0) Page 3 3CH-9552 Bronschhofen, Switzerland Fax: +41 (0) sales@swissbit.com of 12

114 VDD 15 VSS 16 VSS 115 A10/AP 116 BA1 17 18 117 BA0 118 /RAS 19 DQ8 20 2 119 /WE 120 /CAS 21 VDD 22 VDD 121 /S0 122 /S1 23 DQ9 24 3 123 DU 124 DU 25 1 26 1 125 VSS 126 VSS 27 VSS 28 VSS 127 2 128

4 PIN # PIN # PIN # PIN # VDD 156 VDD 57 VDD 58 VDD 157 VDD 158 /CK VSS 160 CK VSS 162 VSS 63 VSS 64 VSS VDD 168 VDD 69 VDD 70 VDD CB0 72 CB CB1 74 CB5 173 VSS 174 VSS 75 VSS 76 VSS CB2 80 CB6 179 VDD 180 VDD 81 VDD 82 VDD CB3 84 CB DU 86 DU/(RESET) 185 VSS 186 VSS 87 VSS 88 VSS CK2 90 VSS /CK2 92 VDD 191 VDD 192 VDD 93 VDD 94 VDD 193 SDA 194 SA SCL 196 SA1 97 DU(A13) 98 DU(BA2) 197 VDDSPD 198 SA2 99 A A VDDID 200 DU Industriestrasse 4-8 Fon: +41 (0) Page 4 4CH-9552 Bronschhofen, Switzerland Fax: +41 (0) sales@swissbit.com of 12

82 VDD 181 7 182 1 83 CB3 84 CB7 183 7 184 7 85 DU 86 DU/(RESET) 185 VSS 186 VSS 87 VSS 88 VSS 187 8 188 2 89 CK2 90 VSS 189 9 190 3 91 /CK2 92 VDD 191 VDD 192 VDD 93 VDD 94 VDD 193 SDA 194 SA0 95 1

5 S1 S U1 U5 9 8 U2 U U3 U7 1 0 U4 U U9 U U10 U14 Clock Input CK0- /CKO CK1- /CK1 CK2- /CK2 Clock Wiring SDRAMS 8 SDRAMs 8 SDRAMs NC DQ9 5 DQ8 4 SCL SCL SDA WP A0 A1 A2 SDA SA0 SA1 SA U11 U U12 U16 U1/U5(U3/U7) R=120 Ohm +/- 5% U2/U6(U4/U8) CK0(1) /CK0(1) BA0-BA1 BA0-BA1:DDR SDRAM U1-U16 VDDSPD SPD DQ,, resistors: 22 Ohm U9/U13(U11/U15) A0-A13 A0-A13: DDR SDRAM U1-U16 VDD/VDDQ U1- U16 /RAS /RAS: DDR SDRAM U1-U16 VREF U1- U16 /CAS /CAS: DDR SDRAM U1-U16 VSS U1- U16 U10/U14(U12/U16) /WE /WE: DDR SDRAM U1-U16 VDDID Industriestrasse 4-8 Fon: +41 (0) Page 5 5CH-9552 Bronschhofen, Switzerland Fax: +41 (0) sales@swissbit.com of 12

BA0-BA1 BA0-BA1:DDR SDRAM U1-U16 VDDSPD SPD DQ,, resistors: 22 Ohm U9/U13(U11/U15) A0-A13 A0-A13: DDR SDRAM U1-U16 VDD/VDDQ U1- U16 /RAS /RAS: DDR SDRAM U1-U16 VREF U1- U16 /CAS /CAS: DDR SDRAM

6 (0 C T A + 70 C ; V DD = +2.5V ± 0.2V, V DD Q = +2.5V ± 0.2V) MIN MAX Supply Voltage V DD V I/O Supply Voltage V DD Q V I/O Reference Voltage V REF 0.49 x V DD Q 0.51x V DD Q V I/O Termination Voltage (system) V TT V REF 0.04 V REF V Input High (Logic 1) Voltage V IH (DC) V REF V DD V Input Low (Logic 0) Voltage V IL (DC) -0.3 V REF 0.15 V INPUT LEAKAGE CURRENT Any input 0V V IN V DD, V REF pin 0V V IN 1.35V I I µa (All other pins not under test = 0V) OUTPUT LEAKAGE CURRENT I OZ µa (DQ S are disabled; 0V V OUT V DD Q) OUTPUT LEVELS: High Current (V OUT = V DD Q-0.373V,minimum V REF, minimum V TT ) Low Current (V OUT =0.373V, maximum V REF, maximum V TT ) I OH I OL ma ma DC (0 C T A + 70 C ; V DD = +2.5V ± 0.2V, V DD Q = +2.5V ± 0.2V) PARAMETER/ CONDITION MIN MAX Input High (Logic 1) Voltage V IH (AC) V REF V Input Low (Logic 0) Voltage V IL (AC) - V REF V I/O Reference Voltage V REF(AC) 0.49 x V DD Q 0.51x V DD Q V PARAMETER MIN MAX Input/Output Capacitance: DQ, C pf Input Capacitance: Command and Address C pf Input Capacitance: /S 0,1 C pf Input Capacitance: CK, /CK C pf Input Capacitance: C pf Industriestrasse 4-8 Fon: +41 (0) Page 6 6CH-9552 Bronschhofen, Switzerland Fax: +41 (0) sales@swissbit.com of 12

15 V INPUT LEAKAGE CURRENT Any input 0V V IN V DD, V REF pin 0V V IN 1.

7 DC (0 C T A + 70 C ; V DD Q = +2.5V ± 0.2V, V DD = +2.5V ± 0.2V) Parameter max & Test Condition OPERATING CURRENT : One device I DDO TBD TBD ma bank; Active-Precharge; t RC = t RC (Min); t CK = t CK (Min); DQ, and inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles OPERATING CURRENT : I DD1 TBD TBD ma One device bank; Active-Read- Precharge; Burst = 2; t RC = t RC (Min); t CK = t CK (Min);I OUT = 0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN I DD2P TBD TBD ma STANDBY CURRENT: All device banks idle; Power-down mode; t CK = t CK (Min); = (LOW) IDLE STANDBY CURRENT: CS# = I DD2F TBD TBD ma HIGH; All device banks idle; t CK = t CK (Min); = HIGH; Address and other control inputs changing once per clock cycle. V IN = V REF for DQ,, and ACTIVE POWER-DOWN STANDBY I DD3P TBD TBD ma CURRENT: One device bank active; Power-down mode; t CK = t CK (Min); = LOW ACTIVE STANDBY CURRENT: CS# = I DD3N TBD TBD ma HIGH; = HIGH; One device bank; Active-Precharge; t RC = t RAS (Max); t CK = t CK (Min); DQ, and inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: I DD4R TBD TBD ma Burst = 2; Reads; Continous burst; One bank active; Address and control inputs changing once per clock cycle; t CK = t CK (Min); I OUT = 0mA Industriestrasse 4-8 Fon: +41 (0) Page 7 7CH-9552 Bronschhofen, Switzerland Fax: +41 (0) sales@swissbit.com of 12

and control inputs changing once every two clock cycles OPERATING CURRENT : I DD1 TBD TBD ma One device bank; Active-Read- Precharge; Burst = 2; t RC = t RC (Min); t CK = t CK (Min);I OUT = 0mA;

8 Parameter max & Test Condition OPERATING CURRENT: Burst = 2; I DD4W Writes; Continuous burst; One device TBD TBD ma bank active; Address and control inputs changing once per clock cycle; t CK = t CK (Min); DQ,, and inputs changing twice per clock cycle AUTO REFRESH t RC = t RC (Min) I DD5 TBD TBD ma CURRENT t RC = µs I DD6 TBD TBD ma SELF REFRESH CURRENT: I DD7 TBD TBD 0.2V ma OPERATING CURRENT: Four device I DD8 TBD TBD bank interleaving READs (BL =4) with ma auto precharge, t RC = t RC (Min); t CK = t CK (Min); Address and control inputs change only during Active READ, or WRITE commands Industriestrasse 4-8 Fon: +41 (0) Page 8 8CH-9552 Bronschhofen, Switzerland Fax: +41 (0) sales@swissbit.com of 12

= t CK (Min); DQ,, and inputs changing twice per clock cycle AUTO REFRESH t RC = t RC (Min) I DD5 TBD TBD ma CURRENT t RC = 7.8125µs I DD6 TBD TBD ma SELF REFRESH CURRENT: I DD7 TBD TBD 0.

9 DDR SDRAM COMPONENT AC (0 C T A + 70 C ; V DD Q = +2.5V ± 0.2V, V DD = +2.5V ± 0.2V) AC CHARACTERISTICS PARAMETER SYMBOL MIN MAX MIN MAX Unit Access window of DQ S CK/CK# t AC ns CK high-level width t CH t CK CK low-level width t CL t CK Clock cycle time CL = 2.5 t ck (2.5) ns CL = 2 t ck (2) ns DQ and input hold time t DH ns relative to DQ and input setup time t DS ns relative to DQ and input pulse width t DIPW ns ( for each input ) Access window of from t CK ns CK/CK# input high pulse width t H t CK input low pulse width t L t CK DQ skew, to last DQ t Q ns valid, per group, per access Write command to first t S t CK latching transition falling edge to CK risingsetup t DSS t CK time falling edge from CK risinghold t DSH t CK time Half clock period t HP t CH, t CH, ns Data-out high-impedance t HZ ns window from CK/CK# Data-out low-impedance window t LZ ns from CK/CK# Address and control input hold t IHF ns time ( fast slew rate ) Address and control input setup t ISF ns time ( fast slew rate ) Address and control input hold t IHS ns time ( slow slew rate ) Address and control input setup t ISS ns time ( slow slew rate ) LOAD MODE REGISTER t MRD ns command cycle time DQ- hold, to first DQ to t QH t HP - t QHS t HP - t QHS ns go non-valid, per access Data hold skew factor t QHS ns t CL t CL Industriestrasse 4-8 Fon: +41 (0) Page 9 9CH-9552 Bronschhofen, Switzerland Fax: +41 (0) sales@swissbit.com of 12

5 13 ns DQ and input hold time t DH 0.5 0.45 ns relative to DQ and input setup time t DS 0.5 0.45 ns relative to DQ and input pulse width t DIPW 1.75 1.

10 AC CHARACTERISTICS PARAMETER SYMBOL MIN MAX MIN MAX Unit ACTIVE to PRECHARGE t RAS , ,000 ns command ACTIVE to READ with Auto t RAP ns precharge command ACTIVE to ACTIVE/AUTO t RC ns REFRESH command period AUTO REFRESH command t RFC ns period ACTIVE to READ or WRITE t RCD ns delay PRECHARGE command period t RP ns read preamble t RPRE t CK read postamble t RPST t CK ACTIVE bank a to ACTIVE bank t RRD ns b command write preamble t WPRE t CK write preamble setup time t WPRES 0 0 ns write postamble t WPST t CK Write recovery time t WR ns Internal WRITE to READ t WTR 1 1 t CK command delay Data valid output window na t QH - t Q t QH - t Q ns REFRESH to REFRESH t REFC µs command interval Average periodic refresh interval t REFI µs Terminating voltage delay to V DD t VTD 0 0 ns Exit SELF REFRESH to non- t XSNR ns READ command Exit SELF REFRESH to READ command t XSRD t CK Industriestrasse 4-8 Fon: +41 (0) Page 10 10CH-9552 Bronschhofen, Switzerland Fax: +41 (0) sales@swissbit.com of 12

9 1.1 0.9 1.1 t CK read postamble t RPST 0.4 0.6 0.4 0.6 t CK ACTIVE bank a to ACTIVE bank t RRD 15 12 ns b command write preamble t WPRE 0.25 0.

11 BYTE DESCRIPTION NUMBER OF SPD BYTES USED BY Optosys Technologies 0x80 1 TOTAL NUMBER OF BYTES IN SPD DEVICE 0x08 2 FUNDAMENTAL MEMORY TYPE 0x07 3 NUMBER OF ROW ADDRESSES ON ASSEMBLY 0x0d 4 NUMBER OF COLUMN ADDRESSES ON ASSEMBLY 0x0b 5 NUMBER OF PHYSICAL BANKS ON DIMM 0x02 6 MODULE DATA WIDTH 0x40 7 MODULE DATA WIDTH (cotinued) 0x00 8 MODULE VOLTAGE INTERFACE LEVELS (V DD Q) 0x04 9 SDRAM CYCLE TIME, (t CK ) 0x75 0x60 (CAS LATENCY =2.5) 10 SDRAM ACCESS FROM CLOCK,(t AC ) 0x75 0x70 (CAS LATENCY =2.5) 11 MODULE CONFIGURATION TYPE 0x00 12 REFRESH RATE/ TYPE 0x82 13 SDRAM DEVICE WIDTH (PRIMARY SDRAM) 0x08 14 ERROR- CHECKING SDRAM DATA WIDTH 0x00 15 MINIMUM CLOCK DELAY, BACK- TO- BACK 0x01 RANDOM COLUMN ACCESS 16 BURST LENGTHS SUPPORTED 0x0e 17 NUMBER OF BANKS ON SDRAM DEVICE 0x04 18 CAS LATENCIES SUPPORTED 0x0c 19 CS LATENCY 0x01 20 WE LATENCY 0x02 21 SDRAM MODULE ATTRIBUTES 0x20 22 SDRAM DEVICE ATTRIBUTES: GENERAL 0xc0 23 SDRAM CYCLE TIME, (t CK )(CAS latency=2) 0xa0 0xa75 (CAS LATENCY=2) 24 SDRAM ACCESS FROM CK, (t AC )(CAS latency=2) 0x75 0x70 (CAS LATENCY=2) 25 SDRAM CYCLE TIME, (t CK ) 0x00 (CAS LATENCY=1.5) 26 SDRAM ACCESS FROM CK, (t AC ) 0x00 (CAS LATENCY=1.5) 27 MINIMUM ROW PRECHARGE TIME, (t RP ) 0x50 0x48 28 MINIMUM ROW ACTIVE TO ROW ACTIVE, (t RRD ) 0x3c 0x30 29 MINIMUM RAS# TO CAS# DELAY, (t RCD ) 0x50 0x48 30 MINIMUM RAS# PULSE WIDTH, (t RAS ) 0x2d 0x2a 31 MODULE BANK DENSITY 0x80 Industriestrasse 4-8 Fon: +41 (0) Page 11 11CH-9552 Bronschhofen, Switzerland Fax: +41 (0) sales@swissbit.com of 12

DD Q) 0x04 9 SDRAM CYCLE TIME, (t CK ) 0x75 0x60 (CAS LATENCY =2.5) 10 SDRAM ACCESS FROM CLOCK,(t AC ) 0x75 0x70 (CAS LATENCY =2.

12 BYTE DESCRIPTION ADDRESS AND COMMAND SETUP TIME, (t IS ) 0xa0 0xb80 33 ADDRESS AND COOMAND HOLD TIME, (t IH ) 0xa0 0xb80 34 DATA/DATA MASK INPUT SETUP TIME, (t DS ) 0x50 0x45 35 DATA/DATA MASK INPUT HOLD TIME, (t DH ) 0x50 0x RESERVED 0x00 0x00 41 MIN ACTIVE AUTO REFRESH TIME (t RC ) 0x46 0x3c 42 MINIMUM AUTO REFRESH TO ACTIVE/ 0x46 0x48 AUTO REFRESH COMMAND PERIOD, (t RFC) 43 SDRAM DEVICE MAX CYCLE TIME (t CKMAX ) 0x30 0x30 44 SDRAM DEVICE MAX -DQ SKEW TIME 0x3c 0x2d (t Q ) 45 SDRAM DEVICE MAX READ DATA HOLD SKEW 0xA0 0xA0 FACTOR (t QHS ) RESERVED 0x00 62 SPD REVISION 0x00 63 CHECKSUM FOR BYTES xce 0x79 0x63 64 MANUFACTURER`S JEDEC ID CODE 0x7f 65 MANUFACTURER`S JEDEC ID CODE 0x7f 66 MANUFACTURER`S JEDEC ID CODE 0x2f 67 MANUFACTURER`S JEDEC ID CODE 0xff MANUFACTURER`S JEDEC ID CODE 0xff (continued) 72 MANUFACTURING LOCATION 0x MODULE PART NUMBER (ASCII) 91 PCB IDENTIFICATION CODE 0x01 92 IDENTIFICATION CODE (continued) x 93 YEAR OF MANUFACTURE IN BCD x 94 WEEK OF MANUFACTURE IN BCD x MODULE SERIAL NUMBER x x x x MANUFACTURER-SPECIFIC DATA (RSVD) Industriestrasse 4-8 Fon: +41 (0) Page 12 12CH-9552 Bronschhofen, Switzerland Fax: +41 (0) sales@swissbit.com of 12

(t RFC) 43 SDRAM DEVICE MAX CYCLE TIME (t CKMAX ) 0x30 0x30 44 SDRAM DEVICE MAX -DQ SKEW TIME 0x3c 0x2d (t Q ) 45 SDRAM DEVICE MAX READ DATA HOLD SKEW 0xA0 0xA0 FACTOR (t QHS ) 46-61 RESERVED 0x00 62

N12866N2P-H.PDF

N12866N2P-H.PDF 16Mx64bits PC133 SDRAM SO DIMM Based on 16Mx16 SDRAM with LVTTL, 4 banks & 8K Refresh (16M x 16bit) /. / 1 A0 ~ A12 BA0, BA1 CK0, CK1 CKE0 /S0 /RAS /CAS /WE DQM0 ~ DQM7 DQ0 ~ DQ63 SA0~2 SDA SCL VCC 3.3