橡ﾊｰﾄﾞｳｴｱ仕様r01.PDF
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1 H3/7/4 H3/7/25
2
3 CPU HD647750F67(SH4)... 3 SDRAM TC59SM76AFTL-80 28MB... 3 FLASH ROM BM29LV800BA-90PFTN 2MB... 3 DPRAM IDT70V27L5 28KB... 3 FIFO IDT72V3690L LWORD FIFO Write FIFO Read... 5 DBGREG
4 SETTING REGISTER... 9 GLINK MON REGISTER... 0 GLINK CHK REGISTER... 0 GLINK SET REGISTER... TTC CNT REGISTER... 2 SLINK CNT REGISTER... 3 FIFO INPUT MASK REGISTER... 3 FIFO FULL REGISTER... 4 FIFO ALMOST FULL REGISTER... 4 FIFO EMPTY REGISTER... 5 FIFO FULL MASK REGISTER... 5 FIFO ALMOST FULL MASK REGISTER... 6 GLINK FIFO RESET REGISTER... 6 TTC FIFO RESET REGISTER... 7 OUT FIFO RESET REGISTER... 8 SH4 IRL from CSR REGISTER... 9 VME IREQ from SH4 REGISTER... 9 VME IREQVEC from SH4 REGISTER VME IREQ from CSR REGISTER VME IREQVEC from CSR REGISTER... 2
5 SH4 RESET REGISTER GLINK-Rx (SW7) GLINK-Rx (SW83) AMODE (SW) VADR (SW,2,4,5) SH4 (SW3) (SW6) (SW7,4,5) SYS_RESET TCCLK FG JP VME P VME P (CN) SH4_UART_CH0 (CN3)... 3
6 SH4_UART_CH (CN4)... 3 ALTERA_JTAG (CN6,7)... 3 SH4_JTAG (CN8)... 3 TTCrx(J,2) SLINK (CN5)... 33
7 ATLAS TGC ROD-0 ATLAS TGC ROD-0
8 2
9 CPU HD647750F67(SH4) BCR 0xFF x C BCR2 0xFF xff0c WCR 0xFF x WCR2 0xFF80000C 32 0x WCR3 0xFF x MCR 0xFF x580 60c PCR 0xFF x0000 RTCSR 0xFF8000C 6 0xa509 RTCNT 0xFF xa500 RTCOR 0xFF xa5b4 PFCR 0xFF Default SDMR2 0xFF x00 SDMR3 0xFF x00 SH4 SDRAM TC59SM76AFTL-80 28MB SDRAM CPU FLASH ROM BM29LV800BA-90PFTN 2MB A20A0 A22A2 2 0x AA 00AA 32 20x0000 0AA x A0 00A DPRAM IDT70V27L5 28KB FIFO IDT72V3690L LWORD 3
10 0 H H 00F FFFF H H 03FF FFFF H H 040 FFFF H H 07FF FFFF 2 H H 0BFF FFFF 3 H 0C H 0FFF FFFF 4 H H F 5 6 H H 0FF FFFF H H F H H FF FFFF H H 3FF FFFF H H 5FF FFFF H H 7FF FFFF H H 9FF FFFF H A H BFF FFFF FLASH-ROM (2MB) DPRAM (28KB) SDRAM (64MB) SDRAM (64MB) CSR(FPGA) DBGREG FIFO-n FIFO-TTCn FIFO-n FIFO-TTCn ReadoutFIFO FIFO-VME /6/32/ /6/32/ Write 32 Read Write 4
11 FIFO Write H GLINK-FIFO_0 H GLINK-FIFO_ H GLINK-FIFO_2 H GLINK-FIFO_3 H GLINK-FIFO_4 H 2A GLINK-FIFO_5 H 2C GLINK-FIFO_6 H 2E GLINK-FIFO_7 H GLINK-FIFO_8 H GLINK-FIFO_9 H GLINK-FIFO_0 H GLINK-FIFO_ H GLINK-FIFO_2 H 3A TTC-FIFO_0 H 3C TTC-FIFO_ H 3E FIFO SH4 GLINK-FIFO-n D<5..0>, D<3..6> FPGA GLINK-FIFO-n TTC-FIFO 5FIFO Read H GLINK-FIFO_0 H GLINK-FIFO_ H GLINK-FIFO_2 H GLINK-FIFO_3 H GLINK-FIFO_4 H 4A GLINK-FIFO_5 H 4C GLINK-FIFO_6 H 4E GLINK-FIFO_7 H GLINK-FIFO_8 H GLINK-FIFO_9 H GLINK-FIFO_0 H GLINK-FIFO_ H GLINK-FIFO_2 H 5A TTC-FIFO_0 H 5C TTC-FIFO_ H 5E
12 DBGREG 0x Bit R/W R R R R R R R R R R R R R R R R Bit FLA SH_B USY R/W R R R R R R R R R R R R R R R R Bit Reg 3 RSV 0 FLASH_BUSY 0 6
13 H H 0 007F H H 0 FFFF H 0000 H 7FFF H 8000 H FFFF CSR D32 ReadoutFIFO D32 FIFO-VME D32 D32BLT H H 2 FFFF DPRAM (28Kbyte) D32 7
14 R/W 0x00 SETTING R/W H CSR 0x04 GLINK_MON R H x08 GLINK_CHK RC H x0C GLINK_SET R/W H x0 TTC_CNT R/W H x4 SLINK_CNT R/W H x8 FIFO_INPUT_MASK R/W H xC Reserved 0x20 FIFO_FULL RC H INTR 0x24 FIFO_ALMOST_FULL RC H x28 FIFO_EMPTY R H x2C FIFO_FULL_MASK R/W H 000 FFFF 32 0x30 FIFO_ALMOST_FULL_MASK R/W H 000 FFFF 32 0x34 GLINK_FIFO_RESET R/W H x38 TTC_FIFO_RESET R/W H x3C OUT_FIFO_RESET R/W H x40 SH4_IRL from CSR R/W H F 32 0x44 VME_IREQ from SH4 R/W H x48 VME_IREQVEC R/W H from SH4 0x4C VME_IREQ from CSR R/W H x50 VME_IREQVEC R/W H from CSR 0x54 Reserved 0x5C 0x60 SH4_RESET R/W H x64 0x7C Reserved 8
15 SETTING REGISTER Bit R/W R R R R R R R R R R R R R R R R Bit ROD BZ FIFO OUT TEST FIFO SC LK GC LK R/W R R R R R R R R R R R R/W R/W R/W R/W R/W Bit Reg 35 RSV 4 RODBZ 3 FIFOOUT 2 TESTFIFO SCLK 0 GCLK 0 ROD_BUSY (FF/PAF) ROD_BUSY 0 RreadoutFIFO Slink RreadoutFIFO Vme 0 FIFO-n,FIFO-TTCn SH4 WriteDisable FIFO-n,FIFO-TTCn SH4 WriteEnable 0 Slink CLK TTCrx 40.08MHz /2 Slink CLK 40.08MHz /2 0 Glink CLK TTCrx 40.08MHz Glink CLK 40.08MHz 9
16 GLINK MON REGISTER 4 GLINK Bit RDY 2 RDY RDY 0 RDY 9 RDY 8 RDY 7 RDY 6 RDY 5 RDY 4 RDY 3 RDY 2 RDY RDY 0 R/W R R R R R R R R R R R R R R R R Bit GER 2 GER GER 0 GER 9 GER 8 GER 7 GER 6 GER 5 GER 4 GER 3 GER 2 GER GER 0 R/W R R R R R R R R R R R R R R R R Bit reg 35 RSV 286 RDY[2..0] 0 Glink not Ready Glink Ready 53 RSV 20 GER[2..0] 0 Glink DATA not ERROR Glink DATA ERROR GLINK CHK REGISTER 8 ENABLE ENABLE bit FDC E2 FDC E FDC E0 FDC E9 FDC E8 FDC E7 FDC E6 FDC E5 FDC E4 FDC E3 FDC E2 FDC E FDC E0 R/W R R R RC RC RC RC RC RC RC RC RC RC RC RC RC bit FGE R2 FGE R FGE R0 FGE R9 FGE R8 FGE R7 FGE R6 FGE R5 FGE R4 FGE R3 FGE R2 FGE R FGE R0 R/W R R R RC RC RC RC RC RC RC RC RC RC RC RC RC bit Reg 35 RSV 286 FDCE[2..0] 0 FIFO-read-data data/conrol word FIFO-read-data data/conrol word 53 RSV 20 FGER[2..0] 0 FIFO-read-data RxGERR FIFO-read-data RxGERR 0
![35 RSV 286 RDY[2..0] 0 Glink not Ready Glink Ready 53 RSV 20 GER[2.](/docs-images/47/20492435/images/page_16.jpg ".0] 0 Glink DATA not ERROR Glink DATA ERROR GLINK CHK REGISTER 8 ENABLE ENABLE bit 3 30 29 28 27 26 25 24 23 22 2 20 9 8 7 6 FDC E2 FDC E FDC E0 FDC E9 FDC E8 FDC E7 FDC E6 FDC E5 FDC E4 FDC E3 FDC")
17 GLINK SET REGISTER C bit R/W R R R R R R R R R R R R R R R R bit ESM PX ENB RX FLG ENB R/W R R R R R R R R R R R R R R R/W R/W bit Reg 32 RSV ESMPXENB 0 RXFLGENB 0 disable descramble (Glink enable descramble (Glink 0 Flg bit is not used as a user bit (Glink Flg bit is used as a user bit (Glink
18 TTC CNT REGISTER 0 bit R/W R R R R R R R R R R R R R R R R bit SDA I SDA O SCL I SCL O TTCR ST TTCR DY R/W R R R R R R R R R R/W R R/W R R R/W R Bit Reg 38 RSV 7 SDAI 0 TTCrx-I2C 6 SDAO 0 TTCrx-I2C 5 SCLI 0 TTCrx-I2C 4 SCLO 0 TTCrx-I2C 32 RSV TTCRST 0 reset TTCrx(reset_b) none 0 TTCRDY 0 TTCrx not ready TTCrx ready 2
19 SLINK CNT REGISTER 4 Bit R/W R R R R R R R R R R R R R R R R Bit LRL3 LRL2 LRL LRL0 LDO WN# UCN TL# UTE ST# URE SET# R/W R R R R R R R R R R R R R R/W R/W R/W bit reg 38 RSV 74 LRL[3..0] 3 LDOWN# 2 UCNTL# UTEST# 0 URESET# 0 LINK RETURN KINE DATA 0 SLINK IS NOT OPERATIONAL OPERATIONAL 0 TRANSMIT CONTROL WORD TRANSMIT DATA WORD 0 SET THE SLINK TO THE TEST MODE SET THE SLINK TO NORMAL MODE 0 SLINK SET NONE FIFO INPUT MASK REGISTER 8 Bit R/W R R R R R R R R R R R R R R R R Bit FIM_ T FIM_ T0 FIM_ 2 FIM_ FIM_ 0 FIM_ 9 FIM_ 8 FIM_ 7 FIM_ 6 FIM_ 5 FIM_ 4 FIM_ 3 FIM_ 2 FIM_ FIM_ 0 R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W bit reg 35 RSV 40 FIM_T[..0] 0 FIFO Write Enable FIM[2..0] FIFO Input Mask(Write Disable) 3
![.0] 3 LDOWN# 2 UCNTL# UTEST# 0 URESET# 0 LINK RETURN KINE DATA 0 SLINK IS NOT OPERATIONAL OPERATIONAL 0 TRANSMIT CONTROL WORD TRANSMIT DATA WORD 0 SET THE SLINK TO THE TEST MODE SET THE SLINK TO](/docs-images/47/20492435/images/page_19.jpg "NORMAL MODE 0 SLINK SET NONE FIFO INPUT MASK REGISTER 8 Bit 3 30 29 28 27 26 25 24 23 22 2 20 9 8 7 6 R/W R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 5 4 3 2 0 9 8 7 6 5 4 3 2")
20 FIFO FULL REGISTER 20 ENABLE ENABLE Bit FF_ VF R/W R R R R R R R R R R R R R R R Bit FF_ FF_ FF_ FF2 FF FF0 FF9 FF8 FF7 FF6 FF5 FF4 FF3 FF2 FF FF0 ROF T T0 R/W RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC bit Reg 37 RSV 60 FF_VF FF_ROF FF_T[..0] FF[2..0] 0 not Full FIFO-Full FIFO ALMOST FULL REGISTER 24 ENABLE ENABLE Bit AF_ VF R/W R R R R R R R R R R R R R R R RC Bit AF_ AF_ AF_ AF2 AF AF0 AF9 AF8 AF7 AF6 AF5 AF4 AF3 AF2 AF AF0 ROF T T0 R/W RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC bit Reg 37 RSV 60 AF_VF AF_ROF AF_T[..0] AF[2..0] 0 not Almost-Full FIFO Almost-Full 4
![.0] 0 not Full FIFO-Full FIFO ALMOST FULL REGISTER 24 ENABLE ENABLE Bit 3 30 29 28 27 26 25 24 23 22 2 20 9 8 7 6 AF_ VF R/W R R R R R R R R R R R R R R R RC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 5 4 3](/docs-images/47/20492435/images/page_20.jpg "2 0 9 8 7 6 5 4 3 2 0 AF_ AF_ AF_ AF2 AF AF0 AF9 AF8 AF7 AF6 AF5 AF4 AF3 AF2 AF AF0 ROF T T0 R/W RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC RC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit Reg 37 RSV 60")
21 FIFO EMPTY REGISTER 28 FIFO VME FIFO EMPTY FIFO Bit R/W R R R R R R R R R R R R R R R R EF_ VF Bit EF_ EF_ EF_ EF2 EF EF0 EF9 EF8 EF7 EF6 EF5 EF4 EF3 EF2 EF EF0 ROF T T0 R/W R R R R R R R R R R R R R R R R Bit reg 37 RSV 60 EF_VF EF_ROF EF_T[..0] EF[2..0] 0 not Empty FIFO Empty FIFO FULL MASK REGISTER 2C Bit MFF_ VF R/W R R R R R R R R R R R R R R R R/W Bit MFF_ ROF MFF_ T MFF_ T0 MFF 2 MFF MFF 0 MFF 9 MFF 8 MFF 7 MFF 6 MFF 5 MFF 4 MFF 3 MFF 2 MFF MFF 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit reg 37 RSV 60 MFF_VF MFF_ROF MFF_T[..0] MFF[2..0] 0 FIFO-Full Enable FIFO-Full Disable 5
22 FIFO ALMOST FULL MASK REGISTER 30 Bit MAF _ VF R/W R R R R R R R R R R R R R R R R/W Bit MAF _ROF MAF _T MAF _T0 MAF 2 MAF MAF 0 MAF 9 MAF 8 MAF 7 MAF 6 MAF 5 MAF 4 MAF 3 MAF 2 MAF MAF 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit reg 37 RSV 60 MAF_VF MAF_ROF MAF_T[..0] MAF[2..0] GLINK FIFO RESET REGISTER 34 0 FIFO Almost-Full Enable FIFO Almost-Full Disable FIFO Bit R/W R R R R R R R R R R R R R R R R/W Bit G_FS EL G_FS EL0 G_ LD G_ FRST R/W R R R R R R R R R R R R R/W R/W R/W R/W Bit Reg 34 RSV 32 G_FSEL[..0] 0 MRST Offset pin G_LD 0 G_FRST 0 MRST Offset pinmrst Offset Enable MRST Offset pinmrst Offset Disable 0 FIFO reset none 6
23 TTC FIFO RESET REGISTER 38 FIFO Bit R/W R R R R R R R R R R R R R R R R/W Bit T_FS EL T_FS EL0 T_ LD T_ FRST R/W R R R R R R R R R R R R R/W R/W R/W R/W Bit Reg 34 RSV 32 T_LD T_FSEL[..0] 0 T_FRST 0 MRST Offset pin 0 MRST Offset pinmrst Offset Enable MRST Offset pinmrst Offset Disable 0 FIFO reset None 7
24 OUT FIFO RESET REGISTER 3C FIFO Bit R/W R R R R R R R R R R R R R R R R/W Bit RV_F SEL RV_F SEL0 RV_ LD RV_ FRST R/W R R R R R R R R R R R R R/W R/W R/W R/W Bit Reg 34 RSV 32 T_LD T_FSEL[..0] 0 T_FRST 0 MRST Offset pin 0 MRST Offset pinmrst Offset Enable MRST Offset pinmrst Offset Disable 0 FIFO reset none LD,FSEL[..0]offset-value LD FSEL FSEL0 offset-value H L L 023 L H L 5 L L H 255 L L L 27 L H H 63 H H L 3 H L H 5 H H H 7 8
25 SH4 IRL from CSR REGISTER 40 FIFO_FULLALMOST_FULL SH4 FIFO_FULL,ALMOST_FULL H F Bit R/W R R R R R R R R R R R R R R R R/W Bit IRL3 IRL2 IRL IRL0 R/W R R R R R R R R R R R R R/W R/W R/W R/W Bit Reg 34 RSV 30 IRL[3..0] 0 SH4 VME IREQ from SH4 REGISTER 44 SH4 VME Bit R/W R R R R R R R R R R R R R R R R/W Bit SI SI SI REQ2 REQ REQ0 R/W R R R R R R R R R R R R R R/W R/W R/W Bit Reg 33 RSV 20 SIREQ[2..0] 0 SH4 VME (7) 9
26 VME IREQVEC from SH4 REGISTER 48 SH4 VME IREQ VECTOR Bit C3 C30 C29 C28 C27 C26 C25 C24 C23 C22 C2 C20 C9 C8 C7 C6 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit C5 C4 C3 C2 C C0 C9 C8 C7 C6 C5 C4 C3 C2 C C0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Reg 30 C[3..0] 0 SH4 VME VME IREQ from CSR REGISTER 4C FIFO_FULLALMOST_FULL VME Bit R/W R R R R R R R R R R R R R R R R Bit CI REQ2 CI REQ CI REQ0 R/W R R R R R R R R R R R R R R/W R/W R/W Bit Reg 33 RSV 20 CIREQ[2..0] 0 CSR VME (7) 20
27 VME IREQVEC from CSR REGISTER 50 CSR VME IREQ VECTOR Bit C3 C30 C29 C28 C27 C26 C25 C24 C23 C22 C2 C20 C9 C8 C7 C6 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit C5 C4 C3 C2 C C0 C9 C8 C7 C6 C5 C4 C3 C2 C C0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Reg 30 C[3..0] 0 CSR VME SIREQ[2..0],CIREQ[2..0]VME IREQ[7..] SIREQ[2..0]/CIREQ[2..0] VME 0 IREQ 0 IREQ2 00 IREQ3 0 IREQ4 00 IREQ5 00 IREQ6 000 IREQ7 SH4,CSR VECTOR IREQ VME IREQ 2
28 SH4 RESET REGISTER 60 SH4 Bit R/W R R R R R R R R R R R R R R R R Bit SH4_ RST R/W R R R R R R R R R R R R R R R R/W Bit Reg 3 RSV 0 SH4_RST 0 SH4 RESET None 22
29 GLINK-Rx (SW7) SW7 CH RXPASSENB Disable Enable GLINK-2 ON 2 RXDIV0 0 GLINK-2 OFF 3 RXDIV 0 GLINK-2 ON DSW GLINK HIGH HIGH,LOW GLINK-Rx (SW83) SWx CH RXPASSENB Disable Enable GLINK-n ON 2 RXDIV0 0 GLINK-n OFF 3 RXDIV 0 GLINK-n ON 4 RXPASSENB Disable Enable GLINK-n+ ON 5 RXDIV0 0 GLINK-n+ OFF 6 RXDIV 0 GLINK-n+ ON (n=0,2,4,6,8,0) DSW GLINK HIGH HIGH,LOW AMODE (SW) PATERN PATERN2 PATERN3 PATERN4 8 AMODE[0] AMODE[] 0 0 A32 A24 A6 NOT USED 23
30 VADR (SW,2,4,5) VME SW ON OFF 3 VADR[5] 0 2 VADR[6] 0 VADR[7] 0 SW2 ON OFF 8 VADR[8] 0 7 VADR[9] 0 6 VADR[0] 0 5 VADR[] 0 4 VADR[2] 0 3 VADR[3] 0 2 VADR[4] 0 VADR[5] 0 SW4 ON OFF 8 VADR[6] 0 7 VADR[7] 0 6 VADR[8] 0 5 VADR[9] 0 4 VADR[20] 0 3 VADR[2] 0 2 VADR[22] 0 VADR[23] 0 SW5 ON OFF 8 VADR[24] 0 7 VADR[25] 0 6 VADR[26] 0 5 VADR[27] 0 4 VADR[28] 0 3 VADR[29] 0 2 VADR[30] 0 VADR[3] 0 24
31 SH4 (SW3) 3 ON OFF 8 OFF 7 0 OFF 6 ON 5 0 OFF OFF 3 ON CPU 2 OFF OFF SH (SW6) ROD SH4 (SW7,4,5) 25
32 SYS_RESET JP JP SYS_RESET TCCLK JP JP-7,8 TTCrx FIFO TTXrx FG JP JP23 GND JP 26
33 LED LED LED5 LED LED9 LED0 LED LED2 LED3 LED4 LED23 LED9 LED23 LED24 LED75 LED76 LED79 LED80 LED92 LED VME CLK LED2 VME LED3 BERR LED4 LED5 FF,PAF FIFO EF FIFO PAF FIFO FF SLINK LED9 LED20 LED2 LED22 LED23 GNIK LED(24+4n) LED(25+4n) LED(26+4n) LED(27+4n) TTCrx LED76 LED77 LED78 LED79 SLINKCLK FIFODATA SLINK FIFODATA VME LFF GLINK_FIFO CLK TESTFIFO RXERROR RXREADY TESTMD ON TTC_FIFO_0 TTC_FIFO_ TTC_FIFO CLK CN P VME P P2 VME P2 CN CN2 ROD_BUSY CN3 SH4-UART_CH0 CN4 SH4-UART_CH DBG CN5 SLINK CN6 ALTERA-JTAG ROM 27
34 CN7 ALTERA-JTAG SRAM CN8 SH4-JTAG J TTCrx J2 TTCrx 28
35 VME P A VD0 B C VD8 D Z A2 VD B2 C2 VD9 D2 GND Z2 GND A3 VD2 B3 C3 VD0 D3 Z3 A4 VD3 B4 C4 VD D4 Z4 GND A5 VD4 B5 C5 VD2 D5 Z5 A6 VD5 B6 C6 VD3 D6 Z6 GND A7 VD6 B7 C7 VD4 D7 Z7 A8 VD7 B8 C8 VD5 D8 Z8 GND A9 GND B9 C9 GND D9 Z9 A0 SYSCLK B0 C0 D0 Z0 GND A GND B C BERRIN# D Z A2 DS# B2 C2 SYSRST# D2 +3.3V Z2 GND A3 DS0# B3 C3 LWORD# D3 Z3 A4 WRITE# B4 C4 AM5 D4 +3.3V Z4 GND A5 GND B5 C5 VA23 D5 Z5 A6 DTACK# B6 AM0 C6 VA22 D6 +3.3V Z6 GND A7 GND B7 AM C7 VA2 D7 Z7 A8 AS# B8 AM2 C8 VA20 D8 +3.3V Z8 GND A9 GND B9 AM3 C9 VA9 D9 Z9 A20 IACK# B20 GND C20 VA8 D V Z20 GND A2 IACKIN# B2 C2 VA7 D2 Z2 A22 IACKOUT# B22 C22 VA6 D V Z22 GND A23 AM4 B23 C23 VA5 D23 Z23 A24 VA7 B24 IREQ7# C24 VA4 D V Z24 GND A25 VA6 B25 IREQ6# C25 VA3 D25 Z25 A26 VA5 B26 IREQ5# C26 VA2 D V Z26 GND A27 VA4 B27 IREQ4# C27 VA D27 Z27 A28 VA3 B28 IREQ3# C28 VA0 D V Z28 GND A29 VA2 B29 IREQ2# C29 VA9 D29 Z29 A30 VA B30 IERQ# C30 VA8 D V Z30 GND A3 B3 C3 D3 GND Z3 A32 +5V B32 +5V C32 +5V D32 Z32 GND 29
36 VME P2 A B +5V C D Z A2 B2 GND C2 D2 Z2 GND A3 B3 RETRY# C3 D3 Z3 A4 B4 VA54 C4 D4 Z4 GND A5 B5 VA25 C5 D5 Z5 A6 B6 VA26 C6 D6 Z6 GND A7 B7 VA27 C7 D7 Z7 A8 B8 VA28 C8 D8 Z8 GND A9 B9 VA29 C9 D9 Z9 A0 B0 VA30 C0 D0 Z0 GND A B VA3 C D Z A2 B2 GND C2 D2 Z2 GND A3 B3 +5V C3 D3 Z3 A4 B4 VD6 C4 D4 Z4 GND A5 B5 VD7 C5 D5 Z5 A6 B6 VD8 C6 D6 Z6 GND A7 B7 VD9 C7 D7 Z7 A8 B8 VD20 C8 D8 Z8 GND A9 B9 VD2 C9 D9 Z9 A20 B20 VD22 C20 D20 Z20 GND A2 B2 VD23 C2 D2 Z2 A22 B22 GND C22 D22 Z22 GND A23 B23 VD24 C23 D23 Z23 A24 B24 VD25 C24 D24 Z24 GND A25 B25 VD26 C25 D25 Z25 A26 B26 VD27 C26 D26 Z26 GND A27 B27 VD28 C27 D27 Z27 A28 B28 VD29 C28 D28 Z28 GND A29 B29 VD30 C29 D29 Z29 A30 B30 VD3 C30 D30 Z30 GND A3 B3 GND C3 D3 GND Z3 A32 B32 +5V C32 D32 Z32 GND (CN) +3.3V V V V 5 +5V 6 GND 7 GND 8 GND 9 GND 0 GND 30
37 SH4_UART_CH0 (CN3) TX0 2 RX0 3 GND SH4_UART_CH (CN4) TX 2 RX 3 GND ALTERA_JTAG (CN6,7) TCKI 2 GND 3 TDO V 5 TMS TDI 0 GND SH4_JTAG (CN8) TCK 2 GND 3 TRST# 4 GND 5 SHTDO 6 GND 7 ASEBRK# 8 9 TMS 0 GND TDI 2 GND 3 RST# 4 GND 3
38 TTCrx(J,2) (J) (J2) 2 TTCCLKdes EVCNTLSTR 8 8 EVCNTHSTR GND SUBADR0 BCNT0 2 SUBADR 2 BCNT 3 SUBADR2 3 BCNT2 4 SUBADR3 4 BCNT3 5 SUBADR4 5 BCNT4 6 SUBADR5 6 BCNT5 7 SUBADR6 7 BCNT6 8 SUBADR7 8 BCNT7 9 TTC_DQ0 9 BCNT8 20 TTC_DQ 20 BCNT9 2 TTC_DQ2 2 BCNT0 22 TTC_DQ3 22 BCNT 23 Doutstr GND TTC_DOUT TTC_DOUT TTC_DOUT2 27 SDA 28 TTC_DOUT TTC_DOUT4 29 BCNTSTR 30 TTC_DOUT TTC_DOUT6 3 GND 32 TTC_DOUT7 32 GND 33 RESET_B 33 GND 34 READY 34 GND 35 GND 35 +5V 36 GND 36 +5V 37 GND 37 +5V 38 GND 38 +5V 39 GND GND 40 SCL 4 GND 4 GND 42 GND 42 GND 43 GND V 44 GND V 45 GND V 46 GND V 47 GND 47 GND 48 GND 48 GND 49 GND 49 GND 50 GND 50 GND 32
39 SLINK (CN5) LRL3 33 SLD23 2 LRL2 34 SLD V 35 SLD2 4 LRL 36 GND V 37 SLD20 6 LRL0 38 SLD9 7 LDOWN# V 8 GND 40 SLD8 9 GND 4 SLD7 0 LFF# 42 SLD6 UCLK 43 SLD5 2 GND 44 GND 3 GND 45 SLD4 4 UWEN# 46 SLD3 5 URESET# 47 GND 6 GND 48 SLD2 7 GND 49 SLD 8 UTEST# 50 SLD0 9 UCNTRL# 5 SLD9 20 GND V 2 SLD3 53 SLD V 54 SLD7 23 GND 55 GND 24 SLD30 56 SLD6 25 SLD29 57 SLD5 26 SLD28 58 SLD4 27 SLD27 59 SLD3 28 GND 60 GND 29 SLD26 6 SLD2 30 SLD25 62 SLD 3 GND V 32 SLD24 64 SLD0 33
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( ) () ( ) 1 1 TX19A31_AG3 TX19A/H1 CPUTMP19A31CYFG AG3 AG3 2 2 3 TX19A31_AG3 CPU 32 RISC TMP19A31CYFG (U1) 80MHz ROM 32Mbit ROM 1 ROM (U8) 16Mbit Flash ROM 1 (U9) RAM 4Mbit SRAM 1 (U10) I/F RS232C 1chSIO
oaks32r_m32102
OAKS32R-M32102S6FP 2 OAKS32R OAKS32R-M32102S6FP M32102S6FP... 4... 5... 6... 7 4.1. CPU...7 4.2. Flash ROM SDRAM....8 4.3. LANC....8 4.4. RS232C....9 4.5. CPU....9 4.6.....9 4.7....10 4.8. SDI....10...
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