AK8854VQ_MS0973-J-03
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- ふさこ まきい
- 6 years ago
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1 AK8854VQ Multi-Format Digital Video Decoder AK8854VQ NTSC, PAL, SECAM S (Y/C) 525i / 625i RGB RGB (CSYNC) H/VSYNC Green (Sync on Green) ITU-R BT.601 Y, Cb, Cr ITU-R BT C 85 C 10mm 64pinLQFP NTSC-J,M, NTSC-4.43 / PAL-B,D,G,H,I,N, Nc, M, PAL-60, SECAM S (Y/C) 525i / 625i (YPbPr) 525i / 625i RGB : 10ch 10-bit ADC 2ch PLL ( PLL PLL) PGA ( -6dB +6dB) Auto Gain Control (AGC) Auto Color Control (ACC) (Contrast, Satulation, Brightness, Hue, Sharpness) 2 YC PAL ITU-R BT.601 (4:2:2_8bit) ITU-R BT.656(4:2:2_8bit _EAV/SAV ) ( ) VBID(CGMS-A) (CRCC ) ( ) WSS ( ) Macrovision (Macrovision Certification) I2C V V 40 C 85 C 64 LQFP (Notice) This device is protected by U.S. patent number 6,600,873 and other intellectual property rights. MS0973-J /05
2 [ ] TEST0 TEST1 XTI XTO CLKMD VSYNC H_CSYNC SELA SDA SCL PDN RSTN OE TEST LOGIC Clock Module Timing Controller Digital PLL Microprocessor Interface AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 MUX CLAMP CLAMP CLAMP AAF AAF AAF MUX VREF PGA1 PGA2 10-bit ADC 10-bit ADC Decimation Filter Sync Separation RGB / YUV Convert Luminance Process VBI Decoding V Process U Process Output Buffer HD VD_F DVALID_F NSIG DTCLK DATA[7:0] ATIO VRP VCOM VRN IREF AVDD AVSS DVDD DVSS PVDD1 PVDD2 MS0973-J /05
3 [ ] TEST0 TEST1 XTI XTO CLKMD VSYNC H_CSYNC SELA SDA SCL PDN RSTN OE TEST LOGIC Clock Module Timing Controller Digital PLL Microprocessor Interface YC Separation Y Sync Separation Luminance Process HD VD_F AIN MUX CLAMP AAF PGA1 10-bit ADC Decimation Filter C Chrominance Process V U V Process U Process VBI Decoding Output Buffer DVALID_F NSIG DTCLK VREF DATA[7:0] ATIO VRP VCOM VRN IREF AVDD AVSS DVDD DVSS PVDD1 PVDD2 MS0973-J /05
4 [S(Y/C) ] TEST0 TEST1 XTI XTO CLKMD VSYNC H_CSYNC SELA SDA SCL PDN RSTN OE TEST LOGIC Clock Module Timing Controller Digital PLL Microprocessor Interface AIN Y CLAMP AAF PGA1 10-bit ADC Y Sync Separation Luminance Process HD VD_F AIN MUX C CLAMP AAF PGA2 10-bit ADC Decimation Filter C Chrominance Process U V VBI Decoding V Process U Process Output Buffer DVALID_F NSIG DTCLK VREF DATA[7:0] ATIO VRP VCOM VRN IREF AVDD AVSS DVDD DVSS PVDD1 PVDD2 MS0973-J /05
5 [ ] TEST0 TEST1 XTI XTO CLKMD VSYNC H_CSYNC SELA SDA SCL PDN RSTN OE TEST LOGIC Clock Module Timing Controller Digital PLL Microprocessor Interface AIN Y CLAMP AAF PGA1 10-bit ADC Y Sync Separation Y Luminance Process HD VD_F AIN AIN MUX Pr Pb CLAMP CLAMP AAF AAF MUX PGA2 10-bit ADC Decimation Filter V U V U V Process U Process VBI Decoding Output Buffer DVALID_F NSIG DTCLK VREF DATA[7:0] ATIO VRP VCOM VRN IREF AVDD AVSS DVDD DVSS PVDD1 PVDD2 MS0973-J /05
6 [ RGB ] TEST0 TEST1 XTI XTO CLKMD VSYNC H_CSYNC SELA SDA SCL PDN RSTN OE TEST LOGIC Clock Module Timing Controller Digital PLL Microprocessor Interface AIN G CLAMP AAF PGA1 10-bit ADC Sync Separation G Y Luminance Process HD VD_F AIN AIN R B MUX CLAMP CLAMP AAF AAF MUX VREF PGA2 10-bit ADC Decimation Filter R B RGB / YUV Convert V U VBI Decoding V Process U Process Output Buffer DVALID_F NSIG DTCLK DATA[7:0] ATIO VRP VCOM VRN IREF AVDD AVSS DVDD DVSS PVDD1 PVDD2 MS0973-J /05
7 2. 64pins LQFP DVDD DVSS NSIG SDA PVDD2 SCL SELA OE RSTN PDN DVDD XTO DVSS CLKMD XTI AVSS AVDD IREF AVSS ATIO AVSS AIN1 AVDD AIN2 VCOM AIN3 VRN AIN4 VRP AIN5 AVDD AIN TEST0 TEST1 DVSS DTCLK PVDD1 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DVSS PVDD1 DATA6 DATA7 HD VD_F DVALID_F DVSS DVDD VSYNC H_CSYNC PVDD1 AVSS AIN10 AVSS AIN9 AVSS AIN8 AVSS AIN7 AVSS MS0973-J /05
8 3. I/O No. 1 AVSS A G Page.100 [ ] 39%(-8.19dB) 0.033uF 2 AIN7 A I NC 3 AVSS A G Page. 100 [ ] 39%(-8.19dB) 0.033uF 4 AIN8 A I NC 5 AVSS A G Page. 100 [ ] 39%(-8.19dB) 0.033uF 6 AIN9 A I NC 7 AVSS A G Page. 100 [ ] 39%(-8.19dB) 0.033uF 8 AIN10 A I NC 9 AVSS A G 10 PVDD1 P1 P I/O RGB 11 H_CSYNC P1 I DVSS RGB 12 VSYNC P1 I DVSS 13 DVDD D P 14 DVSS D G DVALID / FIELD O DVALID / FIELD 15 DVALID_F P1 (I/O) ( I/O ) OE / PDN / RSTN (*1) VD(Vertical Data) / FIELD 16 VD_F P1 O VD / FIELD OE / PDN / RSTN (*1) 17 HD P1 18 DATA7 P1 19 DATA6 P1 O (I/O) O (I/O) O (I/O) 20 PVDD1 P1 P I/O 21 DVSS D G 22 DATA5 P1 O (I/O) HD(Horizontal Data) ( I/O ) OE / PDN / RSTN (*1) (MSB) ( I/O ) OE / PDN / RSTN (*1) ( I/O ) OE / PDN / RSTN (*1) ( I/O ) OE / PDN / RSTN (*1) MS0973-J /05
9 No. I/O 23 DATA4 P1 24 DATA3 P1 25 DATA2 P1 26 DATA1 P1 27 DATA0 P1 O (I/O) O (I/O) O (I/O) O (I/O) O (I/O) ( I/O ) OE / PDN / RSTN (*1) ( I/O ) OE / PDN / RSTN (*1) ( I/O ) OE / PDN / RSTN (*1) ( I/O ) OE / PDN / RSTN (*1) (LSB) ( I/O ) OE / PDN / RSTN (*1) 28 PVDD1 P1 P I/O 29 DTCLK P1 O I/F 27MHz OE / PDN / RSTN (*1) 30 DVSS D G 31 TEST1 D I DVSS 32 TEST0 D I DVSS 33 DVDD D P 34 DVSS D G 35 NSIG P2 O Low : ( ) High : OE / PDN / RSTN (*1) 36 SDA P2 I/O I2C PVDD2 PDN=L Hi-z SDA 37 PVDD2 P2 P I/F 38 SCL P2 I I2C PVDD2 PDN=L Hi-z SCL 39 SELA P2 I I2C PVDD2 : [0x8A] DVSS : [0x88] 40 OE P2 I Output Enable L : Hi-z H : OE Hi-z 41 RSTN P2 I Hi-z L : H : 42 PDN P2 I Hi-z L : H : MS0973-J /05
10 No. I/O 43 DVDD D P 44 XTO D O ( 22pF ) MHz PDN=L DVSS NC DVSS 45 DVSS D G 46 XTI D I ( 22pF ) MHz MHz 47 CLKMD D I DVDD DVSS DVSS : DVDD : ( ) 48 AVSS A G 49 AVDD A P 50 IREF A O 6.8k ( 1% ) 51 AVSS A G 52 ATIO A I/O AVSS 53 AVSS A G 54 AIN1 A I Page. 100 [ ] 39%(-8.19dB) 0.033uF NC 55 AVDD A P 56 AIN2 A I Page. 100 [ ] 39%(-8.19dB) 0.033uF NC 57 VCOM A O AD 0.1uF AVSS 58 AIN3 A I Page. 100 [ ] 39%(-8.19dB) 0.033uF NC 59 VRN A O AD 0.1uF AVSS 60 AIN4 A I Page. 100 [ ] 39%(-8.19dB) 0.033uF NC 61 VRP A O AD 0.1uF AVSS 62 AIN5 A I Page. 100 [ ] 39%(-8.19dB) 0.033uF NC MS0973-J /05
11 No. I/O 63 AVDD A P 64 AIN6 A I Page. 100 [ ] 39%(-8.19dB) 0.033uF NC A :AVDD, D :DVDD, P1 :PVDD1, P2 :PVDD2 I/O I :, O :, I/O :, P :, G : (*1) OE, PDN, RSTN OE PDN RSTN Output1 (*2) Output2 (*2) L x x Hi-z L H L x L L H H L L L H Defalt Data Out (*3) Defalt Data Out (*3) (*2) Output1 : DATA[7:0], HD, VD_F, DVALID_F, DTCLK Output2 : NSIG OE=H PDN=H (*3) AIN (Y=0x10, Cb/Cr=0x80) ( ) MS0973-J /05
12 4. (1) DVDD, AVDD PVDD1, PVDD2 A (VinA) D (VinD) AVDD ( 2.2) V -0.3 DVDD ( 2.2) V V V XTI, XTO, CLKMD, TEST0, TEST1 P1 (VioP1) -0.3 PVDD ( 4.2) V (*1) P2 (VioP2) -0.3 PVDD ( 4.2) V (*2) (Iin) ( ) ma C * (DVSS=AVSS) 0V( ) (AVSS, DVSS) (*1) DTCLK, DATA[7:0], HD, VD_F, DVALID_F, H_CSYNC, VSYNC (*2) OE, SELA, PDN, RSTN, SDA, SCL, NSIG (2) (AVDD) * (DVDD) * V AVDD=DVDD I/O (PVDD1) * PVDD1 DVDD V I/F (PVDD2) * PVDD2 DVDD (Ta) C * (DVSS=AVSS) 0V( ) (AVSS, DVSS) MS0973-J /05
13 (3) DC ( ) P2 H P2 L VPIH VPIL 0.8PVDD2 V *1 0.7PVDD2 V *2 0.2PVDD2 V *1 0.3PVDD2 V *2 D H VDIH 0.8DVDD V D L VDIL 0.2DVDD V H L VIH VIL 0.8PVDD1 V *1 0.7PVDD1 V *2 0.2PVDD1 V *1 0.3PVDD1 V *2 IL 10 ua P1 H VOH 0.7PVDD1 V IOH = -600uA P1 L VOL 0.3PVDD1 V IOL = 1mA P2 H VOH 0.7PVDD2 V IOH = -600uA P2 L VOL 0.3PVDD2 V IOL = 1mA I 2 C(SDA)L VOLC PVDD2 V IOLC = 3mA PVDD2 2.0V PVDD2<2.0V *1: < DVDD = 1.70V2.00V, DVDD PVDD1<2.70V, DVDD PVDD2<2.70V, Ta: C > *2: < DVDD = 1.70V2.00V, 2.70V PVDD1 3.60V, 2.70V PVDD2 3.60V, Ta: C > P2, SDA, SCL, SELA, OE, PDN, RSTN D CLKMD, TEST0, TEST1 H_CSYNC, VSYNC P1, DTCLK, DATA[7:0], HD, VD_F, DVALID_F, P2, NSIG SDA MS0973-J /05
14 (4) (AVDD=1.8V, 25 C) VIMX V PP PGA_GAIN PGA_GAIN PGA 7 bit GMN -6 db GMX 6 db GST db AD RES 10 bit FS 27 MHz INL LSB FS=27MHz, PGA_GAIN DNL LSB FS=27MHz, PGA_GAIN S/N SN 53 db Fin=1MHz*, FS=27MHz, PGA_GAIN S/(N+D) SND 51 db Fin=1MHz*, FS=27MHz PGA_GAIN IFGM 5 % PGA_GAIN ADC VCOM 0.9 V ADC VREF VRP 1.1 V ADC VREF VRN 0.7 V *Fin = AIN AAF (Anti-Aliasing Filter) Gp db 6MHz Gs db 27MHz (5) (DVDD = AVDD = PVDD1 = PVDD2 = 1.8V, Ta = C ) ( ) IDD ma RGB/YPbPr: 3ch AIDD 82 ma RGB/YPbPr: 3ch (63) ma YC: 2ch (*1) (34) ma : 1ch (*1) DIDD 22 ma Xtal I/O PIDD 4 ma : CL=15pF(*2) ( ) SIDD ua ASIDD 1 ua PDN=L(DVSS) (*3) DSIDD 1 ua I/O PSIDD 1 ua (*1) (*2) NTSC-J 100% (*3) OE RSTN MS0973-J /05
15 (6) (CLKMD=DVSS ) (Ta : ) f MHz f / f 100 ppm CL 15 pf Re 100 (*1) CO 0.9 pf XTI CXI 22 pf CL=15pF XTO CXO 22 pf CL=15pF (*1) Re = R1 x (1+CO/CL) 2 [R1]: Rf AK8854 XTI pin XTO pin Rd (* 2) CXI = 22pF CXO = 22pF (*2) (Rd) MS0973-J /05
16 AK8854VQ AK AC (DVDD=1.70V2.00V, PVDD1=DVDD3.60V, PVDD2=DVDD3.60V, ) CL=15pF (1) (CLKMD=DVDD ) AK8854 fclk tclkl tclkh 0.8DVDD 1/2 0.2DVDD CLK fclk MHz CLK H tclkh 16 nsec CLK L tclkl 16 nsec 100 ppm (2) (DTCLK ) DTCLK fdtclk 27 MHz fdtclk 0.5PVDD1 MS0973-J /05
17 (3) (DATA[7:0], HD, VD_F, DVALID_F) DTCLK 0.5PVDD1 tds tdh VOH OUTPUT DATA VOL Output Data Setup Time tds 10 nsec Output Data Hold Time tdh 10 nsec (4) ( ) RSTN VIL RESETTIMING fclk 100 CLK RSTN RESETTIMING CLK (4.1) (usec) * RSTN Low MS0973-J /05
18 (5) / PDN (PDN=Low) usec * 1 PDN (PDN=Hi) 10msec CLKIN RSTN RESs RESh VIH VIL PDN GND VIH STPI2C 2048 CLK PDN RESs (83.33) (usec) PDN=Hi RSTN=Hi RESh 10 msec I2C * 2 STPI2C 1 msec ViH/ViL * 1 * 2 I2C I2C AVDD/DVDD PVDD1/PVDD2 PDN RSTN XTI VCOM,VRP,VRN : 5 ms (max) * PDN RESh 10mS(min) * MS0973-J /05
19 (6) / (*1) AVDD/DVDD/PVDD1/PVDD2 (*2) VDD RSTN VIL VREF RESPON RSTN RESPON 10 msec (*1) (*2) PVDD2 AVDD/DVDD PVDD1 MS0973-J /05
20 (7)I2C (DVDD=1.70V2.00V, PVDD1=DVDD3.60V, PVDD2=DVDD3.60V, ) (7-1) 1 tbuf thd : STA tr tf tsu : STO SDA VIH VIL tf tr SCL VIH VIL tlow tsu : STA Bus Free Time tbuf 1.3 usec Hold Time (Start Condition) thd:sta 0.6 usec Clock Pulse Low Time tlow 1.3 usec Input Signal Rise Time tr 300 nsec Input Signal Fall Time tf 300 nsec Setup Time(Start Condition) tsu:sta 0.6 usec Setup Time(Stop Condition) tsu:sto 0.6 usec I2C I2C I2C (7-2) 2 thd : DAT SDA VIH VIL thigh SCL VIH VIL TSU : DAT Data Setup Time tsu:dat 100(*1) nsec Data Hold Time thd:dat (*2) usec Clock Pulse High Time thigh 0.6 usec (*1)I2C tsu:dat 250nSec (*2)AK8854 tlow (tlow= ) MS0973-J /05
21 6. [1] AK8854 () S-Video YPbPr RGB 10ch [2] AK8854 AD ( ) [3] AK8854 ADC ( ) [4] AK8854 S-Video NTSC-M,J NTSC-4.43 PAL-B,D,G,H,I,N PAL-Nc PAL-M PAL-60 SECAM ( ) [5] AK8854 VBI ITU-R BT.601 [6] AK8854 AGC [7] AK8854 ACC [8] AK Y/C Y/C [9] AK8854 [10] AK AK8854 [11] AK8854 PAL-B,D,G,H,I,N [12] AK8854 ITU-R BT.656 ( ) [13] AK8854 ITU-R BT.656 (Active Video) DVALID [14] AK8854 PGA PGA -6+6dB 0.1dB/Step [15] AK8854 PLL [16] AK8854 [17]AK8854 MS0973-J /05
22 [18] AK8854 [19] AK8854 VBI Closed Caption Data, Closed Caption Extended Data, VBID(CGMS), WSS [20] AK8854 [21] AK8854 Macrovision (RGB ) [22] AK8854 C Low Pass Filter U/V [23] AK8854 YC C MS0973-J /05
23 7. < > AK ch () S-Video(Y/C) YPbPr RGB AINSEL[7:0] 14 Sub Address 0x00_[7:0] AINSEL[7:0]-bit [ ] AIN1 () [ ] AIN2 () [ ] AIN3 () [ ] AIN4 () [ ] AIN5 () [ ] AIN6 () [ ] AIN6(Y) / AIN7(C) [ ] AIN5(Y) / AIN8(C) [ ] AIN4(Y) / AIN9(C) [ ] AIN3(Y) / AIN10(C) [ ] AIN6(Y) / AIN7(Pb) / AIN9(Pr) [ ] AIN6(G) / AIN7(R) / AIN9(B) [ ] AIN5(Y) / AIN8(Pb) / AIN10(Pr) [ ] AIN5 (G)/ AIN8(R) / AIN10(B) AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AINSEL[7:0] [ ] AIN1 () [ ] AIN2 () [ ] AIN3 () [ ] AIN4 () [ ] AIN5 () [ ] AIN6 () MS0973-J /05
24 S-Video Y C AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AINSEL[7:0] [ ] AIN1 () [ ] AIN2 () [ ] AIN3 () [ ] AIN4 () [ ] AIN5 () [ ] AIN6(Y) / AIN7(C) YPbPr Y Pb Pr AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AINSEL[7:0] [ ] AIN1 () [ ] AIN2 () [ ] AIN3 () [ ] AIN4 () [ ] AIN5 () [ ] AIN6(Y) / AIN7(Pb) / AIN9(Pr) RGB G R B AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AINSEL[7:0] [ ] AIN1 () [ ] AIN2 () [ ] AIN3 () [ ] AIN4 () [ ] AIN5 () [ ] AIN6(G) / AIN7(R) / AIN9B) MS0973-J /05
25 S-Video Y 1 Y 2 C 2 C 1 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AINSEL[7:0] [ ] AIN1 () [ ] AIN2 () [ ] AIN3 () [ ] AIN4 () [ ] AIN5(Y) / AIN8(C) [ ] AIN6(Y) / AIN7(C) S-Video YPbPr Y 1 Y 2 C 2 Pb 1 Pr 1 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AINSEL[7:0] [ ] AIN1 () [ ] AIN2 () [ ] AIN3 () [ ] AIN4 () [ ] AIN6(Y) / AIN7(C) [ ] AIN5(Y) / AIN8(Pb) / AIN10(Pr) S-Video RGB G Y C R B AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AINSEL[7:0] [ ] AIN1 () [ ] AIN2 () [ ] AIN3 () [ ] AIN4 () [ ] AIN6(Y) / AIN7(C) [ ] AIN5(G) / AIN8(R) / AIN10(B) MS0973-J /05
26 YPbPr Y 1 Y 2 Pb 2 Pb 1 Pr 2 Pr 1 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AINSEL[7:0] [ ] AIN1 () [ ] AIN2 () [ ] AIN3 () [ ] AIN4 () [ ] AIN6(Y) / AIN7(Pb) / AIN9(Pr) [ ] AIN5(Y) / AIN8(Pb) / AIN10(Pr) RGB G 1 G 2 R 2 R 1 B 2 B 1 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AINSEL[7:0] [ ] AIN1 () [ ] AIN2 () [ ] AIN3 () [ ] AIN4 () [ ] AIN6(G) / AIN7(R) / AIN9(B) [ ] AIN5(G) / AIN8(R) / AIN10(B) YPbPr RGB G Y Pb R Pr B AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AINSEL[7:0] [ ] AIN1 () [ ] AIN2 () [ ] AIN3 () [ ] AIN4 () [ ] AIN6(Y) / AIN7(Pb) / AIN9(Pr) [ ] AIN5(G) / AIN8(R) / AIN10(B) MS0973-J /05
27 S-Video Y 1 Y 2 Y 3 C 3 C 2 C 1 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AINSEL[7:0] [ ] AIN1 () [ ] AIN2 () [ ] AIN3 () [ ] AIN4(Y) / AIN9(C) [ ] AIN5(Y) / AIN8(C) [ ] AIN6(Y) / AIN7(C) S-Video YPbPr Y 1 Y 2 Y 3 C 3 C 1 Pb 2 Pr 2 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AINSEL[7:0] [ ] AIN1 () [ ] AIN2 () [ ] AIN3 () [ ] AIN4(Y) / AIN9(C) [ ] AIN6(Y) / AIN7(C) [ ] AIN5(Y) / AIN8(Pb) / AIN10(Pr) S-Video RGB Y 1 C 1 G R B Y 2 C 2 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AINSEL[7:0] [ ] AIN1 () [ ] AIN2 () [ ] AIN3 () [ ] AIN4(Y) / AIN9(C) [ ] AIN6(Y) / AIN7(C) [ ] AIN5(G) / AIN8(R) / AIN10(B) MS0973-J /05
28 S-Video Y 1 Y 2 Y 3 Y 4 C 4 C 3 C 2 C 1 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AINSEL[7:0] [ ] AIN1 () [ ] AIN2 () [ ] AIN3(Y) / AIN10(C) [ ] AIN4(Y) / AIN9(C) [ ] AIN5(Y) / AIN8(C) [ ] AIN6(Y) / AIN7(C) <, > [ ] AK8854 AD ( ) 1dB ( 6MHz ) -22dB ( 27MHz ).Typical [ ] AK8854 AK8854 ( ) AK8854 S-Video (Y ) AK8854 Y AK8854 ( ) (C ) AK8854 C Y ( ) MS0973-J /05
29 YPbPr YPBPRCP: YPbPr Sub-address 0x02_[4] YPBPRCP-bit Y: [0] Pb, Pr: Y: [1] * Pb, Pr: *PbPr RGB Sync On Green (G ) AK8854 G AK8854 ( ) (B,R ) AK8854 B,R G ( ) B,R (ALLSYNC=[1] ) RGB H/VSYNC CSYNC (R,G,B ) AK8854 RGB (HSYNC CSYNC) ( ) RGB (ALLSYNC=[1] ) RGB ALLSYNC RGB Sub-address 0x03_[0] ALLSYNC-bit [0] (SOG): R B * (C. H/ V): RGB [1] (SOG): R B (C. H/ V): RGB *(SOG): Sync On Green (C, H/ V): CSYNC H/VSYNC MS0973-J /05
30 Y C G Y Pb B Pr R MS0973-J /05
31 CLPWIDTH[1:0] Sub-address 0x01_[7:6] CLPWIDTH[1:0]-bit [00] 275nsec [01] 555nsec [10] 1.1usec [11] 2.2usec CLPSTAT[1:0] Sub-address 0x01_[5:4] CLPSTAT[1:0]-bit [00] / / [01] (1/128)H [10] (2/128)H [11] (1/128)H BCLPSTAT[2:0] Sub-address 0x01_[2:0] BCLPSTAT[1:0]-bit [000] CLPSTAT [001] CLPSTAT (1/128)H [010] CLPSTAT (2/128)H [011] CLPSTAT (3/128)H [100] CLPSTAT (4/128)H [101] CLPSTAT (3/128)H [110] CLPSTAT (2/128)H [111] CLPSTAT (1/128)H CLPSTAT BCLPSTAT CLPSTAT BCLPSTAT MS0973-J /05
32 CLPWIDTH[1:0] CLPSTAT[1:0] = 00 CLPSTAT[1:0] = 01 CLPSTAT[1:0] = 11 1/128H 1/128H / / CLPSTAT[1:0] = 10 2/128H CLPSTAT[1:0] = 00 BCLPSTAT[2:0] = 000 CLPWIDTH[1:0] CLPSTAT[1:0] =10 BCLPSTAT[2:0] = 000 CLPSTAT[1:0] =10 BCLPSTAT[2:0] = 111 2/128H 3/128H CLPSTAT[1:0] =10 BCLPSTAT[2:0] = 000 2/128H CLPG[1:0] Sub-address 0x02_[1:0] CLPG[1:0]-bit [00] Min. [01] Middle 1 (Default ) [10] Middle 2 [11] Max. Middle 1 = (Min. x 3 ) Middle 2 = (Min. x 5 ) Max. = (Min. x 7 ) UDG[1:0] Sub-address 0x02_[3:2] UDG[1:0]-bit [00] Min. (Default ) [01] Middle 1 [10] Middle 2 [11] Max. Middle 1 = (Min. x 2 ) Middle 2 = (Min. x 3 ) Max. = (Min. x 4 ) ADC ( ) MS0973-J /05
33 < > AK8854 S-Video NTSC-M, J NTSC-4.43 PAL-B, D, G, H, I, N PAL-Nc PAL-M PAL-60 SECAM VSCF[1:0]-bit : Sub-address 0x04_[1:0] VSCF[1:0]-bit (MHz) [00] NTSC-M,J [01] PAL-M [10] PAL-Nc [11] PAL-B,D,G,H,I,N, NTSC-4.43, PAL-60 SECAM* * SECAM VSCF[1:0] [11] VCEN[1:0]-bit : Sub-address 0x04_[3:2] VCEN[1:0]-bit [00] NTSC [01] PAL [10] SECAM YPBPr RGB [11] Reserved VLF-bit : 1 Sub-address 0x04_[4] VLF-bit (Lines) [0] 525 NTSC-M,J, NTSC-4.43, PAL-M, PAL-60 [1] 625 PAL-B,D,G,H,I,N,Nc, SECAM BW-bit : ( ) Sub-address 0x04_[5] BW-bit [0] ( OFF) [1] ( ON) AD Luminance Process ON YC YC Cb/Cr 0x80(601 ) S-Video SETUP-bit : Setup Sub-address 0x04_[6] SETUP-bit SETUP [0] Setup [1] Setup 7.5IRE Setup Setup : Y=(Y-7.5)/0.925 : U=U/0.925, V=V/0.925 MS0973-J /05
34 YPbPr EIA A EIA A 525Lines (YPbPr) 625Lines (YPbPr) VLF-bit : 1 Sub-address 0x04_[4] VLF-bit (Lines) [0] 525 [1] 625 BW-bit : ( ) Sub-address 0x04_[5] BW-bit [0] ( OFF) [1] ( ON) SETUP-bit : Setup Sub-address 0x04_[6] SETUP-bit SETUP [0] Setup [1] Setup 7.5IRE Setup Setup : Y=(Y-7.5)/0.925 : U=U/0.925, V=V/0.925 CSSL-bit: Y Sub-address 0x03_[1] CSSL-bit (mv) [0] 300 EIA A [1] 286 EIA A RGB [SMPTE-253M] 525Lines RGB 625Lines RGB VLF-bit: 1 Sub-address 0x04_[4] VLF-bit (Lines) [0] 525 [1] 625 RGBSS[1:0]-bit: RGB Sub-address 0x03_[4:3] RGBSS-bit [00] Sync On Green [01] CSYNC [10] H/VSYNC [11] Reserved BW-bit : ( ) Sub-address 0x04_[5] BW-bit [0] ( OFF) [1] ( ON) RGB->YCbCr MS0973-J /05
35 SETUP-bit : Setup Sub-address 0x04_[6] SETUP-bit SETUP [0] Setup [1] Setup 7.5IRE Setup Setup RGB->YCbCr : Y=(Y-7.5)/0.925 : U=U/0.925, V=V/0.925 ALLSYNC RGB Sub-address 0x03_[0] ALLSYNC-bit [0] (SOG): R B (C. H/ V): RGB * [1] (SOG): R B (C. H/ V): RGB *(SOG): Sync On Green (C, H/ V): CSYNC H/VSYNC CSSL-bit: (100IRE) Sub-address 0x03_[1] CSSL-bit (mv) / (100IRE) (mv) [0] 300 / 700 [1] 286 / 714 CSCL-bit:: Sub-address 0x03_[2] CSCL-bit [0] 700mV [1] 714mV CSSL CSCL CSSL-bit CSCL-bit / (100IRE) [0] 300mV/ 700mV [0] / (100IRE) [1] 300mV/ 700mV 714mV / (100IRE) [0] 286mV/ 714mV 700mV [1] / (100IRE) [1] 286mV/ 714mV MS0973-J /05
36 AK8854 H/VSYNC CSYNC H/VSYNC CSYNC CSY[1: 0]-bit: Sub-address 0x03_[6:5] CSY-bit [00] CSYNC1 4 [01] CSYNC5 H/VSYNC [10] CSYNC6.14 [11] Reserved CSY[1:0] MS0973-J /05
37 a (usec) b (usec) c (usec) d (usec) (Typical) (=b/2) (=a/2) MS0973-J /05
38 a (usec) b (usec) c (usec) d (usec) (Typical) (=b/2) 32 (=a/2) MS0973-J /05
39 a (usec) b (usec) c (usec) d (usec) (Typical) (=b/2) (=a/2) MS0973-J /05
40 a (usec) b (usec) c (usec) d (usec) (Typical) (=b/2) 32 (=a/2) MS0973-J /05
41 VLSTR[1: 0]-bit: CSY=[01] [10] Sub-address 0x09_[1:0] VLSTR-bit 525 (Odd/ Even) 625 (Odd/ Even) [00] Line 4 / Line Line 1/ Line [01] Line 3 / Line Line 625/ Line [10] Line 2 / Line Line 624/ Line [11] Line 1 / Line Line 623/ Line VLSTP[2: 0]-bit: CSY=[01] [10] Sub-address 0x09_[4:2] VLSTP-bit 525 (Odd/ Even) 625 (Odd/ Even) [000] Line 4 / Line Line 1/ Line [001] Line 5 / Line Line 2/ Line [010] Line 6 / Line Line 3/ Line [011] Line 7 / Line Line 4/ Line [100] Line 8 / Line Line 5/ Line [101] Line 9 / Line Line 6/ Line [110] Line 10 / Line Line 7/ Line CSYNC5 CSYNC6 VLSTR=[11] VLSTP=[110] CSYNC14 H/VSYNC VLSTR=[00] VLSTP=[010] VLSTR/ VLSTP 12 3 CSDLY[2: 0]-bit:: RGB Sub-address 0x09_[7:5] CSYDLY-bit [000] RGB [001] RGB [010] RGB 2 [011] RGB 3 [100] RGB 4 [101] RGB 3 [110] RGB 2 [111] RGB 1 MS0973-J /05
42 < > S-Video (YPbPr RGB ) AUTODET-bit : ( ) Sub-address 0x04_[7] AUTODET-bit [0] OFF [1] ON : 525/625 : : NTSC PAL SECAM * : / ( ON(COLKILL-bit = [1]) ) AK8854 Input Video Status Register (Sub-address 0x25) ( ) NTSC-M,J / NTSC-4.43 / PAL-B,D,G,H,I,N / PAL-M / PAL-Nc / PAL-60 / SECAM NTSC-M NTSC-J PAL-B,D,G,H,I,N YPbPr RGB 525Line/ 625Line MS0973-J /05
43 < > AK8854 NDMODE Register : Sub-address 0x06_[7:0] Bit Register Name Definition bit 0 NDPALM No Detect PAL-M bit bit 1 NDPALNC No Detect PAL-Nc bit bit 2 NDSECAM No Detect SECAM bit [0] : PAL-M [1] : PAL-M [0] : PAL-Nc [1] : PAL-Nc [0] : SECAM [1] : SECAM bit 3 Reserved Reserved Reserved bit 4 NDNTSC443 No Detect NTSC-4.43 bit bit 5 NDPAL60 No Detect PAL-60 bit bit 6 ND525L No Detect 525Line bit bit 7 ND625L No Detect 625Line bit [0] : NTSC-4.43 [1] : NTSC-4.43 [0] : PAL-60 [1] : PAL-60 [0] : 525Line [1] : 525Line [0] : 625Line [1] : 625Line YPbPr RGB ND525L ND625L [1] NDNTSC443(bit 4) NDPAL60(bit 5) [1](High) [2] ND525L(bit 6) ND625L(bit 7) [1](High) [3] OFF ON OFF Input Video Standard Register NDMODE Register ON MS0973-J /05
44 < > AK8854 VBIL[2:0]-bit : Sub-address 0x05_[2:0] VBIL[2:0]-bit 525/625 [001] 525 Line1Line20 Line263.5Line Line623.5Line23 Line311Line Line [010] 525 Line1Line21 Line263.5Line Line623.5Line24 Line311Line Lines [011] 525 Line1Line22 Line263.5Line Line623.5Line25 Line311Line Lines [000] 525 Line1Line19 Line263.5Line Line623.5Line22 Line311Line335.5 [101] 525 Line1Line16 Line263.5Line Line623.5Line19 Line311Line Lines [110] 525 Line1Line17 Line263.5Line Line623.5Line20 Line311Line Lines [111] 525 Line1Line18 Line263.5Line Line623.5Line21 Line311Line Line [100] Reserved Reserved 525 : Line1Line19 Line263.5Line : Line623.5Line22 Line311Line LIMIT-bit : Min / Max Sub-address 0x05_[3] 601LIMIT-bit MinMax [0] Y: 1254 Cb, Cr: 1254 [1] Y: Cb, Cr: AK8854 ITU-R BT.601 (Y:Cb:Cr=4:2:2) Min=1,Max= LIMIT-bit [1] 115, ,235 TRSVSEL-bit : ITU-R BT.656 EAV/SAV V-bit Sub-address 0x05_[4] TRSVSEL-bit V-bit=0 V-bit=1 V-bit=0 V-bit=1 [0] ITU-R BT [1] ITU-R BT SMPTE125M Line10Line263 Line273Line525 Line20Line263 Line283Line525 VBIL[2:0]-bit Line1Line9 Line264Line272 Line1Line19 Line264Line282 Line23Line310 Line336Line623 Line1Line22 Line311Line335 Line624Line625 MS0973-J /05
45 SLLVL-bit : Sub-address 0x05_[5] SLLVL-bit [0] 25IRE [1] 50IRE AK8854 S-Video YCbCr VBI ITU-R BT.601 VBI VBIL[2:0]-bit VBI 601 Cb/Cr Hi/Low Slice Data Set Register (Sub-address 0x18_[7:0] Sub-address 0x19_[7:0]) Hi Slice Data Set Register* : 2 High 0xEB(235) Low Slice Data Set Register* : 2 Low 0x10(16) *0x00 0xFF 601 VBIDEC[1:0]-bit : VBI Sub-address 0x05_[7:6] VBIDEC[1:0]-bit [00] Y = 0x10 Cb/Cr = 0x80 [01] Y = 601 Cb/Cr = 0x80 [10] Y/Cb/Cr = (Hi/Low Slice Data Set Register ) [11] Reserved Reserved * Line1 Line9, Line263.5 Line272.5 (525Line ) Line623.5 Line6.5, Line311 Line318 (625Line ) VBIDEC[1:0] MS0973-J /05
46 * (mv) NTSC/PAL 601 Code 714/ % White 357/ SLLVL=[1] 50IRE 180/ SLLVL=[0] 25IRE L L ```` L L H H ```` H H L L: Low Slice Data Set Register H: High Slice Data Set Register ````` Cb/Y `````` Cr/Y Cb/Y `````` Cr/Y ``````` * (mv) Cb/Y Cr/Y YPbPr RGB VBIDEC[1:0]=[00]( ) MS0973-J /05
47 < > Output Control Register DATA[7:0], VD_F, DVALID_F, NSIG, HD Low (* OE, PDN, RSTN ) <VLOCK > AK VLOCK VLOCK UnLock UnLock [VLOCK-bit] VLOCK 4 < > AK8854 YCDELAY[2:0]-bit : YC Sub-address 0x08_[2:0] YCDELAY[2:0]-bit [001] Y C 1sample 74nsec [010] Y C 2sample 148nsec [011] Y C 3sample 222nsec [000] Y/C [101] Y C 3sample 222nsec [110] Y C 2sample 148nsec [111] Y C 1sample 74nsec [100] Reserved *2 C sample 1sample 74nsec YCDELAY[2:0] = [000] Cb0 Y0 Cr0 Y1 Cb1 Y2 Cr1 Y3 Cb2 Y4 Cr2 Y5 Y/C default YCDELAY[2:0] = [111] Cb0 Y857 Cr0 Y0 Cb1 Y1 Cr1 Y2 Cb2 Y3 Cr2 Y4 1sample delay YCDELAY[2:0] = [001] Cb0 Y1 Cr0 Y2 Cb1 Y3 Cr1 Y4 Cb2 Y5 Cr2 Y6 1sample adv. DTCLK MS0973-J /05
48 ACTSTA[2:0]-bit : Sub-address 0x08_[6:4] ACTSTA[2:0]-bit [001] 525 Line Active video 124sample 625 Line Active video 134sample 74nsec [010] 525 Line Active video 125sample 625 Line Active video 135sample 148nsec [011] 525 Line Active video 126sample 625 Line Active video 136sample 222nsec [000] 525 Line Active video 123sample 625 Line Active video 133sample [101] 525 Line Active video 120sample 625 Line Active video 130sample 222nsec [110] 525 Line Active video 121sample 625 Line Active video 131sample 148nsec [111] 525 Line Active video 122sample 625 Line Active video 132sample 74nsec [100] Reserved Reserved (ITU-R BT.601 ) O H O H 122sample(525Line) Active video start 132sample(625Line) Active video start <Auto Gain Control _ AGC> AK8854 AGC ( ) 286mV / 300mV PGA AGC AD AK8854 AGC AGC AGC AGC AGC S-Video NTSC-M,J, NTSC-4.43, PAL-M..286mV PAL-B,D,G,H,I,N, PAL-Nc, PAL-60, SECAM. 300mV YPbPr RGB CSSL AGC Y G Pb, Pr B, R Y G * H/VSYNC CSYNC RGB AGC Disable *Pb, Pr Pb, Pr MS0973-J /05
49 AGCT[1:0]-bit : AGC Sub-address 0x0A_[1:0] AGCT[1:0]-bit [00] Disable AGC OFF PGA [01] Fast T= 1Field [10] Middle T= 7Fields [11] Slow T= 29Fields T AGC Disable PGA H/VSYNC CSYNC RGB AGC Disable AGCC-bit : AGC Sub-address 0x0A_[3:2] AGCC[1:0]-bit [00] 2LSB [01] 3LSB [10] 4LSB [11] AGCFRZ-bit : AGC Sub-address 0x0A_[4] AGCFRZ-bit AGC [0] [1] PGA1,2 Control Register AGCTL-bit : AGC AGC Sub-address 0x0B_[0] AGCTL-bit AGC [0] Quick [1] Slow <Auto Color Control _ ACC> AK8854 ACC SECAM YPbPr RGB 286mV / 300mV AGC NTSC-M,J, NTSC-4.43, PAL-M..286mV PAL-B,D,G,H,I,N, PAL-Nc, PAL mV ACCT[1:0]-bit : ACC Sub-address 0x0A_[6:5] ACCT[1:0]-bit [00] Disable ACC OFF [01] Fast T= 2Fields [10] Middle T= 8Fields [11] Slow T= 30Fields MS0973-J /05
50 ACCFRZ-bit : ACC Sub-address 0x0A_[7] ACCFRZ-bit ACC [0] [1] ACC (Satulation) ACC Enable ACC <Y/C > AK Y/C Y/C NTSC-4.43, PAL-60, SECAM 1 Y/C YCSEP[1:0]-bit : Y/C Sub-address 0x0C_[1:0] YCSEP[1:0]-bit YC [00] Y/C [01] 1 Y/C 1 (BPF)Y/C [10] 2 Y/C (NTSC-M,J, PAL-M) : 3Line2 Y/C (PAL-B,D,G,H,I,N,Nc) : 5Line2 Y/C (*1) [11] Reserved * NTSC-4.43, PAL-60, SECAM 1 Y/C <C > AK8854 YC C C358FIL[1:0] : 3.58MHz C Sub-address 0x0B_[2:1] C358FIL[1:0] -bit C [00] Narrow [01] Medium [10] Wide NTSC-M,J, PAL-M, PAL-Nc [11] Reserved MS0973-J /05
51 C443FIL[1:0] : 4.43MHz C Sub-address 0x0B_[4:3] C443FIL[1:0] -bit C [00] Narrow [01] Medium [10] Wide PAL-B,D,G,H,I,N, NTSC-4.43, PAL-60 [11] Reserved *SECAM <U/ V > AK8854 S-Video C Low Pass Filter U/ V RGB U/ V Low Pass Filter UVFILSEL[1:0]-bit : U/ V [ S-Video ] Sub-address 0x0C_[3:2] UVFILSEL[1:0] bit U/V [X0] Wide 1 [X1] Narrow 1 MS0973-J /05
52 [YPbPr RGB ] Sub-address 0x0C_[3:2] UVFILSEL -bit U/V [00] Middle 1 [01] Middle 2 [10] Wide 2 Narrow 2 < Middle 1 < Middle 2 < Wide 2 [11] Narrow 2 < > AK8854 ON/OFF AUTO ON/OFF OFF ON ON INTPOL[1:0]-bit : Sub-address 0x0C_[5:4] INTPOL[1:0]-bit [00] Auto [01] ON [10] OFF [11] Reserved MS0973-J /05
53 < > AK PLL PLL 2. PLL PLL 3. PLL SAV(Start Active Video) (EAV ) 1 SAV EAV AK8854 ITU-R BT.656 ( ITU-R BT.656 ) ITU-R BT.656 CLKMODE[1:0]-bit : Sub-address 0x0C_[7:6] CLKMODE[1:0]-bit [00] [01] [10] [11] < > AK8854 S-Video PAL-B,D,G,H,I,N,Nc,60,M ON NTSC-M,J SECAM MS0973-J /05
54 DPAL[1:0]-bit : Sub-address 0x0D_[1:0] DPAL[1:0]-bit [00] [01] ON [10] OFF [11] Reserved YPbPr RGB DPAL[1:0]=[10] < > ( NOSIG-bit [1]) ( ) ( ) ( ) NSIGMD-bit : Sub-address 0x0D_[3:2] NSIGMD [1:0]-bit [00] [01] [10] ( ) [11] Reserved AK8854 NSIG S-Video Y C YPbPr Y C Sync On Green G B,R RGB CSYNC CSYNC G,B,R H/VSYNC HSYNC G,B,R VSYNC MS0973-J /05
55 < > [1] [ ] AK8854 ITU-R BT.656 ITU-R BT : 858 (525 ) / 864 (625 ) 1 : 525 / 625 AK8854 PLL ITU-R BT.656 AK8854 ITU-R BT.656 ( ) (a). ITU-R BT /625 ( 524/ /626 ) (b). * 858/864 * (b) ERRHND-bit : ITU-R BT.656 Sub-address 0x0D_[5:4] ERRHND-bit [00] Line Drop / Line Repeat Default [01] Pixel Drop / Pixel Repeat by Field [10] Pixel Drop / Pixel Repeat by Frame [11] Reserved MS0973-J /05
56 2. [ ] (24.576MHz) 27MHz ITU-R BT.656 SAV SAV EAV 720Pixel EAV SAV ( ) SAV EAV 720 pixels 858 / 864 ( NTSC / PAL ) pixels [2] DVALID AK8854 ITU-R BT.656 (Active Video) DVALID DVALID Low Active DVALID 122 / 132 (NTSC / PAL)Pixel ( ) 122/132 Pixels Video Signal HD DVALID CLK27MOUT D[7:0] Cb0 Y0 Cr0 Y1 Cb1 Y2 Cr1 Y3 Y718 Cr359 Y719 Active Video MS0973-J /05
57 < > AK8854 HD VD_F DVALID_F 525-Line 625-Line HD kHz 4.7[usec] kHz 4.7[usec] Low Low VD Line4Line6 Line266.5Line269.5 Line1Line3.5 Line313.5Line315 VD_F Low Low DVALID_F FIELD ODD-Field : Low, EVEN-Field : High DVALID Active-Low VD_F, DVALID_F VD_FSEL-bit : VD/FIELD Sub-address 0x07_[5] VD_FSEL-bit VD_F [0] VD [1] Field DVALID_FSEL-bit : DVALID/FIELD Sub-address 0x07_[6] DVALID_FSEL-bit DVALID_F [0] DVALID [1] Field 525Line ( ) HD VD FIELD EVEN ODD HD VD FIELD ODD EVEN 625Line ( ) HD VD FIELD EVEN ODD HD VD FIELD ODD EVEN Output Control Register, Control 0 Register DTCLK, HD, VD_F, DVALID_F MS0973-J /05
58 < Setup > AK8854 S-Video Setup YPbPr RGB Setup STUPATOFF-bit : Setup (Sub-address 0x0D_[6]) Setup : Y=(Y-7.5)/0.925 : U=U/0.925, V=V/0.925 Setup : AK8854 STUPATOFF-bit Setup-bit [ Setup ] Setup NTSC-M,J PAL-B,D,G,H,I,N PAL-Nc, 60 SECAM [0] [1] [0] [1] [0] [1] PAL-M NTSC-4.43 [0] [1] [0] [1] [0] [1] Setup MS0973-J /05
59 <PGA (Programable Gain Amp)> AK8854 PGA PGA -66dB 0.1dB/Step PGA[7:0]-bit : PGA (Sub-address 0x0E_[6:0] 0x0F_[6:0]) AGC AGC Enable PGA[7:0]-bit AGC Disable PGA H/VSYNC CSYNC RGB AGC PGA PGA1, Y, G PGA2 C, Pb Pr, B, R AK %(-8.19dB) < > AK8854, Y, Sync on Green, Y 10bit (ITU-R BT.601 ) -8+7LSB 1LSB 0.4LSB BKLVL[3:0]-bit : Sub-address 0x10_[3:0] BKLVL[3:0]-bit 601 [0001] 1 0.4LSB [0010] 2 0.8LSB [0011] 3 1.2LSB [0100] 4 1.6LSB [0101] 5 2.0LSB [0110] 6 2.4LSB [0111] 7 2.8LSB [0000] [1000] 8 3.2LSB [1001] 7 2.8LSB [1010] 6 2.4LSB [1011] 5 2.0LSB [1100] 4 1.6LSB [1101] 3 1.2LSB [1110] 2 0.8LSB [1111] 1 0.4LSB 2 MS0973-J /05
60 < >, Y Sync on Green (286mV/300mV) 16(8-Bit, ITU-R BT.601 ) DPCT[1:0]-bit : Sub-address 0x10_[5:4] DPCT[1:0]-bit [00] Fast [01] Middle [10] Slow [11] Disable OFF DPCC[1:0]-bit : (Coring Level) Sub-address 0x10_[7:6] DPCC[1:0]-bit [00] 1bit [01] 2bit [10] 3bit [11] < > S-Video AK8854 AK8854 Cb/Cr 0x80 PLL COLKILL-bit: ON/OFF ON Sub-address 0x11_[7] COLKILL-bit [0] Enable [1] Disable CKLVL[3:0]-bit: [1000] = -23dB CKSCM[1:0]-bit: SECAM SECAM CKLVL[3:0]-bit 2 CKILSEL: Sub-address 0x0D_[7] CKILSEL-bit [0] CKLVL[3:0]-bit [1] CKLVL[3:0]-bit PLL MS0973-J /05
61 < > AK8854 * 1. (Sub-address 0x12_[7:0]) CONT[7:0]-bit: (0x80) Contrast Control Register CONTSEL=[0] YOUT = (CONT / 128) x (YIN 128) CONTSEL=[1] YOUT = (CONT / 128) x YIN YOUT : YIN : CONT : ( ) 0255 [254]/ [1] ( 601LIMIT [1] ) CONTSEL-bit : Sub-address 0x11_[6] CONTSEL -bit [0] 128 [1] 0 2. (Sub-address 0x13_[7:0]) BR[7:0]-bit: 2 (0x00) ITU-R BT.601 8Bit ( ) YOUT = YIN+BR YOUT : YIN : BR : ( ) (1step) 2 [254]/ [1] ( 601LIMIT [1] ) 3. (Saturation) SAT[7:0]-bit : (0x80) 0255/128(1/128steps) [ S-Video ] (Sub-address 0x15_[7:0]) U/V [YPbPr RGB ] (Sub-address 0x15_[7:0] Sub-address 0x16_[7:0]) U/ V U/ V MS0973-J /05
62 4. (HUE) (Sub-address 0x17_[7:0]) HUE[7:0]-bit: 2 (0x00) AK ( 0.35 steps) S-video 5. SHARP[1:0]-bits SHCORE[1:0]-bits Filter Coring Delay SHARP[1:0]-bit: Sub-address 0x14_[1:0] SHARP[1:0]-bit [00] [01] Min [10] Middle [11] Max SHCORE[1:0]-bit: (Sub-address 0x14_[3:2]) SHCORE[1:0]-bit [00] [01] 1LSB [10] 2LSB [11] 3LSB VBIIMGCTL-bit: VBI ON/OFF (Sub-address 0x14_[7]) VBIIMGCTL -bit VBI [0] [1] YPbPr RGB VBIIMGCTL=[1] MS0973-J /05
63 < > MPEG LUMFIL[1:0]-bit : (Sub-address 0x14_[5:4]) LUMFIL [1:0]-bit [00] -3dB at 6.29MHz [01] Narrow -3dB at 2.94MHz [10] Mid -3dB at 3.30MHz [11] Wide -3dB at 4.00MHz < > AK8854 SEPIA-bit : (Sub-address 0x14_[6]) SEPIA bit [0] [1] <VBI Information > AK8854 VBI Closed Caption Data, Closed Caption Extended Data, VBID(CGMS), WSS Request VBI Information Register()-[3:0] AK8854 Status 2 Register(R)-[3:0] VBID (CGMS-A) CRCC MS0973-J /05
64 Closed Caption Line Line Closed Caption Extended Data Line Line VBID Line20 / 283 Line20 / Line 625-Line WSS Line Line Closed Caption 1 Register, Closed Caption 2 Register WSS 1 Register, WSS 2 Register Extended Data 1 Register, Extended Data 2 Register VBID 1 Register, VBID 2 Register < > NOSIG-bit: NOSIG bit [0] [1] VLOCK-bit: VLOCK VLOCK-bit [0] [1] COLKILON: (ON/OFF) COLKILON bit [0] [1] YPbPr RGB COLKILON Sub-address 0x22_[0] Sub-address 0x22_[1] Sub-address 0x22_[3] SCLKMODE -bit: SCLKMODE bit [00] [01] [10] [11] Reserved Sub-address 0x22_[5:4] PKWHITE: AGC Sub-address 0x22_[6] PKWHITE bit [0] [1] OVCOL: ACC Sub-address 0x22_[7] OVCOL bit [0] [1] YPbPr RGB OVCOL Status 2-Ragister: ClosedCaption, ExtendedData, VBID, WSS MS0973-J /05
65 REALFLD-bit: AK8854 Sub-address 0x23_[4] REALFLD -bit [0] Even [1] Odd AGCSTS-bit: AGC Sub-address 0x23_[5] AGCSTS -bit [0] AGC [1] AGC H/VSYNC CSYNC RGB AGCSTS Macrovision Status-Register: AK8854 S-Video YPbPr Macrovision Sub-address 0x24 Bit Register Name Definition bit 0 AGCDET AGC Process Detect R bit 1 CSDET Color Stripe Detect R bit 2 CSTYPE Color Stripe Type R bit 3 bit 7 Reserved Reserved R Reserved Macrovision AGC [0] : Macrovision AGC [1] : Macrovision AGC Macrovision Color Stripe [0] : Color Stripe [1] : Color Stripe [0] : Color Stripe Type2 [1] : Color Stripe Type3 RGB MS0973-J /05
66 Input Video Status-Register: BIT bit 0 bit 1 bit 2 bit 3 bit 4 Sub-address 0x25 Register Name ST_VSCF0 ST_VSCF1 ST_VCEN0 ST_VCEN1 ST_VLF Status of Video Sub-Carrier Frequency Status of Video Color Encode Status of Video Line Frequency bit 5 ST_BW Status of B/W Signal R bit 6 UNDEF Un_define bit R bit 7 FIXED Input Video Standard fixed bit R R R R Definition [ ST_VSCF1 : ST_VSCF0 ] ( MHz ) [00] : (NTSC-M,J) [01] : (PAL-M) [10] : (PAL-Nc) [11] : (PAL-B,D,G,H,I,N,60, NTSC-4.43) [ST_VCEN1 : ST_VCEN0] [00] : NTSC [01] : PAL [10] : SECAM [11] : Reserved (*1) [0] : 525 (NTSC-M,J, NTSC-4.43, PAL-M,60) [1] : 625 (PAL-B,D,G,H,I,N,Nc, SECAM) (*2) [0] : [1] : (*3) [0] : [1] : (*4) [0] : [1] : (*1)YPbPr RGB 525Lines, 625Lines ST_VLF YPbPr RGB UNDEF FIXED (*2) ON(COLKILL-bit = [1]) ST_BW-bit [1] Sub Adress 0x01 B/W-bit 525/625 ST_VLF YPbPr RGB B/W-bit (*3) [0] [1] (*4) [0] [1] UNDEF-bit = [1] FIXED-bit = [0] MS0973-J /05
67 VBI Closed Caption 1 Register Sub-address 0x26 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0 Closed Caption 2 Register Sub-address 0x27 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 CC15 CC14 CC13 CC12 CC11 CC10 CC9 CC8 WSS 1 Register Sub-address 0x28 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 G2-7 G2-6 G2-5 G2-4 G1-3 G1-2 G1-1 G1-0 WSS 2 Register Sub-address 0x29 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Reserved Reserved G4-13 G4-12 G4-11 G3-10 G3-9 G3-8 Extended Data 1 Register Sub-address 0x2A bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 EXT7 EXT6 EXT5 EXT4 EXT3 EXT2 EXT1 EXT0 Extended Data 2 Register Sub-address 0x2B bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 EXT15 EXT14 EXT13 EXT12 EXT11 EXT10 EXT9 EXT8 VBID 1 Register Sub-address 0x2C bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Reserved Reserved VBID1 VBID2 VBID3 VBID4 VBID5 VBID6 VBID 2 Register Sub-address 0x2D bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 VBID7 VBID8 VBID9 VBID10 VBID11 VBID12 VBID13 VBID14 MS0973-J /05
68 8. AK8854 I2C [ I2C SLAVE Address] I2C SELA [ ] [ ] [ I2C ] Slave Address SELA MSB LSB [Low] [High] (1) Write 1 AK Write 1 Write Write Sequential Write operation (a) 1 Write Slave S w A Address 8-bit 1- bit Sub Address 8-bit A Data A Stp 1- bit 8-bit 1- bit (b) (m-bytes) Write (Sequential Write Operation) Sub Slave Data S w A Address A Data(n) A A Address (n+1) (n) 8-bit 1- bit 8-bit 1- bit 8-bit 1- bit 8-bit 1- bit Data (n+m) 8-bit A 1- bit stp S (2) Read 1 AK Slave Address w A Sub Address (n) A rs Slave Address R A Data1 A Data 2 A Data3 A 8-bit 1 8-bit 1 8-bit 1 8-bit 1 8-bit 1 8-bit 1 Data n!a stp 8-bit 1 S : Start Condition rs : repeated Start Condition A : Acknowledge (SDA Low )!A : Not Acknowledge (SDA High) stp : Stop Condition 1 : Read 0 : Write : : AK8854 MS0973-J /05
69 9. Sub Address Default 0x00 Input Channel Select Register 0x00 0x01 AFE Control 1 Register 0x00 0x02 AFE Control 2 Register 0x01 0x03 Component Setting Control Register 0x00 YPbPr RGB 0x04 Input Video Standard Register 0x00 0x05 Output Format Regsiter 0x00 0x06 NDMODE Register 0x00 0x07 Output Control Register 0x00 0x08 Start and Delay Control Register 0x00 0x09 CSYNC Delay Control Register 0x08 0x0A AGC & ACC Control Register 0x00 AGC ACC 0x0B Control 0 Register 0x00 0x0C Control 1 Register 0x00 0x0D Control 2 Register 0x00 0x0E PGA Control 1 Register 0x3E PGA1 0x0F PGA Control 2 Register 0x3E PGA2 0x10 Pedestal Level Control Register 0x00 0x11 Color Killer Control Register 0x08 0x12 Contrast Control Register 0x80 0x13 Brightness Control Register 0x00 0x14 Image Control Register 0x00 0x15 Saturation / U tone Control Register 0x80 / U 0x16 V tone Control Register 0x80 V 0x17 HUE Control Register 0x00 HUE 0x18 High Slice Data Set Register 0xEB VBI High 0x19 Low Slice Data Set Register 0x10 VBI Low 0x1A Request VBI Infomation Register 0x00 VBI 0x1B Reserved Register 0x00 0x1C Reserved Register 0x00 0x1D Reserved Register 0x00 0x1E Reserved Register 0x00 0x1F Reserved Register 0x00 0x20 Reserved Register 0x00 0x21 Reserved Register 0x00 0x22 Status 1 Register R 0x23 Status 2 Register R 0x24 Macrovision Status Register R 0x25 Input Video Status Register R 0x26 Closed Caption 1 Register R Closed Caption 0x27 Closed Caption 2 Register R Closed Caption 0x28 WSS 1 Register R WSS 0x29 WSS 2 Register R WSS 0x2A Extended Data 1 Register R Closed Caption Extended 0x2B Extended Data 2 Register R Closed Caption Extended 0x2C VBID 1 Register R VBID 0x2D VBID 2 Register R VBID 0x2E Device and Revision ID Register R Device ID Revision Default MS0973-J /05
70 10. Input Channel Select Register () [Sub Address 0x00] Sub Address 0x00 Default Value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 AINSEL7 AINSEL6 AINSEL5 AINSEL4 AINSEL3 AINSEL2 AINSEL1 AINSEL0 Default Value Input Channel Select Register Definition Register Bit Name bit 0 bit 7 AINSEL0 AINSEL7 Analog Input Select R / W R / W Definition [AINSEL7 : AINSEL0 ] [ ]: AIN1 () [ ]: AIN2 () [ ]: AIN3 () [ ]: AIN4 () [ ]: AIN5 () [ ]: AIN6 () [ ]: AIN6(Y) / AIN7(C) [ ]: AIN5(Y) / AIN8(C) [ ]: AIN4(Y) / AIN9(C) [ ]: AIN3(Y) / AIN10(C) [ ]: AIN6(Y) / AIN7(Pb) / AIN9(Pr) * [ ]: AIN6(G) / AIN7(R) / AIN9(B) * [ ]: AIN5(Y) / AIN8(Pb) / AIN10(Pr) * [ ]: AIN5 (G)/ AIN8(R) / AIN10(B) * *YPbPr RGB Sub Address 0x0D DPAL[1:0] = [10] Sub Address 0x14 VBIMGCTL = [1] MS0973-J /05
71 AFE Control Register 1() [Sub Address 0x01] Sub Address 0x01 Default Value : 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 CLPWIDTH1 CLPWIDTH0 CLPSTAT1 CLPSTAT0 Reserved BCLPSTAT2 BCLPSTAT1 BCLPSTAT0 Default Value AFE Control Register 1 Definition Bit Register Name R / W Definition bit 0 bit 2 BCLPSTAT0 Back Porch Clamp Start R / W BCLPSTAT2 bit 3 Reserved Reserved R Reserved bit 4 bit 5 bit 6 bit 7 CLPSTAT0 CLPSTAT1 CLPWIDTH0 CLPWIDTH1 Clamp Start Clamp Pulse Width R / W R / W [ BCLPSTAT2 : BCLPSTAT0 ] [000]: CLPSTAT [001]: CLPSTAT (1/128)H [010]: CLPSTAT (2/128)H [011]: CLPSTAT (3/128)H [100]: CLPSTAT (4/128)H [101]: CLPSTAT (3/128)H [110]: CLPSTAT (2/128)H [111]: CLPSTAT (1/128)H [ CLPSTAT1 : CLPSTAT0 ] [00] : [01] : (1/128)H [10] : (2/128)H [11] : (1/128H) [ CLPWIDTH1 : CLPWIDTH0 ] [00] : 275nsec [01] : 555nsec [10] : 1.1usec [11] : 2.2usec MS0973-J /05
72 AFE Control Register 2() [Sub Address 0x02] Sub Address 0x02 Default Value: 0x01 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Reserved Reserved Reserved YPBPRCP UDG1 UDG0 CLPG1 CLPG0 Default Value AFE Control Register 2 Definition Register Bit Name bit 0 bit 1 bit 2 bit 3 CLPG 0 CLPG1 UDG 0 UDG 1 Clamp Gain Up Down Gain R / W R / W R / W bit 4 YPBPRCP YPbPr Clamp R / W bit 5 bit 7 Definition Reserved Reserved R / W Reserved [00]: Min. [01]: Middle 1 (Default) [10]: Middle 2 [11]: Max. [00]: Min. (Default) [01]: Middle 1 [10]: Middle 2 [11]: Max. YPbPr [0]: Y Pb,Pr [1]: Y Pb,Pr MS0973-J /05
73 Component Setting Control Register () [Sub Address 0x03] YPbPR RGB Sub Address 0x03 Default Value: 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Reserved CSY1 CSY0 RGBSS1 RGBSS0 CSCL CSSL ALLSYNC Default Value Component Setting Control Register Definition Register Bit R / W Name bit 0 ALLSYNC ALL Sync Select R / W bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 CSSL CSCL RGBSS0 RGBSS1 CSY0 CSY1 Component Signal Sync Level Component Signal Chroma Level RGB Sync Select CSYNC SELECT R / W R / W R / W R / W Definition bit 7 Reserved Reserved R / W Reserved RGB Sync On Green [0]: R B [1]: R B CSYNC H/VSYNC [0]: RGB [1]: RGB YPbPr RGB [0]: 300mV [1]: 286mV [0]: 700mV [1]: 714mV RGB [ RGBSS1: RGBSS0 ] [00]: Sync On Green [01]: CSYNC [10]: H/VSYNC [00]: Reserved RGB [ CSY1: CSY0 ] [00]: CSYNC1 4 [01]: CSYNC5 H/VSYNC [10]: CSYNC6 [11]: Reserved MS0973-J /05
74 Input Video Standard Register () [Sub Address 0x04] Sub Address 0x04 Default Value : 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 AUTODET SETUP BW VLF VCEN1 VCEN0 VSCF1 VSCF0 Default Value Input Video Standard Register Definition Register Bit Name bit 0 bit 1 bit 2 bit 3 VSCF0 VSCF1 VCEN0 VCEN1 Video Sub-Carrier Frequency Video Color Encode bit 4 VLF Video Line Frequency bit 5 BW Black & White bit 6 SETUP Setup bit 7 AUTODET Video Standard Auto Detect Definition [VSCF1 : VSCF0 ] ( MHz ) [00] : (NTSC-M,J) [01] : (PAL-M) [10] : (PAL-Nc) [11] : (PAL-B,D,G,H,I,N,60, NTSC-4.43, SECAM) * 1 [VCEN1 : VCEN0] [00] : NTSC [01] : PAL [10] : SECAM * 2 [11] : Reserved [0] : 525 (NTSC-M,J, NTSC-4.43, PAL-M,60) [1] : 625 (PAL-B,D,G,H,I,N, PAL-Nc, SECAM) [0] : OFF [1] : ON Setup [0] : Setup [1] : Setup [0] : OFF ( ) [1] : ON ( ) *1 SECAM VSCF[1:0] [11] *2 YPbPr RGB VCEN[1:0]=[10](SECAM) MS0973-J /05
75 Output Format Register () [Sub Address 0x05] Sub Address 0x05 Default Value : 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 VBIDEC1 VBIDEC0 SLLVL TRSVSEL 601LIMIT VBIL2 VBIL1 VBIL0 Default Value Output Format Register Definition Register Bit Name Definition 525LINE : Line1 Line19 / Line263.5 Line LINE : Line623.5 Line22 / Line311 Line335.5 VBI bit 0 bit 2 VBIL0 VBIL2 Vertical Blanking Length 1Line 525LINE : Line1 Line20 / Line263.5 Line LINE : Line623.5 Line23/ Line311 Line336.5 VBI 1Line 525LINE : Line1 Line18 / Line263.5 Line LINE : Line623.5 Line21/ Line311 Line334.5 VBI bit 3 601LIMIT 601 Output Limit [ VBIL2 : VBIL0 ] [001] : VBI 1Line [010] : VBI 2Line [011] : VBI 3Line [000] : Default( ) [101] : VBI 3Line [110] : VBI 2Line [111] : VBI 1Line [100] : Reserved Min - Max [0] : (Y/Cb/Cr) [1] : (Y) / (Cb/Cr) / 240 (Y / Cb,Cr) 240 MS0973-J /05
76 bit 4 TRSVSEL Time Reference Signal V Select Bit ITU-R BT.656 Timing reference signals V-bit 525LINE 0 V=1 (Line1 Line9 / Line264 Line272) V=0 (Line10 Line263 / Line273 Line525) 1 V=1 (Line1 Line19 / Line264 Line282) V=0 (Line20 Line263 / Line283 Line525) bit 5 SLLVL Slice Level bit 6 bit 7 VBIDEC0 VBIDEC1 VBI Decode 625LINE V=1 (Line1 Line22 / Line311 Line335 / Line624 Line625) V=0 (Line23 Line310 / Line336 Line623) [0] : 25IRE [1] : 50IRE Vertical Blanking Length * [ VBIDEC1 : VBIDEC0 ] [00] : [01] : [10] : [11] : Reserved *YPbPr RGB VBIDEC[1:0]=[00]( ) MS0973-J /05
77 NDMODE Register () [Sub Address 0x06] Sub Address 0x06 Default Value : 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ND625L ND525L NDPAL60 NDNTSC443 Reserved NDSECAM NDPALNC NDPALM Default Value NDMODE Register Definition Register Bit Name bit 0 NDPALM No Detect PAL-M bit bit 1 NDPALNC No Detect PAL-Nc bit bit 2 NDSECAM No Detect SECAM bit Definition [0] : PAL-M [1] : PAL-M [0] : PAL-Nc [1] : PAL-Nc [0] : SECAM [1] : SECAM bit 3 Reserved Reserved Reserved bit 4 NDNTSC443 No Detect NTSC-4.43 bit bit 5 NDPAL60 No Detect PAL-60 bit bit 6 ND525L No Detect 525Line bit bit 7 ND625L No Detect 625Line bit [0] : NTSC-4.43 [1] : NTSC-4.43 [0] : PAL-60 [1] : PAL-60 [0] : 525Line [1] : 525Line [0] : 625Line [1] : 625Line [1] NDNTSC443(bit 4) NDPAL60(bit 5) [1](High) [2] ND525L(bit 6) ND625L(bit 7) [1](High) [3] OFF ON MS0973-J /05
78 Output Control Register () [Sub Address 0x07] Output Sub Address 0x07 Default Value : 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 CLKINV DVALID_FSEL VD_FSEL HL NL DVALID_FL VD_FL DL Default Value Output Control Register Definition Bit Register Name Definition bit 0 DL D Output Low bit [0] : [1] : [D7 : D0 ] Low bit 1 VD_FL VD/FIELD Low bit [0] : [1] : VD_F Low bit 2 DVALID_FL DVALID/FIELD Low bit [0] : [1] : DVALID_F Low bit 3 NL NSIG Low bit [0] : [1] : NSIG Low bit 4 HL HD Low bit [0] : [1] : HD Low bit 5 VD_FSEL VD/FIELD Select bit VD_F [0] : VD [1] : FIELD bit 6 DVALID_FSEL DVALID/FIELD Select bit bit 7 CLKINV CLK Invert Set bit DVALID_F [0] : DVALID [1] : FIELD DTCLK [0] : [1] : (* OE, PDN, RSTN ) MS0973-J /05
79 Start and Delay Control Register () [Sub Address 0x08] Sub Address 0x08 Default Value : 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Reserved ACTSTA2 ACTSTA1 ACTSTA0 Reserved YCDELAY2 YCDELAY1 YCDELAY0 Default Value Start and Delay Control Register Definition Register Bit Name bit 0 bit 2 YCDELAY0 YCDELAY2 Y/C Delay Control Definition bit 3 Reserved Reserved Reserved bit 4 bit 6 ACTSTA0 ACTSTA2 Active Video Start Control bit bit 7 Reserved Reserved Reserved Y / C 1sample 13.5MHz ( 74nsec) [ YCDELAY2 : YCDELAY0 ] [001] : Y C 1sample [010] : Y C 2sample [011] : Y C 3sample [000] : Y/C [101] : Y C 3sample [110] : Y C 2sample [111] : Y C 1sample [100] : Reserved 1sample 13.5MHz ( 74nsec) [ ACTSTA2 : ACTSTA0 ] [001] : 1Sample [010] : 2Sample [011] : 3Sample [000] : [101] : 3Sample [110] : 2Sample [111] : 1Sample [100] : Reserved MS0973-J /05
80 CSYNC Delay Control Register () [Sub Address 0x09] CSYNC H/V Sub Address 0x09 Default Value : 0x08 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 CSDLY2 CSDLY1 CSDLY0 VLSTP2 VLSTP1 VLSTP0 VLSTR1 VLSTR0 Default Value CSYNC Delay Control Register Definition Register Bit Name bit 0 bit 1 bit 2 bit 4 VLSTR[1:0] VSYNC Line Start VLSTP[2:0] VSYNC Line Stop Definition RGB CSYNC H/VSYNC CSY=[01] [10] [VLSTR1: VLSTR0] 525 (ODD/EVEN) [00] : Line 4/ Line [01] : Line 3/ Line [10] : Line 2/ Line [11] : Line 1/ Line (ODD/EVEN) [00] : Line 1/ Line [01] : Line 625/ Line [10] : Line 624/ Line [11] : Line 623/ Line RGB CSYNC H/VSYNC CSY=[01] [10] [VLSTP2: VLSTP0] 525 (ODD/EVEN) [000]: Line 4/ Line [001]: Line 5/ Line [010]: Line 6/ Line [011]: Line 7/ Line [100]: Line 8/ Line [101]: Line 9/ Line [110]: Line 10/ Line (ODD/EVEN) [000]: Line 1/ Line [001]: Line 2/ Line [010]: Line 3/ Line [011]: Line 4/ Line [100]: Line 5/ Line [101]: Line 6/ Line [110]: Line 7/ Line MS0973-J /05
81 bit 5 bit 7 CSDLY[2:0] CSYNC Dealy (CSYNC H/VSYNC) RGB [CSDLY2: CSDLY0] [000]: RGB [001]: RGB [010]: RGB 2 [011]: RGB 3 [100]: RGB 4 [101]: RGB 3 [110]: RGB 2 [111]: RGB 1 MS0973-J /05
82 AGC & ACC Control Register () [Sub Address 0x0A] AGC ACC Sub Address 0x0A Default Value : 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ACCFRZ ACC1 ACC0 AGCFRZ AGCC1 AGCC0 AGCT1 AGCT0 Default Value AGC & ACC Control Register Definition Register Bit Name bit 0 bit 1 bit 2 bit 3 AGCT0 AGCT1 AGCC0 AGCC1 AGC Time Constant AGC Coring Control bit 4 AGCFRZ AGC Freeze bit 5 bit 6 ACCT0 ACCT1 ACC Time Constant bit 7 ACCFRZ ACC Freeze Definition AGC Disable PGA T * [ AGCT1 : AGCT0 ] [00] : Disable [01] : Fast [ T = 1Field ] [10] : Middle [ T =7Fields ] [11] : Slow [ T = 29Fields ] AGC [ AGCC1 : AGCC0 ] [00] : 2LSB [01] : 3LSB [10] : 4LSB [11] : AGC AGC [0] : [1] : ACC T [ ACCT1 : ACCT0 ] [00] : Disable [01] : Fast [ T = 2Fields ] [10] : Middle [ T =8Fields ] [11] : Slow [ T = 30Fields ] ACC ACC [0] : [1] : *H/VSYNC CSYNC RGB AGC AGCT[1:0]=[00] MS0973-J /05
83 Control 0 Register () [Sub Address 0x0B] Sub Address 0x0B Default Value : 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DVALID_FP VD_FP HDP C443FIL0 C443FIL0 C358FIL1 C358FIL0 AGCTL Default Value Control 0 Register Definition Register Bit Name bit 0 AGCTL AGC Transition Level bit 1 bit 2 bit 3 bit 4 C358FIL0 C358FIL1 C443FIL0 C443FIL1 C Filter_358 Select bit C Filter_443 Select bit bit 5 HDP HD Pin Polarity Set bit bit 6 VD_FP VD_F Pin Polarity Set bit bit 7 DVALID_FP DVALID_F Pin Polarity Set bit Definition AGC AGC [0] : Quick [1] : Slow 3.58MHz C [C358FIL1 : C358FIL0 ] [00] : 3.58 Narrow [01] : 3.58 Medium [10] : 3.58 Wide [11] : Reserved 4.43MHz C [C443FIL1 : C443FIL0 ] [00] : 4.43 Narrow [01] : 4.43 Medium [10] : 4.43 Wide [11] : Reserved HD [0] : Active Low [1] : Active High VD_F (VD ) [0] : Active Low [1] : Active High (Field ) [0] : Odd-Field Low, Even-Field High [1] : Even-Field Low, Odd-Field High DVALID_F (DVALID ) [0] : Active Low [1] : Active High (Field ) [0] : Odd-Field Low, Even-Field High [1] : Even-Field Low, Odd-Field High MS0973-J /05
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お客様各位 カタログ等資料中の旧社名の扱いについて 2010 年 4 月 1 日を以って NEC エレクトロニクス株式会社及び株式会社ルネサステクノロジが合併し 両社の全ての事業が当社に承継されております 従いまして 本資料中には旧社名での表記が残っておりますが 当社の資料として有効ですので ご理解の程宜しくお願い申し上げます ルネサスエレクトロニクスホームページ (http://www.renesas.com)
42PHD60123_ p65
R - STANDBY G POWER INPUT VOL ENTER N SURROUND VOL PLASMA DISPLAY INPUT SOUND SET UP MULTI ZOOM PIP SWAP SELECT MOVE POS. /SIZE PC R ASPECT TIMER 1234 TH-42PHD6 1234567 1234567 TH-5PHD6 1234567 1234567
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お客様各位 カタログ等資料中の旧社名の扱いについて 2010 年 4 月 1 日を以って NEC エレクトロニクス株式会社及び株式会社ルネサステクノロジが合併し 両社の全ての事業が当社に承継されております 従いまして 本資料中には旧社名での表記が残っておりますが 当社の資料として有効ですので ご理解の程宜しくお願い申し上げます ルネサスエレクトロニクスホームページ (http://www.renesas.com)
BRC-X1000
C-455-100-02(1) BRC-X1000/H800 2016 Sony Corporation 2 3 4 5 6 4 D E 5 6 7 A B C F G 7 8 9 0 qa qs SYSTEM SELECT IN IR SELECT VISCA RS - 422 OUT OSD OFF CAMERA SETUP 1 qd 2 3 4 5 6 7 8 LAN 12V qf HDMI
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DAC121S101 DAC121S101/DAC121S101Q 12-Bit Micro Power, RRO Digital-to-Analog Converter Literature Number: JAJSA89 DAC121S101 12 D/A DAC121S101 12 D/A (DAC) 2.7V 5.5V 3.6V 177 A 30MHz 3 SPI TM QSPI MICROWIRE
DS
FUJITSU SEMICONDUCTOR DATA SHEET DS4 272 1 ASSP (AC / DC ) BIPOLAR, IC,, 2 ma, 5 V SOP 16 1 AC/DC Copyright 1986-211 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 211.5 (TOP VIEW) IN1 1 16 IN2 IN1
????????????MUX ????????????????????
PGA116 PGA112 PGA113 PGA117 PGA112, PGA113 PGA116, PGA117 www.tij.co.jp µµ µµ ± µ +5V +3V AV DD 1 C BYPASS.1µF DV DD C BYPASS.1µF C BYPASS.1µF V CAL/CH CH1 3 2 1kΩ MUX CAL1 PGA112 PGA113 R F 1 Output Stage
ADC78H90 8-Channel, 500 kSPS, 12-Bit A/D Converter (jp)
8-Channel, 500 ksps, 12-Bit A/D Converter Literature Number: JAJSA63 8 500kSPS 12 A/D 8 12 CMOS A/D 500kSPS / AIN1 AIN8 8 SPI QSPI MICROWIRE DSP (AV DD ) 2.7V 5.25V (DV DD ) 2.7V AV DD 3V 1.5mW 5V 8.3mW
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HN58V256A HN58V257A 256k EEPROM (32-kword 8-bit) Ready/Busy and RES function (HN58V257A) RJJ03C0132-0600 Rev. 6.00 2007. 05. 24 HN58V256A HN58V257A 32768 8 EEPROM ROM MNOS CMOS 64 3V 2.7 5.5V 120ns (max)
AN5637
IC SECAM IC SECAM IC 1 SECAM Unit : mm 19.2±0.3 16 9 1 8 (0.71) 0.5±0.1 Seating plane 2.54 1.22±0.25 DIP016-P-0300D 6.2±0.3 5.20±0.25 1.10±0.25 3.05±0.25 7.62±0.25 3 to 15 0.30 +0.10 ) (DIP016- P-0300M)
NL-20取扱説明書_操作編
MIC / Preamp A C AMP 1 AMP 2 AMP 3 FLAT FLAT CAL.SIG. OVER LOAD DET. AMP 4 AMP 5 A/D D/A CONV. V ref. AMP 8 AMP 10 DC OUT AC OUT AC DC OUT DATA BUS CPU ADDRESS BUS DSP Start Pause Stop Store Mode Cont
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HN58C256A HN58C257A 256k EEPROM (32-kword 8-bit) Ready/Busy and RES function (HN58C257A) RJJ03C0133-0600Z Rev. 6.00 2006. 10. 26 HN58C256A HN58C257A 32768 8 EEPROM ROM MNOS CMOS 64 5V±10% 85ns/100ns (max)
EVI-D100/D100P
A-AYS-100-11(1) EVI-D100/D100P 2001 Sony Corporation ... 3... 4... 5... 7... 18 D30/D31... 40... 46... 48... 49 2 3 VIDEO S S S VIDEO VISCA 1 VISCA IN VISCA OUT RS-232C EVI-D100/P VISCA IN AC DC IN 12V
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SD/HD ADV739/ADV739/ADV7392/ADV7393 3 DAC SD 6 26MHz DAC ED 8 26MHz DAC HD 4 297MHz DAC 37mA DAC 4:2:2 YCrCb SD ED HD 4:4:4 RGB SD CVBS S Y/C YPrPb SD ED HD RGB SD ED HD LFCSP 325mm 5mm LFCSP 46mm 6mm
AN6591FJM
IC AN6591FJM PHS, PLL IC AN6591FJMPHSIF PLL IC QFN (Quad flat non-leaded PKG) (0.63) 34 44 R0.30 6.20±0.10 (6.00) 33 23 1 11 (0.63) 22 12 3-C 0.50 (6.00) 6.20±0.10 0.20±0.10 0.80 max Unit : mm, PLL,, APC
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お客様各位 カタログ等資料中の旧社名の扱いについて 2010 年 4 月 1 日を以って NEC エレクトロニクス株式会社及び株式会社ルネサステクノロジが合併し 両社の全ての事業が当社に承継されております 従いまして 本資料中には旧社名での表記が残っておりますが 当社の資料として有効ですので ご理解の程宜しくお願い申し上げます ルネサスエレクトロニクスホームページ (http://www.renesas.com)
R1LV1616H-I シリーズ
お客様各位 カタログ等資料中の旧社名の扱いについて 2010 年 4 月 1 日を以って NEC エレクトロニクス株式会社及び株式会社ルネサステクノロジが合併し 両社の全ての事業が当社に承継されております 従いまして 本資料中には旧社名での表記が残っておりますが 当社の資料として有効ですので ご理解の程宜しくお願い申し上げます ルネサスエレクトロニクスホームページ (http://www.renesas.com)
CP-X608J_表紙_裏表紙.indd
AUDIO IN 1 AUDIO IN 2 SD CARD RGB OUT Y VIDEO S-VIDEO AUX I/O DC 5V 0.5A R L R L AUDIO IN 3 AUDIO IN 4 AUDIO OUT LAN RGB1 RGB2 M1-D CB/PB CR/PR I REMOTE CONTROL (3.5Φ) CONTROL O AC IN K STANDBY/ON VIDEO
ADC082S021 2 Channel, 50 ksps to 200 ksps, 8-Bit A/D Converter (jp)
2 Channel, 50 ksps to 200 ksps, 8-Bit A/D Converter Literature Number: JAJSAA2 2 200KSPS 8 A/D 2 8 CMOS A/D 50kSPS 200kSPS / IN1 IN2 1 2 SPI QSPI MICROWIRE DSP 2.7V 5.25V 3V 1.6mW 5V 5.8mW 3V 0.12 W 5V
AN5308NK
IC AN5308NK IC(I 2 C ) AN5308NK I 2 C NTSC RGB IC : ABL : ACC RGB : RGB : BLK µ H : 58.4±0.3 64 33 1 32 (1.641) Seating plane 1.778 (1.0) 0.5 +0.1 0.05 17.0±0.2 SDIP064-P-0750B 3.85±0.2 (3.3) 0.7 min.
GM-F520S/GM-F470S/GM-F420S
GM-F520S GM-F470S GM-F420S LCT2504-002A-H 2 3 4 200 150 150 50 1 3 4 1 2 3 1 2 3 4 5 e 6 7 8 9 p q w r t 5 6 5 23 7 8 9 p q 4 5 6 7 8 9 2 3 4 5 5 23 6 7 8 9 w 1 2 e r t p p 5 6 9( 3 DVI-D (HDCP) RGB IN
PRECISION COMPACT DISC PLAYER DP-75V
PRECISION COMPACT DISC PLAYER DP-75V Accuphase warranty is valid only in Japan. 7 6 8 9 10 1 2 3 5 4 11 13 14 15 12 16 = CD/PROC PLAY PROGRAM REPEAT ALLONE A B LEVEL khz INDEX TRACK EXT M S db PROCESSOR
N12866N2P-H.PDF
16Mx64bits PC133 SDRAM SO DIMM Based on 16Mx16 SDRAM with LVTTL, 4 banks & 8K Refresh (16M x 16bit) /. / 1 A0 ~ A12 BA0, BA1 CK0, CK1 CKE0 /S0 /RAS /CAS /WE DQM0 ~ DQM7 DQ0 ~ DQ63 SA0~2 SDA SCL VCC 3.3
電源監視回路
TPS3820-xx,TPS3823-xx TPS3824-xx,TPS3825-xx TPS3828-xx www.tij.co.jp µ TYPICAL APPLICATION TPS3820, TPS3823, TPS3828: DBV PACKAGE (TOP VIEW) GND MR 1 2 3 5 4 VDD WDI TPS3824: DBV PACKAGE (TOP VIEW) 1 5
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Wide Temperature Range Version 4M SRAM (256-kword 16-bit) RJJ03C0237-0100 Rev. 1.00 2007.05.24 262,144 16 4M RAM TFT 44 TSOP II 48 CSP 0.75mm 3.0V 2.7V 3.6V 55/70ns max 3µW typ V CC =3.0V 2CS 40 +85 C
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µ CBUSY ANALOG INPUT 10V TO 10V 2. 2. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 V DIG V ANA PWRD BUSY CS R/C TAG SB/BTC DATA EXT/INT DATACLK DGND SY 28 27 26 25 24 23 22 21 20 19 18 17 16 15 10µF 0.1µF SERIAL INTERFACE
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AN2492FH
8mm (NTSC) NTSC 8mm Y/C 1 LSI f C 5V NTSC (PAL AN2493 ) 8mm, 8mm 0.10±0.10 49 64 (1.25) 12.00±0.20 10.00±0.20 48 33 1 0.50 16 0.18 +0.10 0.05 SEATING PLANE 32 (1.25) 10.00±0.20 12.00±0.20 17 0.15 +0.10
PDW-75MD
3-270-633-02(1) PDW-75MD 2007 Sony Corporation m a b c 2 ... 2 6 6... 8... 8 1... 10... 10... 12... 13... 13... 19... 23 2... 25... 26... 27... 27... 28... 29... 29... 29... 30... 31... 33 3... 34... 34...
ANJ_1092A
Application Note SBAA066 ± ± ± ± µ ± ± ± ± 24 Bits 20/24MSB 2 s f S 768 khz 25 MHz (1) V IH 2.0 5.0 V (1) V IL 0 0.8 V (2) V IH 3.0 0 V (2) V IL 5.0 4.2 V (1) I IH V IH = V DD ±10 µa (1) I IL V IL = 0V
HN58X2402SFPIAG/HN58X2404SFPIAG
お客様各位 カタログ等資料中の旧社名の扱いについて 2010 年 4 月 1 日を以って NEC エレクトロニクス株式会社及び株式会社ルネサステクノロジが合併し 両社の全ての事業が当社に承継されております 従いまして 本資料中には旧社名での表記が残っておりますが 当社の資料として有効ですので ご理解の程宜しくお願い申し上げます ルネサスエレクトロニクスホームページ (http://www.renesas.com)
Цифровой спутниковый ресивер Lumax DV 2400 IRD
13... 3 1.... 5 1.1 1.2... 5... 6 2.... 7 2.1 2.2 2.3... 7... 8... 9 3.... 10 3.1... 10 3.1.1 RF...10 3.1.2 SCART...11 3.2... 12 3.2.1 DISH IN...12 3.2.2 DiSEqC...13 4..... 14 4.1 0003.... 15 4.1.1...15
LT 低コスト、シャットダウン機能付き デュアルおよびトリプル300MHz 電流帰還アンプ
µ µ LT1398/LT1399 V IN A R G 00Ω CHANNEL A SELECT EN A R F 3Ω B C 97.6Ω CABLE V IN B R G 00Ω EN B R F 3Ω 97.6Ω V OUT OUTPUT (00mV/DIV) EN C V IN C 97.6Ω R G 00Ω R F 3Ω 1399 TA01 R F = R G = 30Ω f = 30MHz
MAX9471/2 DS.J
19-0524; Rev 0; 5/06 * * ± PART TEMP RANGE PIN- PACKAGE TOP VIEW X2 X1 FSO/SCL FS1/SDA 16 17 18 19 20 + PD FS2 15 14 1 TUNE 2 13 VDD 12 VDD 11 GND MAX9471 VDDA 3 AGND 4 GND 5 CLK1 TQFN (5mm x 5mm) 10 9
2
WV-CW960 2 3 4 5 6 7 8 9 10 11 SW1 S TA RT RS485Setting SW2 DIP SW1 ON 1 2 3 4 5 6 7 8 ON 1 2 3 4 DIP SW2 12 13 q w q e 14 15 16 17 18 19 ** RS485 SETUP ** UNIT NUMBER SUB ADDRESS BAUD RATE DATA BIT PARITY
AN15880A
DATA SHEET 品種名 パッケージコード QFH064-P-1414H 発行年月 : 2008 年 12 月 1 目次 概要.. 3 特長.. 3 用途.. 3 外形.. 3 構造...... 3 応用回路例.. 4 ブロック図.... 5 端子.. 6 絶対最大定格.. 8 動作電源電圧範囲.. 8 電気的特性. 9 電気的特性 ( 設計参考値 )... 10 技術資料.. 11 入出力部の回路図および端子機能の
TH-42/47/55LF6J,TH-42/47/55LF60J
- + - + 1 2 M3 HDMI HDMI AV OUT HDMI AV OUT DVD DVD 19 3 1 18 4 2 11 12 13 14 15 16 17 18 19 10 DVD VIDEO OUT VCR AUDIO OUT L R RCA-BNC RCA-BNC Y PB PR OUT RGB OUT L R AUDIO OUT RGB DVD DVI-D PC DVI 5
TOS7200 CD-ROM DUT PC 1.0X p.15 NEMA Vac/10 A [85-AA-0003] m : CEE7/7 : 250Vac/10 A [85-AA-0005] : GB1002 : 250Vac/10A [ ] 2016
![TOS7200 CD-ROM DUT PC 1.0X p.15 NEMA Vac/10 A [85-AA-0003] m : CEE7/7 : 250Vac/10 A [85-AA-0005] : GB1002 : 250Vac/10A [ ] 2016](/thumbs/93/112128441.jpg "TOS7200 CD-ROM DUT PC 1.0X p.15 NEMA Vac/10 A [85-AA-0003] m : CEE7/7 : 250Vac/10 A [85-AA-0005] : GB1002 : 250Vac/10A [ ] 2016")
No. IB028901 Nov. 2016 1. 11 TOS7200 2. 14 3. 19 4. 23 5. 39 6. 49 7. 51 TOS7200 CD-ROM DUT PC 1.0X p.15 NEMA5-15 125 Vac/10 A [85-AA-0003] 1 2.5 m : CEE7/7 : 250Vac/10 A [85-AA-0005] : GB1002 : 250Vac/10A
mbed祭りMar2016_プルアップ.key
1 2 4 5 Table 16. Static characteristics (LPC1100, LPC1100L series) continued T amb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ [1] Max Unit Standard port pins, RESET
2
WV-CS570 2 3 4 5 6 7 8 9 10 11 12 13 q w q e 14 1 2 15 3 4 5 16 6 7 8 9 17 1 2 3 18 19 1 2 * RS485 SET UP * UNIT NUMBER SUB ADDRESS BAUD RATE DATA BIT PARITY CHECK STOP BIT X/X WAIT TIME ALARM DATA DELAY
AN2493FH
8mm (PAL) PAL 8mm Y/ C 1 LSI f C 5V PAL (NTSC : AN2492 ) 8mm 8mm 0.10±0.10 49 64 (1.25) 12.00±0.20 10.00±0.20 48 33 1 0.50 16 0.18 +0.10 0.05 SEATING PLANE 32 (1.25) 10.00±0.20 12.00±0.20 17 0.15 +0.10
AN8934FA
BS +QPSK IC BS QPSK IC 4.5MHz L.P.F. 5.7MHz B.P.F. C/N 2 (75Ω ) 1 (75Ω ) PCM IC MN88831 1 (18.432MHz) BS 37 48 (14.25) 1 12.00±0.20 10.00±0.20 36 25 0.65 12 0.30 +0.10 0.05 Seating plane 24 13 (1.425)
2
WV-CW970 2 3 4 5 6 7 8 9 10 11 12 DIP SW1 ON 1 2 3 4 5 6 7 8 ON 1 2 3 4 DIP SW2 SW1 S TA RT RS485Setting SW2 13 14 q w q e 15 16 17 18 19 20 ** RS485 SETUP ** UNIT NUMBER SUB ADDRESS BAUD RATE DATA BIT
MEDIAEDGE MEDIAEDGE TEL FAX :00 12:00 13:00 17: MEDIAEDGE MEDIAEDGE 8. HDMI HDMIHigh-Definition M
VPM-H1 HDMI http://www.mediaedge.co.jp http://www.mediaedge.co.jp TEL:078-265-1551 FAX:078-265-1550 TEL:03-3517-1655 FAX:03-3517-1657 10 00 12 00 13 00 17 00 e-mail:info-mec@mediaedge.co.jp 651-0083 5-1-14
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1 CMOS 0.35um CMOS, 3V CMOS 2 RF CMOS RF CMOS RF CMOS RFCMOS (ADC Fabless 3 RF CMOS 1990 Abidi (UCLA): Fabless RF CMOS CMOS 90% 4 5 f T [GHz] 450 400 350 300 250 200 150 Technology loadmap L[nm] f T [GHz]
4
I/O 2AO DC0-10V/ 10V 16Bit Ver. 1.0.0 2 750-562 Copyright 2006 by WAGO Kontakttechnik GmbH All rights reserved. 136-0071 1-5-7 ND TEL 03-5627-2059 FAX 03-5627-2055 http://www.wago.co.jp/io/ WAGO Kontakttechnik
查询 AK4626 供应商 ASAHI KASEI [AK4626] AK4626 High Performance Multi-channel Audio CODEC AK4626 2ch ADC 6ch DAC 1 24bit CODEC ADC DAC ADC µp I/F AK4626 AD
![查询 AK4626 供应商 ASAHI KASEI [AK4626] AK4626 High Performance Multi-channel Audio CODEC AK4626 2ch ADC 6ch DAC 1 24bit CODEC ADC DAC ADC µp I/F AK4626 AD](/thumbs/96/129624108.jpg "查询 AK4626 供应商 ASAHI KASEI [AK4626] AK4626 High Performance Multi-channel Audio CODEC AK4626 2ch ADC 6ch DAC 1 24bit CODEC ADC DAC ADC µp I/F AK4626 AD")
查询 AK4626 供应商 AK4626 High Performance Multichannel Audio CODEC AK4626 2ch ADC 6ch DAC 1 24bit CODEC ADC DAC ADC µp I/F AK4626 ADC 102 DAC 106 AC3 IEC60958 (AK4112B) AC3 44 LQFP *AC3 Dolby Laboratories
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LV-X J PC ADJ..4.8 m 4 m 00 PC MUTE NO SHOWFREEZE P-TIMER DVD HDTV NTSC NTSC4.43 PAL SECAM PAL-M PAL-N B500 9 0 36XGA 3W UHP.4 9 00 D-sub 5 ( ) S USB INPUT POWER + VOL W KEY MUTE STONE D ZOOM T MENU SET
DS90LV V or 5V LVDS Driver/Receiver (jp)
DS90LV019 DS90LV019 3.3V or 5V LVDS Driver/Receiver Literature Number: JAJS563 DS90LV019 LVDS 1 / DS90LV019 Low Voltage Differential Signaling (LVDS) 1 CMOS / DS90LV019 EIA-644 IEEE1596.3 (SCI LVDS) 2
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COPAL ELECTRONICS 32 (DP) DP INC 2 3 3 RH RL RWB 32 C S U/D INC U/D CS 2 2 DP7114 32 SOIC CMOS 2.5 V - 6.0 V / 10 kω 50 kω 100 kω TSSOP MSOP /BFR INC / U/D RH RoHS GND RWB RL CS VCC 2017 6 15 1 : R = 2
3 2 q w e r t y
Panasonic System Networks Co., Ltd. 2010 WV-CL930,WV-CL934 WV-LZ80/2 TV LENS 6~12mm 1:1.4 WV-CL930,WV-CL934 3 2 q w e r t y 4 q w e r t y u i o!0!1!2!3!4!5 5 7 6 9 8 11 10 13 12 AC 24V IN DC 12V IN GEN-LOCK
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LeCroy Corporation 700 Chestnut Ridge Road Chestnut Ridge, NY, 10977 6499 Tel: (845) 578 6020, Fax: (845) 578 5985 Internet: www.lecroy.com 2010 by LeCroy Corporation. All rights reserved. LeCroy and other
l n l l l
MSM7653 l n n l l l l l l l l l l l l l l l l l n l l l n l l n l n l l n n W Ω Ω Ω ΩΩ Ω l n l m m Ω l W W W l n TS CLKX2 HSYNC_L, VSYNC_L, BLANK_L, YD, CD, MS, MODE, OLR, OLG, OLB, OLC ts1 Invalid data
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1M EEPROM (128-kword 8-bit) Ready/Busy and function R10DS0209JJ0100 Rev.1.00 131072 8 EEPROM ROM MONOS CMOS 128 2.7V 5.5V 150ns (max) @ Vcc=4.5V 5.5V 250ns(max) @ Vcc=2.7V 5.5V 20mW/MHz (typ) 110µW (max)
4
I/O 2AO 0/4-20mA / DC6-18V 16Bit Ver. 1.0.0 2 750-563 Copyright 2006 by WAGO Kontakttechnik GmbH All rights reserved. 136-0071 1-5-7 ND TEL 03-5627-2059 FAX 03-5627-2055 http://www.wago.co.jp/io/ WAGO
02_Matrox Frame Grabbers_1612
Matrox - - Frame Grabbers MatroxRadient ev-cxp Equalizer Equalizer Equalizer Equalizer 6.25 Gbps 20 Mbps Stream channel Control channel Stream channel Control channel Stream channel Control channel Stream
AK4161 Japanese Datasheet - Product Brief
AK4161 6channel Capacitive Touch Sensor IC 概要 AK4161 は 低電圧動作および低消費電力の 6 チャンネル静電容量式タッチセンサです センサ入力 6 チャンネルは GPIO LED 駆動にそれぞれ割り当てることが可能です さらにセンサ入力のうち 2ch は 割り込み出力として利用することが可能です また センス端子毎に独立した環境ドリフト自動補正機能を備えており
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CMOS 376-851511 0277 (30) 1788 0277 (30)1707 e-mail: k_haruo@el.gunma-u.ac.jp AD AD AD [] AD AD AD [] ISSCC 2007 TSMC ISSCC2007 ISSCC2007 /DAC (regulation) (AGC) ADC/DAC AD AD AD [] AD CMOS SAR ADC Gr),,
AD5302/AD5312/AD5322: 2.5 ～ 5.5 V 電源、230 μA 消費電流、デュアル、レール to レール電圧出力の 8 ／ 10 ／ 12 ビット D/A コンバータ
2.5 5.5V 23µA to8/1/12 D/A AD532 18DAC 2 A 1LSB INL B.5LSB INL AD5312 11DAC 2 A 4LSB INL B 2LSB INL AD5322 112DAC 2 A 16LSB INL B 8LSB INL 1MSOP 3µA@5V 2nA@5V 5nA@3V 2.5 5.5V V REF V LDAC DAC to 1MSOP
橡51553abj.PDF
Type No. 2002 10 3 ******** ACI 1.... 2 2.... 3 3.... 12 4. I/O... 14 5.... 17 6.... 18 7.... 22 8.... 22 9.... 22 10.... 23 11.... 24 CORPORATION Page 1/24 1. min. -20max. 70 min. -30max. 85 128 (W) 64
51553aej.PDF
2005 9 8 ******** ACI ACI Type No. 1.... 2 2.... 3 3.... 12 4. I/O... 14 5.... 17 6.... 18 7.... 22 8.... 22 9.... 22 10.... 23 11.... 24 F-51553GNBJ-LW-AEN (AE) No.2005-0146 OPTREX CORPORATION Page 1/24
1516-機器センサ_J.indb
機器用センサ Grid-EYE Grid-EYE Grid-EYE Grid-EYE Grid-EYE 着座検知 扉開閉 洗濯機の水位検知 電子レンジ PS-A 微圧タイプ 水位検知 Grid-EYE 温度計測 位置検知 熱 軸GF 赤外線アレイセンサ Grid-EYE 設計 仕様について予告なく変更する場合があります ご購入及びご使用前に当社の技術仕様書などをお求め願い それらに基づいて購入及び使用していただきますようお願いします
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: SOU1AP2011003 2011/12/25 & Copyright 2010, Toshiba Corporation. : SOU1AP2011003 1. 2.CMOS 3.CMOS 4.CMOS 5.CMOS 6. 2 : SOU1AP2011003 3 : SOU1AP2011003 NAND,OR,, IC 1A 1 1B 2 14 13 V CC 4B 1Y 2A 2B 3 4
AX-V8000[DOM]
![AX-V8000[DOM]](/thumbs/91/106835731.jpg "AX-V8000[DOM]")
5 3 7 8 SPEAKERS SPEAKERS 2 INPUT MODE INPUT ATT SURROUND ON/OFF HTX ON / OFF DSP MODE LINE DIRECT SOUND SELECTOR REC SELECTOR ADJUST MENU SETUP MENU AUDIO/VIDEO CONTROL AMPLIFIER DOWN LEFT UP RIGHT SET
高速度スイッチングダイオード
は簡単な構成で FM ステレオ送信を実現できる IC です ステレオコンポジット信号を作るステレオ変調器及び FM 信号を空中へ輻射するための FM トランスミッタで構成されています ステレオ変調器は 3kHz 発振器より MAIN SUB 及びパイロット信号からなるコンポジット信号を発生します FM トランスミッタは FM 帯のキャリアを発振させコンポジット信号によって FM 変調をかけ FM 波を空中に輻射します
VPH-G70QJ
3-858-611-03 (2) VP-G70QJ 1996 by Sony Corporation 2 / 1 2 3 5 7 8 9 10 22 28 75 30 32 33 37 42 43 49 64 3 67 77 100 109 111 113 114 115 116 117 122 4 5 6 7 8 1 v 2 v 3 v 4 v 5 v 6 v 7 v 8 v 9 v 0 9 695
AN7500FHQ
1.5V IC 1.5V B IC 0.98V 37 48 9.00±0.40 7.00±0.20 36 25 24 (0.75) 7.00±0.20 13 9.00±0.40 Unit : mm 35 1.5V DC/DC 40 1 (0.75) 0.50 12 0.20 0.05 +0.10 SEATING PLANE (0.625) 1.40±0.10 1.70 max. (0.625) 0.10±0.10
OPA134/2134/4134('98.03)
OPA OPA OPA OPA OPA OPA OPA OPA OPA TM µ Ω ± ± ± ± + OPA OPA OPA Offset Trim Offset Trim Out A V+ Out A Out D In +In V+ Output In A +In A A B Out B In B In A +In A A D In D +In D V NC V +In B V+ V +In
PIN S 5 K 0 K 1 K 2 K 3 K 4 V DD V 0 V 1 V 2 V SS OSC SEG 32 SEG 31 SEG 30 SEG 29 SEG 28 SEG 27 SEG 26 SEG 25 SEG 24 SEG 23 SEG 22 SEG 21 SEG 20 SEG 1
1/3 1/4 LCD NJU6535 LCD 1/3 1/4 LCD key(scan 6 Scan 5) CPU 3 4 42 41 1/3 126 1/4 164 LED NJU6535FH1 LCD 42 126 164 30 Scan 6 Scan 5 1/2, 1/3 LED 4 (,,, CS) (8 ) 4.5 ~ 5.5V 5.5V QFP64-H1 CMOS ( :P) -1-
ELCODIS.COM - ELECTRONIC COMPONENTS DISTRIBUTOR
IC : = 2 MHz Max 2 : : TSSOP-20 RJJ03D0873-0200 Rev.2.00 2008.07.01 VIN Vout + DC 5 V DC 5 V DC 5 V DC 5 V DC 5 V Vbias (DC 12 V) VCC OUT -A GND OUT -B CS RAMP R2A20121 RT SYNC SS FB (+) OUT -C DELAY -1
TM-m30 詳細取扱説明書
M00094106 Rev. G Seiko Epson Corporation 2015-2018. All rights reserved. 2 3 4 5 6 7 8 Bluetooth 9 ... 71 10 1 11 Bluetooth 12 1 13 1 2 6 5 4 3 7 14 1 1 2 3 4 5 15 16 ONF 1 N O O N O N N N O F N N F N
RM0002-J01 Real Time Clock Module RTC-4543SA/SB RTC-4543SA RTC-4543SB Q Q
RM0002-J01 Real Time Clock Module RTC-4543SA/SB RTC-4543SA RTC-4543SB Q41454351000200 Q41454361000200 本マニュアルのご使用につきましては 次の点にご留意願います 1) 本カタログの内容については 予告なく変更することがあります 量産設計の際は最新情報をご確認ください 2) 本カタログの一部 または全部を弊社に無断で転載
N Express5800/R320a-E4 N Express5800/R320a-M4 ユーザーズガイド
7 7 Phoenix BIOS 4.0 Release 6.0.XXXX : CPU=Pentium III Processor XXX MHz 0640K System RAM Passed 0127M Extended RAM Passed WARNING 0212: Keybord Controller Failed. : Press to resume, to setup
Express5800/R320a-E4, Express5800/R320b-M4ユーザーズガイド
7 7 Phoenix BIOS 4.0 Release 6.0.XXXX : CPU=Pentium III Processor XXX MHz 0640K System RAM Passed 0127M Extended RAM Passed WARNING 0212: Keybord Controller Failed. : Press to resume, to setup
MS-1J/MS-1WJ（形名：MS-1/MS-1W）取扱説明書 - 詳細- 技術情報編
720 x 400 37.9 85.0 VESA TEXT 640 x 480 31.5 59.9 VESA VGA (60Hz) 640 x 480 37.9 72.8 VESA VGA (72Hz) 640 x 480 37.5 75.0 VESA VGA (75Hz) 640 x 480 43.3 85.0 VESA VGA (85Hz) 800 x 600 35.2 56.3 VESA SVGA
DS04-21361-4
Cypress () FUJITSU SEMICONDUCTOR DATA SHEET DS4 236 4 ASSPDTS Bi-CMOS PLL (. GHz PLL) MB5F7SL MB5F7SL,, MHz 2 PLL (Phase Locked Loop) LSI Bi CMOS, 5 ma (VCC 2.7 V), VCC 2.4 V,.5 ma, 6 ma 2, MB5F7SL,, MHz
TM-m30 詳細取扱説明書
M00094101 Rev. B Seiko Epson Corporation 2015-2016. All rights reserved. 2 3 4 5 6 7 8 Bluetooth 9 Bluetooth 10 1 11 Bluetooth 12 1 13 1 2 6 5 4 3 7 14 1 1 2 3 4 5 15 16 ONF 1 N O O N O N N N O F N N F
CANON_IT_catalog_1612
Image processing products Hardware /Software MatroxRadient Pro CL 7 HDR-26 HDR-26 Data Clock CC [4] UART Data Clock CC [4] UART Camera Link Interface w/ PoCL Camera Link Interface w/ PoCL Image Reconstruction
DL1720/DL1740ディジタルオシロスコープユーザーズマニュアル
DL1720/DL1740 IM 701710-01 http://www.yokogawa.co.jp/measurement/ 0120-137046 tmi-cs@csv.yokogawa.co.jp FAX 0422-52-6624 Disk No. DL30 2nd Edition : July 2001 (YK) All Rights Reserved, Copyright 2001 Yokogawa
Express5800/R320a-E4/Express5800/R320b-M4ユーザーズガイド
7 7 障害箇所の切り分け 万一 障害が発生した場合は ESMPRO/ServerManagerを使って障害の発生箇所を確認し 障害がハー ドウェアによるものかソフトウェアによるものかを判断します 障害発生個所や内容の確認ができたら 故障した部品の交換やシステム復旧などの処置を行います 障害がハードウェア要因によるものかソフトウェア要因によるものかを判断するには E S M P R O / ServerManagerが便利です
TM-m30 詳細取扱説明書
M00094100 Rev. A Seiko Epson Corporation 2015. All rights reserved. 2 3 4 5 6 Bluetooth 7 Bluetooth 8 1 9 Bluetooth 10 1 11 1 2 6 5 4 3 7 12 1 13 14 ONF 1 N O O N O N N N O F N N F N N N N N N F F O O
EVI-D70/D70P
A-BS1-100-11(1) EVI-D70/D70P 2003 Sony Corporation ... 3... 4... 5... 7... 30 D30/D31... 53... 60... 62... 63 2 3 VIDEO S S S VIDEO VISCA 1 VISCA RS-232C IN RS-232C VISCA RS-232C EVI-D70 OUT VISCA IN VISCA
01/DSP-R995 (01-33)
REMOTE CONTROL NATURAL SOUND AV AMPLIFIER DSP-R995 NATURAL SOUND AV AMPLIFIER DSP-R995 CINEMA DSP DOLBY DIGITAL POWER INPUT SELECTOR VOLUME 16 2 12 28 8 STANDBY/ON EXT. DECODER 6 2 A/B/C/D/E 1 2 3 4 5