7. Cyclone III I/O CIII51003-1.0 2 Cyclone III I/O 1 I/O 1 I/O Cyclone III I/O FPGA I/O I/O On-Chip Termination OCT Quartus II I/O Cyclone III I/O Cyclone III LAB I/O IOE I/O I/O IOE I/O 5 Cyclone III I/O I/O I/O PCI LVDS Low-Voltage Differential Signaling / On-Chip Termination Altera Corporation - Preliminary 7 1 2007 3
Cyclone III I/O Cyclone III I/O Cyclone III IOE 1 I/O 5 7-1 Cyclone III IOE IOE 1 2 2 2 2 DDR Clock-to-Output OE Clock-to-Output IOE 7-1. Cyclone III IOE Logic Array OE Register OE D Q CLK_Out OE Register D Q Output Register Output A D Q Input Register D Q Output Register Output B D Q Input (1) CLK_In 7-1 : (1) 2 7 2 Altera Corporation - Preliminary Cyclone III Volume 1 2007 3
Cyclone III I/O IOE Cyclone III I/O LE I/O I/O 4 IOE I/O I/O 2 5 IOE I/O I/O 7-2 I/O 7-3 7-4 I/O Cyclone III Cyclone III Cyclone III MultiTrack Altera Corporation - Preliminary 7 3 2007 3 Cyclone III Volume 1
Cyclone III I/O 7-2. I/O R4 Interconnect R24 Interconnect C4 Interconnect I/O Block Local Interconnect 32 Data & Control Signals from Logic Array (1) LAB 32 Horizontal I/O Block io_dataina[3..0] io_datainb[3..0] (2) Direct Link Interconnect to Adjacent LAB LAB Local Interconnect Direct Link Interconnect from Adjacent LAB io_clk[5..0] Horizontal I/O Block Contains up to Four IOEs 7-2 : (1) I/O 4 IOE 32 (2) I/O 4 IOE io_datain 2 7 4 Altera Corporation - Preliminary Cyclone III Volume 1 2007 3
Cyclone III I/O 7-3. EP3C5 EP3C10 EP3C25 EP3C55 EP3C80 EP3C120 I/O 32 Data & Control Signals from Logic Array (1) Column I/O Block Column I/O Block Contains up to Four IOEs 32 IO_dataina[3:0] IO_datainb[3:0](2) io_clk[5..0] I/O Block Local Interconnect R4 & R24 Interconnects LAB LAB LAB LAB Local Interconnect C16 Interconnect C4 Interconnect LAB Local Interconnect C4 Interconnect C16 Interconnect LAB Local Interconnect 7-3 : (1) 2 I/O 4 IOE 32 (2) I/O 4 IOE io_datain 2 Altera Corporation - Preliminary 7 5 2007 3 Cyclone III Volume 1
Cyclone III I/O 7-4. I/O EP3C16 EP3C40 I/O 40 Data & Control Signals from Logic Array (1) Column I/O Block IO_dataina[4:0] IO_datainb[4:0](2) Column I/O Block Contains up to Four IOEs io_clk[5..0] I/O Block Local Interconnect R4 & R24 Interconnects LAB LAB LAB LAB Local Interconnect C16 Interconnect 7-4 : (1) 2 I/O 5 IOE 40 (2) I/O 5 IOE io_datain 2 7 6 Altera Corporation - Preliminary Cyclone III Volume 1 2007 3
Cyclone III I/O datain IOE io_clk[5..0] I/O IOE IOE oe ce_in ce_out aclr/preset sclr/preset clk_in clk_out. 7-5 7-5. IOE Dedicated I/O Clock [5..0] Local Interconnect io_coe Local Interconnect io_csclr Local Interconnect io_caclr Local Interconnect io_cce_out Local Interconnect io_cee_in Local Interconnect io_cclk clk_in clk_out ce_in ce_out aclr/preset sclr/preset oe OE Clock-to-Output OE Clock-to-output OE LAB I/O Altera Corporation - Preliminary 7 7 2007 3 Cyclone III Volume 1
Cyclone III I/O sclr aclr sclr aclr 7-6 I/O IOE 7-6. I/O Cyclone III IOE Column or Row Interconnect io_clk[5..0] OE OE Register V CCIO clkout oe_out D Q ENA ACLR /PRN Optional PCI Clamp V CCIO aclr/prn Programmable Pull-Up Resistor Chip-Wide Reset Output Register Output Pin Delay data_in1 sclr/ preset D ENA ACLR /PRN Q Current Strength Control Open-Drain Out Slew Rate Control data_in0 clkin oe_in Input Register D Q ENA ACLR /PRN Input Pin to Input Register Delay or Input Pin to Logic Array Delay Bus Hold 7 8 Altera Corporation - Preliminary Cyclone III Volume 1 2007 3
I/O I/O Cyclone III I/O I/O LVTTL LVCMOS SSTL-2 Class I II SSTL- 18 Class I II HSTL-18 Class I II HSTL-15 Class I II HSTL-12 Class I II Quartus II Volume 2Assignment Editor 7 1 I/O SSO I/O I OH I OL On-Chip Termination 7 1. (1) / I/O I OH / I OL (ma) I/O I/O 1.2 V LVCMOS 2 2 4 4 6 6 8 8 10 10 12 1.5 V LVCMOS 2 2 4 4 6 6 8 8 10 10 12 12 16 16 Altera Corporation - Preliminary 7 9 2007 3 Cyclone III Volume 1
Cyclone III I/O 7 1. (1) / I/O I OH / I OL (ma) I/O I/O 1.8 V LVTTL/LVCMOS 2 2 4 4 6 6 8 8 10 10 12 12 16 16 2.5 V LVTTL/LVCMOS 4 4 8 8 12 12 16 16 3.0 V LVCMOS 4 4 8 8 12 12 16 16 3.0 V LVTTL 4 4 8 8 12 12 16 16 3.3 V LVCMOS (2) 2 2 4 4 3.3 V LVTTL (2) 8 8 HSTL-12 Class I 8 8 10 10 12 HSTL-12 Class II 14 HSTL-15 Class I 8 8 10 10 12 12 HSTL-15 Class II 16 16 7 10 Altera Corporation - Preliminary Cyclone III Volume 1 2007 3
I/O 7 1. (1) / I/O I OH / I OL (ma) I/O I/O HSTL-18 Class I 8 8 10 10 12 12 HSTL-18 Class II 16 16 SSTL-18 Class I 8 8 10 10 12 12 SSTL-18 Class II 12 12 16 16 SSTL-2 Class I 8 8 12 12 SSTL-2 Class II 16 16 7 1 : (1) Quartus II I/O Standard HSTL/SSTL Class I OCT HSTL/SSTL Class II OCT 25 Ω (2) Quartus II 3.3 V LVTTL 3.3 V LVCMOS I/O Cyclone III 3.3 V 3.0 V I/O 3.3 V AN 447: Cyclone III 3.3V/3.0V/2.5V LVTTL/LVCMOS I/O Cyclone III I/O I/O 3 Altera Corporation - Preliminary 7 11 2007 3 Cyclone III Volume 1
Cyclone III I/O I/O 8mA I/O 3.3 V LVTTL 3.3 V LVCMOS I/O Quartus II Volume 2Assignment Editor Cyclone III I/O Quartus II Volume 2Assignment Editor Cyclone III I/O I/O I/O V CCIO I/O 7 12 Altera Corporation - Preliminary Cyclone III Volume 1 2007 3
I/O Quartus II Volume 2Assignment Editor V CCIO Cyclone III Volume 2 DC & Cyclone III I/O 1 I/O V CCIO JTAG Joint Test Action Group Quartus II Volume 2Assignment Editor Cyclone III IOE clock-to-output 0ns Quartus II 0ns Altera Corporation - Preliminary 7 13 2007 3 Cyclone III Volume 1
Cyclone III I/O 7 2 Cyclone III 7 2. Cyclone III Quartus II IOE 2 2 2 LE 2 Quartus II Input delay from pin to internal cells Quartus II Input delay from pin to input register I/O IOE IOE High Low Low High Low IOE 1 IOE IOE Quartus II Volume 2 7 14 Altera Corporation - Preliminary Cyclone III Volume 1 2007 3
On-Chip Termination PCI Cyclone III I/O PCI PCI 3.3 V LVTTL 3.3 V LVCMOS 3.0 V LVTTL 3.0 V LVCMOS PCI PCI-X I/O I/O 3.3 V LVTTL 3.3 V LVCMOS 3.0 V LVTTL 3.3 V LVCMOS PCI PCI-X PCI Quartus II PCI Quartus II Volume 2Assignment Editor Cyclone III PCI AN 447: Cyclone III 3.3 V/3.0 V/2.5 V LVTTL/LVCMOS I/O LVDS Cyclone III LVDS Cyclone III Cyclone III Cyclone III On-Chip Termination Cyclone III I/O On-Chip Termination OCTOn-Chip Termination BGA Cyclone III I/O On-Chip Termination Altera Corporation - Preliminary 7 15 2007 3 Cyclone III Volume 1
Cyclone III I/O On-Chip Termination Cyclone III On-Chip Termination 2 OCT OCT On-Chip Termination Cyclone III On-Chip Termination On-Chip Termination I/O R UP R DN 25 Ω ±1% ±1% I/O 7-7 7-7 RS I/O 7-7. Cyclone III On-Chip Termination Cyclone III Driver Series Impedance Receiving Device V CCIO R S Z O R S GND On-Chip Termination OCT 2 4 5 7 OCT 1 I/O I/O 2 OCT V CCIO 2 V CCIO 7 16 Altera Corporation - Preliminary Cyclone III Volume 1 2007 3
On-Chip Termination OCT 7-8 OCT 7-8. Cyclone III OCT I/O Bank 8 I/O Bank 7 I/O Bank 1 I/O Bank 6 I/O bank with calibration block CYCLONE III I/O bank without calibration block I/O Bank 2 I/O Bank 5 Calibration block coverage I/O Bank 3 I/O Bank 4 R UP R DN OCT 2 25 Ω ±1% ±1% OCT OCT R UP R DN I/O On-Chip Termination Cyclone III 25 Ω On- Chip Termination 25 Ω Cyclone III SSTL-2 SSTL-18 I/O R S =50Ω Altera Corporation - Preliminary 7 17 2007 3 Cyclone III Volume 1
Cyclone III I/O 7-9 On-Chip Termination I/O R S 7-9. Cyclone III On-Chip Termination Cyclone III Driver Series Impedance Receiving Device V CCIO R S Z O R S GND I/O I/O JTAG 7 3 I/O 7 3. On-Chip Termination I/O / I/O On-Chip Termination I/O I/O 3.0 V LVTTL 50 25 25 Ω 3.0 V LVCMOS 50 25 25 Ω 2.5 V LVTTL/LVCMOS 50 25 25 Ω 1.8 V LVTTL/LVCMOS 50 25 25 Ω 7 18 Altera Corporation - Preliminary Cyclone III Volume 1 2007 3
On-Chip Termination 7 3. On-Chip Termination I/O / 1.5 V LVCMOS 50 25 25 Ω 1.2 V LVCMOS 50 25 Ω SSTL-2 Class I 50 SSTL-2 Class II 25 25 Ω SSTL-18 Class I 50 SSTL-18 Class II 25 25 Ω HSTL-18 Class I 50 HSTL-18 Class II 25 25 Ω HSTL-15 Class I 50 HSTL-15 Class II 25 25 Ω HSTL-12 Class I 50 HSTL-12 Class II 25 Ω On-Chip Termination I/O I/O On-Chip Termination V CCIO V REF I/O R S I/O V CCIO V REF I/O Cyclone III Volume 2DC Altera Corporation - Preliminary 7 19 2007 3 Cyclone III Volume 1
Cyclone III I/O I/O Cyclone III I/O I/O Cyclone III 3.3 3.0 2.5 1.8 1.5 V I/O 1.2 V I/O 7 4 Cyclone III I/O I/O I/O 7 4. Cyclone III I/O / I/O 3.3 V LVTTL (1) 3.3 V LVCMOS (1) 3.0 V LVTTL (1) 3.0 V LVCMOS (1) 2.5 V LVTTL/LVCMOS 1.8 V LVTTL/LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS SSTL-2 Class I SSTL-2 Class II SSTL-18 Class I SSTL-18 Class II HSTL-18 class I JESD8-B 3.3 V/ 3.0 V/ 2.5 V JESD8-B 3.3 V/ 3.0 V/ 2.5 V JESD8-B 3.3 V/ 3.0 V/ 2.5 V JESD8-B 3.3 V/ 3.0 V/ 2.5 V JESD8-5 3.3 V/ 3.0 V/ 2.5 V JESD8-7 1.8 V/ 1.5 V JESD8-11 1.8 V/ 1.5 V V CCIO Level I/O CLK PLL_ DQS OUT I/O I/O CLK I/O DQS 3.3 V 3.3 V 3.0 V 3.0 V 2.5 V 1.8 V 1.5 V JESD8-12A 1.2 V 1.2 V JESD8-9A 2.5 V 2.5 V JESD8-9A 2.5 V 2.5 V JESD815 1.8 V 1.8 V JESD815 1.8 V 1.8 V JESD8-6 1.8 V 1.8 V 7 20 Altera Corporation - Preliminary Cyclone III Volume 1 2007 3
I/O 7 4. Cyclone III I/O / I/O HSTL-18 class II HSTL-15 Class I HSTL-15 Class II HSTL-12 Class I HSTL-12 Class II PCI PCI-X SSTL-2 Class I Class II V CCIO Level I/O CLK PLL_ DQS OUT I/O JESD8-6 1.8 V 1.8 V JESD8-6 1.5 V 1.5 V JESD8-6 1.5 V 1.5 V JESD8-16a 1.2 V 1.2 V JESD8-16a 1.2 V 1.2 V 3.0 V 3.0 V (2) JESD8-9A 2.5 V 2.5 V I/O CLK DQS I/O SSTL-18 (2) JESD815 1.8 V Class I Class II 1.8 V HSTL-18 (2) JESD8-6 1.8 V Class I Class II 1.8 V HSTL-15 (2) JESD8-6 1.5 V Class I Class II 1.5 V HSTL-12 (2) JESD8-16A 1.2 V Class I Class II 1.2 V PPDS (3) 2.5 V LVDS 2.5 V 2.5 V RSDS mini-lvds (3) 2.5 V Altera Corporation - Preliminary 7 21 2007 3 Cyclone III Volume 1
Cyclone III I/O 7 4. Cyclone III I/O / I/O V CCIO Level I/O CLK PLL_ DQS OUT I/O LVPECL (4) 2.5 V I/O CLK DQS I/O 7 4 : (1) PCI 3.3 V 3.0 V LVTTL/LVCMOS (2) HSTL SSTL 2 2 HSTL SSTL 2 HSTL SSTL HSTL SSTL CLK (3) PPDS mini-lvds RSDS (4) LVPECL I/O I/O I/O I/O JEDEC 3.3 V LVTTL 3.0 V LVTTL LVCMOS 2.5 V LVTTL LVCMOS 1.8 V LVTTL LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 3.0 V PCI PCI-X 7 22 Altera Corporation - Preliminary Cyclone III Volume 1 2007 3
I/O I/O I/O V REF V TT 7-10 7-11 7-10.Cyclone III HSTL I/O Termination HSTL Class I HSTL Class II External On-Board Termination VTT VREF VTT VTT V REF Transmitter Receiver Transmitter Receiver OCT With and Without Calibration Cyclone III Series OCT VTT V REF Cyclone III Series OCT 25 Ω VTT VTT V REF Transmitter Receiver Transmitter Receiver Altera Corporation - Preliminary 7 23 2007 3 Cyclone III Volume 1
Cyclone III I/O 7-11.Cyclone III SSTL I/O Termination SSTL Class I SSTL Class II VTT VTT VTT External On-Board Termination 25 Ω V REF 25 Ω VREF Transmitter Receiver Transmitter Receiver OCT With and Without Calibration Cyclone III Series OCT VTT V REF Cyclone III Series OCT 25 Ω VTT VTT V REF Transmitter Receiver Transmitter Receiver I/O I/O 2 7-12 7-13 Cyclone III SSTL-2 SSTL-18 HSTL-18 HSTL-15 HSTL-12 PPDS LVDS RSDS mini-lvds LVPECL 7 24 Altera Corporation - Preliminary Cyclone III Volume 1 2007 3
I/O 7-12.Cyclone III HSTL I/O Termination Differential HSTL Class I Differential HSTL Class II VTT VTT VTT VTT VTT VTT External On-Board Termination Transmitter Receiver Transmitter Receiver Cyclone III Series OCT VTT VTT Cyclone III Series OCT 25 Ω VTT VTT VTT VTT OCT Transmitter Receiver Transmitter Receiver Altera Corporation - Preliminary 7 25 2007 3 Cyclone III Volume 1
Cyclone III I/O 7-13.Cyclone III SSTL I/O Termination Differential SSTL Class I Differential SSTL Class II VTT VTT VTT VTT VTT VTT External On-Board Termination 25 Ω 25 Ω 25 Ω 25 Ω Transmitter Receiver Transmitter Receiver VTT VTT VTT VTT VTT VTT Cyclone III Series OCT Cyclone III Series OCT 25 Ω OCT Transmitter Receiver Transmitter Receiver Cyclone III PPDS LVDS mini-lvds RSDS I/O Cyclone III Cyclone III I/O Cyclone III I/O I/O 7-14 Cyclone III 8 I/O I/O 1 I/O I/O I/O I/O HSTL-12II 7 26 Altera Corporation - Preliminary Cyclone III Volume 1 2007 3
I/O 7-14.Cyclone III I/O (1) I/O Bank 8 I/O Bank 7 All I/O Banks Support: I/O Bank 2 I/O Bank 1 3.3-V LVTTL/LVCMOS 3.0-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS 1.2-V LVCMOS PPDS LVDS RSDS mini-lvds LVPECL (3) SSTL-2 class I and II SSTL-18 CLass I and II HSTL-18 Class I and II HSTL-15 Class I and II HSTL-12 Class I and II (4) Differential SSTL-2 (5) Differential SSTL-18 (5) Differential HSTL-18 (5) Differential HSTL-15 (5) Differential HSTL-12 (6) I/O Bank 5 I/O Bank 6 I/O Bank 3 I/O Bank 4 7-14 : (1) Quartus II (2) PPDS LVDS mini-lvds RSDS I/O I/O 1 2 5 6 I/O (3) LVPECL I/O I/O (4) HSTL-12 Class II I/O 3 4 7 8 (5) SSTL-18 SSTL-2 HSTL-18 HSTL-15 I/O PLL (6) HSTL-12 I/O PLL HSTL-12 Class II I/O 3 4 7 8 Altera Corporation - Preliminary 7 27 2007 3 Cyclone III Volume 1
Cyclone III I/O 7 5 Cyclone III I/O I/O I/O 7 5. Cyclone III I/O / I/O I/O 1 2 3 4 5 6 7 8 3.3 V LVCMOS 3.3 V LVTTL 3.0 V LVTTL 3.0 V LVCMOS 2.5 V LVTTL/LVCMOS 1.8 V LVTTL/LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 3.0 V PCI / PCI-X SSTL-18 Class I SSTL-18 Class II SSTL-2 Class I SSTL-2 Class II SSTL-18 Class I SSTL-18 Class II HSTL-18 Class I HSTL-18 Class II HSTL-15 Class I HSTL-15 Class II HSTL-12 Class I HSTL-12 Class II SSTL-2 (1) (1) (1) (1) (1) (1) (1) (1) SSTL-18 (1) (1) (1) (1) (1) (1) (1) (1) HSTL-18 (1) (1) (1) (1) (1) (1) (1) (1) HSTL-15 (1) (1) (1) (1) (1) (1) (1) (1) HSTL-12 (1) (1) (1) (1) (1) (1) (1) (1) PPDS (3) (3) (3) (3) (3) (3) (3) (3) (3) LVDS (2) RSDS mini-lvds (3) (3) (3) (3) (3) (3) (3) (3) 7 28 Altera Corporation - Preliminary Cyclone III Volume 1 2007 3
I/O 7 5. Cyclone III I/O / I/O I/O 1 2 3 4 5 6 7 8 LVPECL (4) (4) (4) (4) (4) (4) (4) (4) 7 5 : (1) I/O PLL_OUT (2) LVDS I/O I/O I/O LVDS I/O (3) I/O (4) I/O Cyclone III I/O I/O V REF V REF V REF V REF I/O I/O I/O 7 6 I/O V REF 7 6. I/O V REF / I/O 1 2 3 4 5 6 7 8 EP3C5 EQFP 144 1 1 1 1 1 1 1 1 FBGA 256 1 1 1 1 1 1 1 1 EP3C10 EQFP 144 1 1 1 1 1 1 1 1 FBGA 256 1 1 1 1 1 1 1 1 EP3C16 EQFP 144 2 2 2 2 2 2 2 2 PQFP 240 2 2 2 2 2 2 2 2 FBGA 256 2 2 2 2 2 2 2 2 FBGA 484 2 2 2 2 2 2 2 2 EP3C25 EQFP 144 1 1 1 1 1 1 1 1 PQFP 240 1 1 1 1 1 1 1 1 FBGA 256 1 1 1 1 1 1 1 1 FBGA 324 1 1 1 1 1 1 1 1 Altera Corporation - Preliminary 7 29 2007 3 Cyclone III Volume 1
Cyclone III I/O 7 6. I/O V REF / I/O 1 2 3 4 5 6 7 8 EP3C40 PQFP 240 4 4 4 4 4 4 4 4 FBGA 324 4 4 4 4 4 4 4 4 FBGA 484 4 4 4 4 4 4 4 4 FBGA 780 4 4 4 4 4 4 4 4 EP3C55 FBGA 484 2 2 2 2 2 2 2 2 FBGA 780 2 2 2 2 2 2 2 2 EP3C80 FBGA 484 3 3 3 3 3 3 3 3 FBGA 780 3 3 3 3 3 3 3 3 EP3C120 FBGA 484 3 3 3 3 3 3 3 3 FBGA 780 3 3 3 3 3 3 3 3 Cyclone III I/O V CCIO 1 I/O 1.2 1.5 1.8 2.5 3.0 3.3 V 1 V CCIO I/O V CCIO 1 Cyclone III 1 I/O V CCIO 2.5 V V CCIO I/O 2.5 V LVTTL 2.5 V LVDS 3.0 V LVTTL 3.3 V LVCMOS I/O V REF V CCIO Cyclone III SSTL-2 SSTL-18 I/O V REF V CCIO 2.5 V V REF 1.25 V I/O SSTL-2 2.5 V LVCMOS 7 30 Altera Corporation - Preliminary Cyclone III Volume 1 2007 3
I/O 7 7 7 7. (1) (2) (3) V CCIO (V) 1.2 V 1.5 V 1.8 V 2.5 V 3.0 V 3.3 V 1.2 V 1.5 V 1.8 V 2.5 V 3.0 V 3.3 V 1.2 V 1.5 V (1) 1.8 V (2) 2.5 V (3) (3) 3.0 V (2) (3) (3) 3.3 V (2) (3) (3) 7 7 : (1) (2) I/O (3) PCI 3.0 V 3.3 V Cyclone III I/O AN 447: Cyclone III 3.3 V/3.0 V/2.5 V LVTTL/LVCMOS I/O Cyclone III LVDS LVDS Cyclone III RSDS Reduced Swing Differential Signaling mini-lvds LVDS RSDS mini-lvds I/O LVDS EMI PPDS National Semiconductor Corporation RSDS Cyclone III National Semiconductor Corporation PPDS PPDS Cyclone III I/OPPDS Altera Corporation - Preliminary 7 31 2007 3 Cyclone III Volume 1
Cyclone III I/O I/O Cyclone III LVDS I/O Cyclone III / PLL IOE / / LVDS 2 100 Ω I/O Cyclone III Cyclone III Volume 1Cyclone III Cyclone III DDR SDRAM DDR2 SDRAM QDRII SRAM I/O Cyclone III Cyclone III Volume 1Cyclone III DC Cyclone III I/O I/O DC Quartus II Quartus II Quartus II I/O Quartus II I/O Management V CCIO I/O Cyclone III 7 32 Altera Corporation - Preliminary Cyclone III Volume 1 2007 3
DC LVDS I/O : LVDS I/O 4 LVDS I/O 5 I/O V CCIO 4 160 MHz LVDS I/O V CCIO 3 320 MHz LVDS I/O V CCIO 4 210 MHz LVDS I/O V CCIO 3 420 MHz LVDS Quartus II 2 RSDS mini-lvds I/O : RSDS mini-lvds 4 RSDS mini-lvds 5 I/O V CCIO 3 85 MHz RSDS mini-lvds I/O V CCIO 3 180 MHz RSDS I/O V CCIO 3 220 MHz mini-lvds Quartus II 2 PPDS I/O : PPDS 4 PPDS 5 I/O V CCIO 3 85 MHz PPDS I/O V CCIO 3 220 MHz PPDS Altera Corporation - Preliminary 7 33 2007 3 Cyclone III Volume 1
Cyclone III I/O Quartus II 2 LVPECL I/O : LVPECL 4 LVPECL 5 V REF V CCIO V REF V REF V CCIO I/O Cyclone III Quartus II V REF FineLine BGA 32 V REF QFP 21 V CCIO Cyclone III V CCIO FineLine BGA 9 QFP 5 SSTL HSTL V REF 2 DQ DQS DDR/DDR2/QDRII SSTL HSTL V REF 2 DQ DQS 7 37 DDR/DDR2 QDRII 7 34 Altera Corporation - Preliminary Cyclone III Volume 1 2007 3
DC DQ DQS 7 37 DDR/DDR2 QDRII OE OE FineLine BGA V REF 32 QFP V REF 21 OE 1 7 8 7 8. FineLine BGA OE 9 V CCIO QFP OE 5 V CCIO V REF 1 + 32 FineLine BGA + 21 QFP Altera Corporation - Preliminary 7 35 2007 3 Cyclone III Volume 1
Cyclone III I/O 7 9 7 9. V REF FineLine BGA QFP 9 V CCIO 5 V CCIO 1 7 10 7 10. V REF FineLine BGA + OE 9 V CCIO QFP + OE 5 V CCIO V REF + 32 FineLine BGA + 21 QFP 7 36 Altera Corporation - Preliminary Cyclone III Volume 1 2007 3
DC 7 11 7 11. V REF FineLine BGA + 9 V CCIO GND QFP + 5 V CCIO GND I/O 1 V CCIO 1 V REF I/O V CCIO V REF 7 6 DDR/DDR2 QDRII DDR DQ DQS DQ DQS DDR DDR2 V CCIO 5 DQ DQ DDR/DDR2 I/O QDRII D QDRII Q QDRII D Q CQ QDR QDRII V CCIO 5 D Q D Q I/O D cms address Q V REF Quartus II D Q I/O Quartus II D Q I/O Cyclone III QDR QDRII Altera Corporation - Preliminary 7 37 2007 3 Cyclone III Volume 1
Cyclone III I/O DC 1 12 240 ma +11 Σ I PIN < 240 ma 1 14 240 ma +13 Σ I PIN < 240 ma Quartus II I PIN Quartus II Cyclone III FPGA The Power Play III Early Power Estimator User Guide for Cyclone III FPGA Cyclone III I/O FPGA Cyclone III I/O Quartus II Cyclone III I/O I/O Cyclone III I/O 7 38 Altera Corporation - Preliminary Cyclone III Volume 1 2007 3
7 12 7 12. 2007 3 v1.0 Altera Corporation - Preliminary 7 39 2007 3 Cyclone III Volume 1
Cyclone III I/O 7 40 Altera Corporation - Preliminary Cyclone III Volume 1 2007 3