XAPP858 (v1.1) 2007 1 9 : Virtex-5 FPGA Virtex-5 DDR2 SDRAM : Karthi Palanisamy Maria George (v1.1) DDR2 SDRAM Virtex -5 I/O ISERDES (Input Serializer/Deserializer) ODDR (Output Double Data Rate) DDR2 SDRAM Virtex-5 FPGA ISERDES FPGA ISERDES OCLK CLKDIV FPGA ISERDES Q3 Q4 BUFIO CC (Clock-Capable) I/O BUFIO DQS ISERDES FPGA ODDR DDR2 SDRAM DDR2 DDR2 SDRAM DDR2 SDRAM DDR SDRAM DDR2 SDRAM SSTL 1.8V I/O DDR2 SDRAM DDR SDRAM DDR2 SDRAM DDR2 SDRAM DDR (DQS) DQS DDR2 SDRAM DQS DDR2 SDRAM DDR2 3 FIFO FIFO 2006-2007 Xilinx, Inc. All Rights Reserved. XILINX Xilinx Xilinx Xilinx Xilinx Inc. : Xilinx Xilinx Xilinx XAPP858 (v1.1) 2007 1 9 japan.xilinx.com 1
DDR2 SDRAM DDR2 SDRAM 1 (RAS) (CAS) (WE) (CKE) High (CS) Low DDR2 1 : DDR2 RAS CAS WE 1 L L L 2 L L H 3 (1) L H L 4 L H H 5 H L L 6 H L H 7 /IDLE H H H : 1. A10 High 1 Low DDR2 SDRAM CAS 1 BA1 BA0 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 0 PD WR DLL TM CAS# Latency BT Burst Length A2 A1 A0 Burst Length 0 1 0 4 0 1 1 8 Others Reserved A11 A10 A9 Write Recovery 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 Others Reserved A6 A5 A4 CAS Latency 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 Others Reserved X858_01_042006 1 : 2 japan.xilinx.com XAPP858 (v1.1) 2007 1 9
DDR2 SDRAM R 2 2 : BA1 BA0 0 0 (MR) 0 1 EMR1 1 0 EMR2 1 1 EMR3 DLL / ODT () CAS AL ( ) OCD ( ) DQS /RDQS/RDQS / OUTPUT / ( 3) OCD 3 : BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 1 Out RDQS DQS OCD Program R TT Posted CAS R TT ODS DLL 2 (EMR2) 10 (BA1 High BA0 Low) Low 3 (EMR3) 11 (BA1 BA0 High) EMR2 Low DDR2 SDRAM 1. Deselect 200µs 2. CKE 3. 400ns 4. EMR (2) BA0 Low BA1 High 5. EMR (3) BA0 BA1 High 6. EMR DLL BA1 A0 Low BA0 High 7. DLL DLL 200 8. 9. 2 10. A8 Low XAPP858 (v1.1) 2007 1 9 japan.xilinx.com 3
DDR2 SDRAM 11. EMR E7 E8 E9 1 OCD 12. EMR E7 E8 E9 0 OCD DDR2 SDRAM Virtex-5 dp_dly_slct_done IDLE (t RP ) A10 1 DDR2 7.8µs 16 1 auto_ref auto_ref 7.8µs High DDR2 SDRAM t RCD DDR2 SDRAM CAS t RCD BA0 BA1 A 0 A i 2 0 3 CAS 4 japan.xilinx.com XAPP858 (v1.1) 2007 1 9
DDR2 SDRAM R CK CK T 0 T 1 T 2 T 3 T 3n T 4 T 4n T 5 Command READ Address DQS DQS Bank a, Col n RL = 3 (AL = 0, CL = 3) DQ DO n X858_02_042606 2 : BA0 BA1 A 0 A i DDR2 SDRAM (RL) 1 (WL) = 1=( +CAS ) 1 3 WL 2 DQS WL CK CK T 0 T 1 T 2 T 2n T 3 T 3n T 4 T 5 Command Write Address Bank a, Col b t DQSS (NOM) DQS DQS t DQSS DQ DI b DM X858_03_042006 3 : XAPP858 (v1.1) 2007 1 9 japan.xilinx.com 5
DDR2 SDRAM 4 DDR2 FIFO FIFO Write & Read Datapaths Synthesizable Test Bench DQS/DQ & Read Enable Calibration State Machines Memory Initialization State Machine & Command MUX Physical Layer Memory Interface TOP_TB CK/CK_N Address/Controls Command/Controls DQ DQS DDR2 SDRAM Read/Write Data & Addr FIFOs User Interface Memory Interface Top Controller (Main Command State Machine) Virtex-5 FPGA X858_04_042606 4 : DDR2 (DDR2 ) ROM RAM DDR2 SDRAM FIFO FIFO FIFO FIFO 3 FIFO 2 FIFO FIFO 6 japan.xilinx.com XAPP858 (v1.1) 2007 1 9
R 4 4 : () usr_ip_add_fifo_addr 36 FIFO : Memory Address 31:0], (CS, Bank, Row, Column)[ Reserved [33:32] Command Request [35:34] usr_ip_add_fifo_empty 1 FIFO EMPTY FIFO ctrl_af_rden 1 FIFO ctrl_wdf_rden 1 FIFO FIFO FULL FIFO16 EMPTY 1 2 8 4 FIFO 64 4 2 128 XAPP858 (v1.1) 2007 1 9 japan.xilinx.com 7
5 : Af_addr (Af_addr) ( 5) col_ap_width - 1:0 col_ap_width + row_address 1:col_ap_width col_ap_width + row_address + bank_address 1:col_ap_width + row_address col_ap_width + row_address + bank_address + chip_address 1:col_ap_width + row_address + bank_address 6 6 : 00 01 10 11 5 4 4 4 7 5 CLK State 09 0A 09 0A 09 0A 09 0A 0B 07 08 07 08 07 08 07 08 ctrl_af_rden ctrl_wdf_rden usr_ip_add_fifo_empty 5 : 4 X858_05_042606 7 : 5 09 Burst Write 0A Write Wait 07 Burst Read 0B Write Read 08 Read Wait 8 japan.xilinx.com XAPP858 (v1.1) 2007 1 9
R DQS DQ Virtex-5 I/O ODDR ODDR (DQ) (DQS) DQS DQ (DQS) CLK0 180 6 ODDR CLK90 DQS DQ 7 16 Write Data Rise D1 DQ Write Data Fall D2 ODDR FPGA Clock (CLK90) X858_06_042606 6 : OSERDES CLK0 CLK Forwarded to Memory Device Command WRITE IDLE Strobe (DQS) Data (DQ), OSERDES Output D0 D1 D2 D3 X858_07_041806 7 : 4 (DQS) (DQ) XAPP858 (v1.1) 2007 1 9 japan.xilinx.com 9
8 333MHz (667Mb/s) 8 : 333MHz DQS DQS T CLOCK 3000 T MEMORY_DLL_DUTY_CYCLE_DIST 150 150 150 DLL ( ) T DATA_PERIOD T DATA_PERIOD 1350 10% T SETUP 100 100 0 T HOLD 175 0 175 T PACKAGE_SKEW 30 30 30 DQS PCB DQ T JITTER T CLOCK_SKEW-MAX T CLOCK_OUT_PHASE DQS DQ DCM ( ) DCM T PCB_LAYOUT_SKEW 50 50 50 : 1. 10 japan.xilinx.com XAPP858 (v1.1) 2007 1 9
R 2 Virtex-5 I/O ISERDES ISERDES CLK OCLK CLKDIV 3 CLK (DQS) OCLK (FPGA ) CLKDIV ( FPGA ) CLK : BUFIO DQS ISERDES CLK ( 8) OCLK : ISERDES OCLK ODDR CLK CLKfast_90 ISERDES OCLK ODDR CLK OCLK CLKDIV : OCLK CLKDIV OCLK CLKDIV CLKfast_90 IOB CLB DQ IDELAY Q2 User Interface FIFOs Read Data Rising Q1 Read Data Falling CLK OCLK CLKDIV FPGA Clock Delayed DQS Data delay value based on per bit deskew DQS IDELAY BUFIO 8 : IDDR CLB X858_08_042606 FPGA (DQ) (DQS) FPGA BUFIO DQS CC (Clock-Capable) I/O DQS BUFIO ISERDES CLK BUFIO DQS XAPP858 (v1.1) 2007 1 9 japan.xilinx.com 11
9 333MHz DQS DQ 9 : 333MHz (ps) T CLOCK 3000 T PHASE 1500 DDR T SAMP_BUFIO 350 Virtex-5-3 IOB FF / 150ps T DCD_BUFIO BUFIO T DQSQ + T QHS 580 VT DQS DQ T IDELAYTAP_JIT 20 IDELAY - : 1. T SAMP_BUFIO BUFIO IDELAY IOB DDR VT 2. 3. BUFIO package_skew pcb_layout_skew TDQSQ TQHS 0 ISERDES FPGA DQ ISERDES Q1 Q2 DQS 1 1 10 DQ DQ FPGA FPGA DQS DQS 1 DQS DQS FPGA DQS DQS DQS DQ DQS DQS DQ DQS DQ 12 japan.xilinx.com XAPP858 (v1.1) 2007 1 9
R 9 ISERDES FPGA FPGA Clock DQS at FPGA DQ at FPGA D0 D1 D2 D3 DQS Delayed by BUFIO at IDDR DQ DQ Captured by DQS Domain D0 D1 D2 D3 D0 D2 D1 D3 DQ Recaptured in FPGA Clock Domain D0 Input to Rising FIFO D2 D1 D3 D0 D2 Input to Falling FIFO D1 D3 X858_09_042606 9 : 10 10 : () phy_init_stg1_calib 1 ( ) phy_init_stg2_calib 1 2 ( ) phy_calib_first_calib_done 1 XAPP858 (v1.1) 2007 1 9 japan.xilinx.com 13
10 : () () phy_calib_second_calib_done 1 ctrl_rden 1 FIFO 10 4 CAS 5 0 CLK0 Command READ DQ at Memory Device DQS at Memory Device Delayed DQS at IDDR CLK I/P Delayed DQ at IDDR I/P D0 D1 D2 D3 D0 D1 D2 D3 ctrl_rden Generated by Controller After CAS Latency ISERDES Q2 O/P - Read Data Rising D0 D2 ISERDES Q1 O/P - Read Data Falling D1 D3 WrEn X858_10_042606 10 : CAS 5 4 DDR2 SDRAM ctrl_rden CAS CAS ISERDES 1 11 14 japan.xilinx.com XAPP858 (v1.1) 2007 1 9
R Number of Registers Determined During Calibration ctrl_rden WrEn Write Enable to Read Data FIFOs CLK0 X858_11_041806 11 : 4 4 5 12 1. FIFO : FIFO FWFT (First-Word-Fall-Through) FIFO FIFO 2. / 3. write_to_read read_to_write FIFO 4. DDR2 XAPP858 (v1.1) 2007 1 9 japan.xilinx.com 15
rst ~phy_init_done Idle cmd wr Active Active Wait Command Wait Conf conflict wr Burst Write conflict Command Wait wr Write Wait Precharge rd rd conflict rd Precharge Wait auto refresh Burst_Read rd rd conflict Write Bank Conf Auto Refresh Auto Refresh Wait conflict Read_Wait Read Wait Conf wr conflict X858_16_041806 12 : DDR2 Virtex-5 DDR2 SDRAM MIG (Memory Interface Generator) CORE Generator TM URL IP http://japan.xilinx.com/xlnx/xil_sw_updates_home.jsp 16 japan.xilinx.com XAPP858 (v1.1) 2007 1 9
R 11 64-11 : 64 2118 BUFG 4 IDELAY 200MHz BUFG BUFIO 8 DCM 1-1 XC5VLX50 MT9HTF6472Y-667B3 DDR2 SDRAM SERDES DQS ISERDES FPGA 2006/05/12 1.0 2007/01/09 1.1 XAPP858 (v1.1) 2007 1 9 japan.xilinx.com 17