SIIGX51005-1.0 5. & IEEE Std. 1149.1 (JTAG) Stratix II GX IEEE Std. 1149.1 JTAG BST JTAG Stratix II GX Quartus II Jam (.jam) Jam Byte-Code (.jbc) JTAG Stratix II GX JTAG BST IOE I/O JTAG CONFIG_IO I/O Stratix II GX JTAG Stratix II GX JTAG I/O JTAG I/O I/O JTAG TDI TDO TMS TCK 4 TRST 1 TCK TDI TMS TRST JTAG 3.3V VCCPD TDO I/O 4 VCCIO Stratix II GX SignalTap II JTAG Stratix II GX 5 1 JTAG Altera Corporation 5 1
IEEE Std. 1149.1 (JTAG) Stratix II GX Stratix II Stratix Cyclone II Cyclone JTAG 17 JTAG Stratix II GX Stratix II Stratix Cyclone II Cyclone 18 SignalTap II 5 1. Stratix II GX JTAG ( / ) JTAG SAMPLE/PRELOAD 00 0000 0101 SignalTap II EXTEST (1) 00 0000 1111 BYPASS 11 1111 1111 TDI TDO1 BST USERCODE 00 0000 0111 32 USERCODE TDI TDO USERCODE TDO IDCODE 00 0000 0110 IDCODE TDI TDO IDCODE TDO HIGHZ (1) 00 0000 1011 TDI TDO1 I/O BST CLAMP (1) 00 0000 1010 TDI TDO1 I/O BST 5 2 Altera Corporation Stratix II GX Volume 1
& 5 1. Stratix II GX JTAG ( / ) JTAG ICR JTAG Stratix II GXUSB-Blaster MasterBlaster ByteBlasterMV ByteBlaster II JRunner.jam.jbc PULSE_NCONFIG 00 0000 0001 nconfig Low CONFIG_IO (2) 00 0000 1101 JTAG I/O I/O JTAG CONFIG_IO nstatus Low IOE nstatus Low TAP UPDATE_DR SignalTap II SignalTap II 5 1 (1) HIGHZ CLAMP EXTEST (2) CONFIG_IO MorphIO: An I/O Reconfiguration Solution for Altera Devices White Paper Altera Corporation 5 3 Stratix II GX Volume 1
SignalTap II Stratix II GX 10 USERCODE 32 5 2 5 3 Stratix II GX IDCODE 5 2. Stratix II GX EP2SGX30 1,320 EP2SGX60 1,506 EP2SGX90 2,016 EP2SGX130 2,454 5 3. Stratix II GX 32 IDCODE (4 ) IDCODE (32 ) (16 ) ID (11 ) LSB (1 ) EP2SGX30 0000 0010 0000 1100 0010 000 0110 1110 1 EP2SGX60 0000 0010 0000 1100 0011 000 0110 1110 1 EP2SGX90 0000 0010 0000 1100 0100 000 0110 1110 1 EP2SGX130 0000 0010 0000 1100 0101 000 0110 1110 1 SignalTap II Stratix II GX IEEE Std.1149.1 (JTAG) SignalTap II I/O FineLine BGA Stratix II GX CMOS SRAM FPGA 5 4 Altera Corporation Stratix II GX Volume 1
& Stratix II GX (MAX II ) Stratix II GX (FPP) (AS) (PS) (PPA) JTAG Stratix II GX Stratix II GX Stratix II GX AES Stratix II GX FPGA Stratix II GX Stratix II GX SRAM SRAM I/O I/O Altera Corporation 5 5 Stratix II GX Volume 1
Stratix II GX SRAM PORSEL 12ms 100ms (POR) PORSEL POR 100ms PORSEL V CC POR 12ms nio_pullup I/O I/O (ncso ASDO DATA[7..0] nws nrs RDYnBSY ncs CS RUnLU PGM[2..0] CLKUSR INIT_DONE DEV_OE DEV_CLR High 1.5V 1.8V 2.5V 3.3V Low Stratix II GX JTAG 3.3V/2.5V 3.3V V CCPD V CCPD JTAG (TCK TMS TDI TRST) (nconfig DCLK ( ) nio_pullup DATA[7..0] RUnLU nce nws nrs CS ncs CLKUSR) VCCSEL ( )V CCIO V CCIO V IL V IH nconfig DCLKnIO_PULLUP RUnLU nce nws nrs CS ncs CLKUSR 3.3V/2.5V 1.8V/1.5V V CCSEL 1.8V/1.5V V CCIO 3.3V/2.5V V CCPD 5 6 Altera Corporation Stratix II GX Volume 1
& V CCSEL V CCSEL V CCSEL V CCINT V CCPD V CCSEL High 1.8V/1.5V Low 3.3V/2.5V V CCSEL MAX II 3.3V/2.5V V CCSEL Low I/O V CCIO 1.8V/1.5V V CCSEL High V CCIO 1.8V/1.5V TDO nceo Stratix II GX Volume 1 Stratix II GX Stratix II GX 5 5 4 Stratix II GX JTAG Stratix II GX (nce) (nceo) 5 Stratix II GX Stratix II GX FPGA Altera Corporation 5 7 Stratix II GX Volume 1
Stratix II GX 5 4 Stratix II GX Stratix II GX Volume 2 Stratix II GX 5 4. Stratix II GX FPP AS PS PPA MAX II Flash MAX II Flash (1) (1) (2) (3) (4) MAX II Flash JTAG (4) MAX II Flash 5 4 (1) 4 DCLK (2) Stratix II GX (3) AS (4) USB-Blaster (USB) MasterBlaster /USB ByteBlaster II ByteBlasterMV 5 8 Altera Corporation Stratix II GX Volume 1
& Stratix II Stratix II GX FPGA (Advanced Encryption Standard AES FPGA 128 Stratix II GX FPGA Stratix II GX FPGA 128 Stratix II GX (PS) (AS) (FPP) 4x DCLK FPGA Stratix II GX FPGA Stratix II GX FPGA Stratix II GX FPGA SRAM Stratix II GX FPGA FPP(MAX II / Flash ) AS PS PPA JTAG Altera Corporation 5 9 Stratix II GX Volume 1
Stratix II GX Time-to- Market Stratix II FPGA Stratix II GX (Nios II ) FPP AS PS PPA Stratix II GX AES Strtaix II GX Stratix II GX Stratix II GX Volume 2 Stratix II GX 5 10 Altera Corporation Stratix II GX Volume 1
& JRunner Stratix II GX FPGA JRunner JTAG ByteBlaster II ByteBlasterMV Stratix II GX FPGA Raw Binary File(.rbf) JRunner Quartus II Chain Description File (.cdf) JRunner JTAG / Windows NT OS JRunner JRunner Software Driver: An Embedded Solution to the JTAG Configuration White Paper (www.altera.co.jp) SRunner SRunner SRunner SRunner (.rpd) SRunner Quartus II SRunner SRunner: An Embedded Solution for Serial Configuration Device Programming White Paper (EPCS1 EPCS4 & EPCS64) Altera Corporation 5 11 Stratix II GX Volume 1
MicroBlaster Driver Stratix II FPGA MicroBlaster RBF FPP PS Windows NT MicroBlaster Configuring the MicroBlaster Fast Passive Parallel Software Driver White PaperConfiguring the MicroBlaster Passive Serial Software Driver White Paper PLL Stratix II GX PLL Phase-Locked Loop VCO I/O PLL PLL PLL Stratix II GX PLL Stratix II GX Volume 2 Stratix II & Stratix II GX PLL Stratix II GX Maxim Integrated Products MAX1617A MAX1619 Stratix II GX 8 (7 1 ) Stratix II GX 5-1 Stratix II GX 2 (tempdiodep tempdioden) Stratix II GX 5 12 Altera Corporation Stratix II GX Volume 1
& 5-1. Stratix II GX Device Temperature-Sensing Device tempdiodep tempdioden 5 5 Stratix II GX 5 5. IBIAS (High) 80 100 120 µa IBIAS (Low) 8 10 12 µa VBP - VBN 0.3 0.9 V VBN 0.7 V 3 Ω 5-2 Altera Corporation 5 13 Stratix II GX Volume 1
SEU 5-2. 0.95 0.90 0.85 0.80 100 µa Bias Current 10 µa Bias Current 0.75 Voltage (Across Diode) 0.70 0.65 0.60 0.55 0.50 0.45 0.40 55 30 5 20 45 70 95 120 Temperature ( C) SEU Stratix II GX SEU Single Event Upset Quartus II Device & Pin Options CRC Cyclic Redundancy Check 32 CRC SEU CRC Stratix II GX Stratix II GX CRC SRAM CRC_ERROR 5 14 Altera Corporation Stratix II GX Volume 1
& Stratix II GX SRAM 1 Quartus II 4.1 Device & Pin Options CRC CRC 400kHz 50MHz CRC Stratix II GX FPGA SRAM CRC AN 357: Error Detection Using CRC in Altera FPGA Devices Altera Corporation 5 15 Stratix II GX Volume 1
SEU 5 16 Altera Corporation Stratix II GX Volume 1