インテル(R) Itanium(R) 2 プロセッサ・ハードウェア・デベロッパーズ・マニュアル

Transcription

1 Itanium Intel Corporation : J-001 Web: ( ) ( )

2 Itanium Intel Corporation * Intel Corporation. I2C Phillips 2 / SMBus 12C / I2C / SMBus / Phillips Electronics( ) North American Phillips Corporation ii Itanium 2

3 Itanium PAL (Processor Abstraction Layer) Itanium EPIC (FPU) (RSE) L L L L ALAT (Advanced Load Address Table) (TLB) IA Itanium IA Itanium 2

4 A Itanium Itanium /ID / BERR# BERR# BERR# BINIT# BINIT# ID RESET# INIT (TAP) TAP TAP TAP (ITP) (LAI) A-1 A.1...A-1 A.1.1 A[49:3]# (I/O)...A-1 A.1.2 A20M# (I)...A-1 A.1.3 ADS# (I/O)...A-1 A.1.4 AP[1:0]# (I/O)...A-1 A.1.5 ASZ[1:0]# (I/O)...A-1 A.1.6 ATTR[3:0]# (I/O)...A-2 A.1.7 BCLKp/BCLKn (I)...A-2 A.1.8 BE[7:0]# (I/O)...A-3 A.1.9 BERR# (I/O)...A-3 A.1.10 BINIT# (I/O)...A-4 A.1.11 BNR# (I/O)...A-4 iv Itanium 2

5 A.1.12 BPM[5:0]# (I/O)... A-4 A.1.13 BPRI# (I)... A-4 A.1.14 BR[0]# (I/O) BR[3:1]# (I)... A-4 A.1.15 BREQ[3:0]# (I/O)... A-5 A.1.16 CCL# (I/O)... A-6 A.1.17 CPUPRES# (O)... A-6 A.1.18 D[127:0]# (I/O)... A-6 A.1.19 D/C# (I/O)... A-6 A.1.20 DBSY# (I/O)... A-6 A.1.21 DBSY_C1# (O)... A-6 A.1.22 DBSY_C2# (O)... A-6 A.1.23 DEFER# (I)... A-7 A.1.24 DEN# (I/O)... A-7 A.1.25 DEP[15:0]# (I/O)... A-7 A.1.26 DHIT# (I)... A-7 A.1.27 DPS# (I/O)... A-8 A.1.28 DRDY# (I/O)... A-8 A.1.29 DRDY_C1# (O)... A-8 A.1.30 DRDY_C2# (O)... A-8 A.1.31 DSZ[1:0]# (I/O)... A-8 A.1.32 EXF[4:0]# (I/O)... A-8 A.1.33 FCL# (I/O)... A-9 A.1.34 FERR# (O)... A-9 A.1.35 GSEQ# (I)... A-9 A.1.36 HIT# (I/O) HITM# (I/O)... A-9 A.1.37 ID[9:0]# (I)... A-9 A.1.38 IDS# (I)... A-9 A.1.39 IGNNE# (I)... A-9 A.1.40 INIT# (I)... A-9 A.1.41 INT (I)... A-10 A.1.42 IP[1:0]# (I)... A-10 A.1.43 LEN[2:0]# (I/O)... A-10 A.1.44 LINT[1:0] (I)... A-10 A.1.45 LOCK# (I/O)... A-10 A.1.46 NMI (I)... A-11 A.1.47 OWN# (I/O)... A-11 A.1.48 PMI# (I)... A-11 A.1.49 PWRGOOD (I)... A-11 A.1.50 REQ[5:0]# (I/O)... A-11 A.1.51 RESET# (I)... A-12 A.1.52 RP# (I/O)... A-12 A.1.53 RS[2:0]# (I)... A-13 A.1.54 RSP# (I)... A-13 A.1.55 SBSY# (I/O)... A-13 A.1.56 SBSY_C1# (O)... A-13 A.1.57 SBSY_C2# (O)... A-13 A.1.58 SPLCK# (I/O)... A-13 A.1.59 STBn[7:0]# STBp[7:0]# (I/O)... A-14 A.1.60 TCK (I)... A-14 A.1.61 TDI (I)... A-14 A.1.62 TDO (O)... A-14 Itanium 2

6 A.1.63 THRMTRIP# (O)...A-14 A.1.64 THRMALERT# (O)...A-15 A.1.65 TMS (I)...A-15 A.1.66 TND# (I/O)...A-15 A.1.67 TRDY# (I)...A-15 A.1.68 TRST# (I)...A-15 A.1.69 WSNP# (I/O)...A-15 A.2...A Itanium Itanium Itanium 2 FMAC Itanium BR[3:0]# (4 ) BR[3:0]# (2 ) TAP STBp[7:0]# STBn[7:0]# Itanium 2 BREQ[3:0]# (4 ) Itanium 2 BREQ[3:0]# (2 ) ID Itanium Itanium 2 (PAL ) vi Itanium 2

7 5-7 Itanium INIT Itanium 2 TAP A-1... A-2 A-2... A-2 A-3... A-3 A-4 BR0# (I/O) BR1# BR2# BR3# (4P )... A-5 A-5 BR0# (I/O) BR1# BR2# BR3# (2P )... A-5 A-6 BR[3:0]# ID... A-5 A-7 DID[9:0]#... A-7 A-8... A-8 A-9... A-10 A-10 REQa#/REQb#... A-12 A-11 STBp[7:0]# STBn[7:0]#... A-14 A A-15 A A-16 A-14 / ( )... A-17 A-15 / ( )... A-18 Itanium 2

8 viii Itanium 2

9 1 Itanium 2 Itanium 2 / Itanium EPIC (Explicitly Parallel Instruction Computing ) RISC CISC EPIC Itanium 2 Microsoft Windows* HP-UX* Linux* Itanium 2 Itanium 2 SMBus (RAS) Itanium 2 / e-business 1.1 Itanium 2 Itanium 2 Itanium AGTL+ (Assisted Gunning Transceiver Logic ) (V CTERM ) Itanium 2 V CTERM V CTERM ( ) Itanium 2 V CTERM V CTERM AGTL+ (V REF ) V REF 0 1 Itanium 2 V REF 1.2 PAL (Processor Abstraction Layer) Itanium 2 PAL (Processor Abstraction Layer) PAL PAL PAL Itanium 2 : Itanium 2 PAL SAL (System Abstraction Layer) SAL Itanium Processor Family System Abstraction Layer Specification Itanium 2

10 1.3 # ( ) RESET# NMI ( ) # D[3:0] = HLHL 16 A D [3:0] # = LHLH 16 A (H = L = ) A[49:3]# 1 1 a (Aa[49:3]# A[49:3]#) 2 (DID[9:0]# ) b (Ab[25:16]# ) RESET# I/O : VCTERM ( V CC,core ) ( T CO ) 1.4 Intel Itanium 2 Processor at 1 GHz and 900 MHz Datasheet Intel Itanium 2 Processor Specification Update Itanium 1 : J 2 : J 3 : J Intel Itanium 2 Processor BSDL Model Itanium 2 : J Intel Itanium Processor Family System Abstraction Layer Specification Intel Itanium Processor Family Error Handling Guide ITP700 Debug Port Design Guide Itanium 2

11 Itanium 2

12 1-4 Itanium 2

13 Itanium 2 2 Itanium 2 Itanium Itanium 2.1 Itanium 2 Itanium (ISA) 2 Itanium 2 EPIC EPIC EPIC (ILP) ILP EPIC Itanium 2 1GHz 900MHz 6 8 ILP GB/ 3MB 1.5MB L3 MP EPIC Itanium 2 EPIC ALU 6 ALU ( 2 ) 3 ALU (A) ALU (I) (M) (F) (B) (L) Itanium 2 Itanium 3 Itanium 2

14 Itanium Itanium 2 Itanium 2 : MII/MBB (2 / 2 ALU 2 ALU 2 ) MIB/MIB MFI 1 12 ( ALU 2 ALU ) SIMD 1 20 (8 8 2 ALU 2 ALU ) M F I M F I 6 Instructions Provide: : 12 / ( ) Parallel Ops/Clock / for ( Scientific Computing ) 20 Parallel Ops/Clock for Digital Content Creation 2 Load fld4 DP (8 SP) 4 4 DP DP FLOPS FLOPS 2 ALU 2 Ops ALU 4 Ops DP via (8 2 Fld-pair SP) (8 (8 SP SP FLOPS) 2 ALU Ops (Post 2 ALU ( incr.) ) M I I M B B 6 Instructions Provide: : 8 / ( 8 Parallel Ops/Clock for Enterprise and ) Internet Applications 2 2 Loads ALU 2 ALU Ops 2 Branch Insts. 2 2 ALU ALU Ops ( (Post incr.) ) : Note: SP SP - - Single Precision DP - DP - Double Precision Itanium (ROT) 2 ( (EXP) (REN)) (REG) REG 3 (DET) Itanium 2 Itanium 2 : 2-2 Itanium 2

15 Itanium Itanium 2 Front-end Execution Core 1 Pre-fetch/Fetch of 6 6 Instructions/Clock / 4 Single Cycle ALU, 2 Load/Stores ALU 2 Hierarchy of Branch Predictors Advanced Load / Control Decoupling Buffer Predicate Delivery and Branch NaT/ NaT/Exceptions/Retirement / IPG ROT EXP REN REG EXE DET WRB Instruction Delivery 11 Dispersal of 6 Instructions onto 6 11 Issue Ports Register Remapping Register Save Engine Operand Delivery Register File Read and Bypass Register Scoreboard Predicated Dependencies a Itanium 2 Itanium L1 2. ALU (FP) L1 FP 3. (RSE) 4. L2 L3 PIC (Programmable Interrupt Controller ) (TLB) ALAT (Advanced Load Address Table) 5. IA-32 IA-32 IA-32 Itanium 2

16 2-3. Itanium 2 L3 L3 Cache L2 L2 Cache - - Quad Port Branch Prediction Scoreboard, Predicate, NaTs, Exceptions NaT L1 L1 Instruction Cache / and ITLB Fetch/Pre-fetch Engine Instruction Queue 88Bundles B B B M M M M I I F F Register Stack Engine / Re-Mapping / IA-32 IA-32 Decode and Control Branch & Predicate 128 Integer Registers FP FP Registers Registers Integer Branch Dual-Port and Units MM L1 L1 MM Units Data Floating Cache Point and Units DTLB ALAT Bus Controller a Itanium 2 Itanium 2 Itanium 2 (IP) Itanium 2 L1 (L1I) 2 (1 3 ) / 2-4 Itanium 2

17 Itanium Itanium 2 0 L1I L2 L1I L2 L2 L1 L2 L2 L Itanium ( 6 ) Itanium / Itanium 2 FP L1 L2 FP FP L2 L1 L SIMD (Single Instruction Multiple Data) (FPU) Itanium 2 Itanium 2 FPU 4 FP FP FP FMAC (FP Multiply Accumulate) SIMD Itanium 2 2 FP ( 2 ) 2 FP 2 FP ( 4 FP ) FP Itanium 2

18 FPU 82 2 FMAC FMAC FPU FP FP 4 FMAC 2 82 (2 FMAC )2 FMAC Itanium 2 FMAC 2 2 Stores/Clock / 6 6 x x bits L3 L3 Cache Even Register L2 File L2 (128-entry Cache Odd bits) ) 4 4 Doubleprecision / Ops/Clock 4 4 Doubleprecision / Ops/Clock (2 (2 ldf x ldf-pair) ) x 82 bits a IA-32 6 ALU 2 2 ALU Itanium 2 Itanium (64 ) GR0 GR GR0 0 GR Itanium 2

19 Itanium (82 ) FR0 FR FR0 FR1 FR FR FR0 FR (1 ) PR0 PR PR (64 ) BR0 BR (RSE) Itanium ISA (RSE) RSE RSE RSE Itanium 2 RSE Itanium 2 : Itanium RSE Itanium 2

20 2.4 Itanium 2 Itanium ( 2-5 ) Itanium Itanium 2 L1D L2 L3 ALAT TLB Itanium 2 IA-32 Itanium 8 unaligned unaligned L1 L2 L3 L1 L1 L1 L2 L2 Itanium 2 L L2 L Itanium 2 L1I L1D b System Bus L2 L3 Itanium Itanium 2 2 Processor a 2-8 Itanium 2

21 Itanium L1 Itanium 2 L1 (L1I) 16KB L1I 4 ( 64 ) ( ) 1 1 ( ) L1I 2 (6 ) L1I L1 L1 4 (2 2 ) 16KB L1D 4 ( 64 ) 2 2 L1 ( ) L1D L1D L2 L2 4 4 L2 256 KB 8 ( 128 ) 16 L2 1 64GB L2 L2 L2 L1I L1D (1 4 ) Itanium 2 L L3 Itanium 2 L3 1.5MB 3MB L3 L3 12 ( 128 ) 8 ( 7 / 1 ) L3 /L1I/L1D L2 32GB/ L3 ECC ALAT (Advanced Load Address Table) ALAT (Advanced Load Address Table) Itanium 2 ALAT ALAT Itanium 2

22 2.5.6 (TLB) Itanium 2 DTLB (Data Translation Lookaside Buffer) ITLB (Instruction Translation Lookaside Buffer) 2 TLB Itanium 2 DTLB L1 DTLB L2 DTLB 2 L1 DTLB L2 DTLB L1D L2/L3 L2 DTLB DTLB ITLB TLB Itanium 8B 32B VHPT (Virtual Hash Page Table) VHPT L2 L3 L1D TLB (DTLB) 1 DTLB (DTLB1) L1 1 DTLB DTLB 32 1 DTLB 4KB 4KB 2 DTLB (DTLB2) 2 DTLB 128 4KB 4GB DTLB (TR) TLB (ITLB) 1 ITLB (ITLB1) L1I 1 ITLB 32 1 ITLB 4KB 2 ITLB (ITLB2) ITLB1 2 ITLB 128 4KB 4GB TR L1 L2 L3 MESI (WC) 1 Itanium 2 WC Itanium 2 WC (WCB) ( ) 2-10 Itanium 2

23 Itanium 2 Itanium Itanium 2 Itanium 2 L1D (L1D ) L2 L3 2.6 IA-32 Itanium 2 IA-32 Itanium 2 Itanium (OS) IA-32 Itanium Itanium 2 IA-32 EPIC IA-32 Itanium 2

24 2-12 Itanium 2

25 3 Itanium 2 Itanium 2 Intel Itanium 2 Processor at 1 GHz and 900 MHz Datasheet A 3.1 Itanium 2 Itanium ( ) ( ) {rcnt} 1 1 [REQUEST] (1 ) (1) (2) A# 1 B# A# 2 B# A# T1 A# T2 A# ( ) 1 T2 T3 B# A# (T2 ) (1 ) B# (T3 ) 1 T2 A# ( T2 )T2 T3 {c} 3-1 ) B# T3 T3 B# T4 Itanium 2

26 T1 T2 T3 T4 T5 CLK BCLKp BCLKn A# B# {c} A# A# B# B# OR 2 ( B# ) BINIT# HIT# HITM# BNR# TND# BERR# (2 ) ( 3-2 ) % 25% 75% 3-2 Itanium 2

27 CLK T1 T2 T3 T4 BCLKp BCLKn DRDY# D# ( ) D1 D2 D3 D4 STBp# ( ) STBn# ( ) D# ( ) D1 D2 D3 D4 STBp# ( ) STBn# ( ) D1 D2 D2 D1 D2 D1 STBp# STBp# STBn# 1 (DRDY#) 3.2 Itanium 2 Intel Itanium 2 Processor at 1 GHz and 900 MHz Datasheet Itanium 2

28 3.2.1 ( 3-1) 3-1. BCLKp BCLKn RESET# PWRGOOD (BCLKp) CLK CLK 5 (BCLKn) RESET# : RESET# Itanium 2 PA L Itanium 2 ( ) RESET# (PWRGOOD) RESET# ( 3-2) ( ) 3-2. BREQ[3:0]# BR[3:0]# BPRI# BNR# LOCK# BR[3:0]# BR0# BREQ[3:0]# 4 4 BR0# BREQ[3:0]# (BREQ[3:0]# ) 1 (BPRI# ) I/O 3-4 Itanium 2

29 BREQn# BREQ[3:0]# BPRI# BPRI# BPRI# BPRI# BNR# BNR# Itanium 2 LOCK# ( 3-3) 3-3. ADS# REQ[5:0]# A[49:3]# AP[1:0]# RP# ADS# REQ[5:0]# A[49:3]# AP[1:0]# RP# ADS# ADS# A[49:3]# AP[1]# A[49:27]# AP[0]# A[26:3]# (RP#) REQ[5:0]# ADS# ( 3-4) 3-4. TND# HIT# HITM# Itanium 2

30 3-4. ( ) DEFER# GSEQ# TND# (PTC.g) PTC.g PTC.g 1 HIT# HITM# ( ) HIT# HITM# HITM# HIT# HITM# DEFER# GSEQ# GSEQ# ( 3-5) 3-5. RS[2:0]# RSP# ( ) TRDY# TRDY# TRDY# RSP# RS[2:0]# 3-6 Itanium 2

31 3.2.6 ( 3-6) ECC DRDY# DRDY_C1# DRDY_C2# DBSY# DRDY_C1# DRDY_C2# SBSY# SBSY_C1# SBSY_C2# D[127:0]# DEP[15:0]# STBp[7:0]# STBn[7:0]# DRDY# DRDY# DRDY# DBSY# DRDY# DRDY# DBSY# SBSY# DRDY# DRDY# SBSY# DBSY# DRDY# SBSY# Itanium 2 DBSY# DRDY# SBSY# 2 3 D[127:0]# 128 BE[7:0]# A[4:3]# DEP[15:0]# D[127:0]# ECC ( ) DEP[15:0]# ECC STBp[7:0]# STBn[7:0]# ( DRDY#) 2 ECC ECC 3-7. STBp[7:0]# STBn[7:0]# ECC STBp[7]# STBn[7]# D[127:112]# DEP[15:14]# STBp[6]# STBn[6]# D[111:96]# DEP[13:12]# STBp[5]# STBn[5]# D[95:80]# DEP[11:10]# STBp[4]# STBn[4]# D[79:64]# DEP[9:8]# STBp[3]# STBn[3]# D[63:48]# DEP[7:6]# STBp[2]# STBn[2]# D[47:32]# DEP[5:4]# STBp[1]# STBn[1]# D[31:16]# DEP[3:2]# STBp[0]# STBn[0]# D[15:0]# DEP[1:0]# Itanium 2

32 3.2.7 ( 3-8) (DPS# ) (DEN# ) 3-8. ID ID IDS# ID[9:0]# IDS# ID[9:0]# DID[9:0]# ID A BINIT# BERR# THRMTRIP# THRMALERT# BINIT# BINIT# ( 5 ) BINIT# BINIT# BINIT# BINIT# BINIT# BINIT# BINIT# BINIT# ID BINIT# BINIT# BERR# ( ) BERR# BERR# BERR# BERR# BERR# 2 ( ) BERR# BERR# BERR# BERR# 3-8 Itanium 2

33 BERR# THRMTRIP# Itanium 2 THRMTRIP# RESET# RESET# THRMALERT# ( 3-10) INIT# PMI# LINT[1:0] INIT# PAL INIT# PMI# PMI# LINT[1:0] RESET# LINT[0] INT (8259 ) LINT[1] NMI ( ) IA-32 IA-32 FERR# IGNNE# A20M# Itanium 2 FERR# IA-32 IGNNE# A20M# Itanium 2

34 ( 3-11) CPUPRES# CPUPRES# Itanium 2 (GND) Itanium ( 3-12) IEEE / BPM[5:0]# / TCK TDI TDO TMS TRST# BPM[5:0]# / (TCK) 5 (TAP) (TDI) (TDO) (TMS) TAP (TRST#) TAP 3-10 Itanium 2

35 4 Itanium 2 ECC Itanium Processor Family Error Handling Guide 4.1 Itanium 2 ( ) (MCA) 3. MCA 1 OS 4. MCA OS 5. MCA OS 4.2 Itanium 2 Itanium 2 ECC ECC 2 3 RP# RSP# IP[1:0]# 5 Itanium 2

36 4.2.1 ECC 4-1 ECC ECC 4-1. RP# AP[0]# AP[1]# RSP# IP[0]# IP[1]# DEP[7:0]# DEP[15:8]# ADS# REQ[5:0]# A[26:3]# A[49:27]# RS[2:0]# IDS# IDa[9:0]# IDS# ( ) IDb[9:2,0]# D[63:0]# D[127:64]# / AP[1:0]# RP# / RSP# MCA IP[1:0]# MCA Itanium 2 ECC ECC ECC MCA ECC P6 4-2 Itanium 2

37 4.2.3 Itanium 2 ECC BCLK RESET# PWRGOOD# LINT[1:0]# CPUPRES# INIT# THRMTRIP# THRMALERT# Itanium Itanium 2 ECC Itanium 2 ECC 1 I/O ECC Itanium 2

38 4-4 Itanium 2

39 5 Itanium 2 Itanium Itanium 2 PAL Itanium 2 RESET# Intel Itanium 2 Processor at 1 GHz and 900 MHz Datasheet Itanium 2 PAL PAL PAL Itanium Itanium 2 (RESET# ) PAL 0 1 PAL PAL ( ) PAL PAL PAL / PAL / PAL Itanium 2

40 A15# 5-1. PAL /ID / BERR# BERR# PAL_BUS_SET_FEATURES BINIT# ( ) / PAL_BUS_GET_FEATURES E ( ) S BINIT# A10# 0 A15# 0 1 A7# 0 PAL_BUS_GET_FEATURES IOQ 8 A[31:28]# 0000 BR0# BREQ0# BR1# ID PAL_FIXED_ADDR BR2# BR3# A[21:17]# PAL_FREQ_RATIOS 2/8 BREQ0# BR[3:0]# Itanium 2 RESET# PA L PA L Itanium /ID Itanium 2 RS[2:0]# ID ID[9:0]# RESET# PAL PAL 5-2 Itanium 2

41 5.2.3 / Itanium 2 A[49:3]# ADS# REQ[4:0]# RESET# PAL / PAL BERR# Itanium 2 BERR# RESET# BERR# PAL BERR# Itanium 2 ( ) BERR# RESET# BERR# PAL BERR# BERR# BERR# (MCA) PAL BINIT# BINIT# Itanium 2 BINIT# RESET# BINIT# PAL BINIT# RESET# A[10]# BINIT# RESET# A[7]# Itanium 2 1 RESET# A[7]# 8 PAL Itanium 2 RESET# A[15]# RESET# A[15]# ID Itanium Itanium 2

42 ID ID Itanium ID BREQ[3:0]# BREQ[3:0]# I/O (BR0#) 3 (BR1# BR2# BR3#) 5-2. Itanium 2 BREQ[3:0]# (4 ) BREQ[0]# BR[0]# BR[3]# BR[2]# BR[1]# BREQ[1]# BR[1]# BR[0]# BR[3]# BR[2]# BREQ[2]# BR[2]# BR[1]# BR[0]# BR[3]# BREQ[3]# BR[3]# BR[2]# BR[1]# BR[0]# 5-3. Itanium 2 BREQ[3:0]# (2 ) 0 1 BREQ[0]# BR[0]# BR[1]# BREQ[1]# BR[1]# BR[0]# BREQ[2]# BREQ[3]# 5-1. BR[3:0]# (4 ) BPRI# BR0# BR1# BR2# BR3# BR0# BR1# BR2# BR3# BR0# BR1# BR2# BR3# BR0# BR1# BR2# BR3# BREQ0# BREQ1# BREQ2# BREQ3# 5-4 Itanium 2

43 5-2. BR[3:0]# (2 ) Priority Agent BPRI# Agent 0 0 Agent 3 3 BR0# BR1# BR2# BR3# BR0# BR1# BR2# BR3# BREQ0# BREQ1# System Interface Logic During Reset RESET# BREQ0# BREQ[3:1]# RESET# BR[3:1]# ID ID ID ( 5-4 ) 5-4. ID 1 BR0# BR1# BR2# BR3# ID ID L H H H 0 0 H H H L 1 2 H H L H 2 4 H L H H L H Itanium Itanium 2 A[21]# A[20]# A[19]# A[18]# A[17]# 2/ / Itanium 2

44 5.3 PAL RESET# Itanium 2 RESET# RESET# IA-32 Itanium 5-6 PAL Itanium 5-6. Itanium 2 (PAL ) IP Itanium Itanium 2 SALE_RESET RSC mode=0 CFM sof=96 sol=0 sor=0 rrbs= INIT FR GR PR 0 TR TLB TC TLB Itanium 2 INIT INIT INIT# INIT (MC) INIT INIT INIT INIT 5-7 INIT Itanium 5-7. Itanium INIT IP Itanium Itanium 2 PALE_INIT IIP IP INIT IP IPSR PSR INIT PSR IFS v=0 IFS 5-6 Itanium 2

45 (TAP) 6 Itanium 2 (TAP) TAP IEEE (JTAG) IEEE TAP 6-1 Itanium 2 TAP 4 (TDI TCK TMS TRST#) 1 (TDO) TAP ID Intel Itanium 2 Processor Boundary Scan Description Language (BSDL) Model 6-1. Boundary Scan Test Register Control Signals TDI Device Identification TDO BYPASS Register TMS TCK Instruction Decode/ / Control Logic TRST# Instruction Register TAPTap Controller b 1. ANSI/IEEE (IEEE a-1993 ) IEEE Standard Test Access Port and Boundary Scan Architecture, IEEE Press Piscataway NJ 1993 Itanium 2

46 6.1 TAP 5 TCK: TAP TMS: TAP TDI: TRST#: TAP TDO: TMS TDI TDO TCK (TCK ) TRST# 6.2 TAP TAP IEEE TAP ( 6-2) / 2 TAP TMS TAP TDI ( Shift-IR Shift-DR ) TCK 6-2. TAP Run-Test/ 1 TMS Select- Select- 1 Idle DR-Scan IR-Scan Test-Logic- Reset 0 1 Capture-DR Capture-IR 0 Shift-DR 0 Shift-IR Exit1-DR 1 Exit1-IR Pause-DR 0 Pause-IR Exit2-DR 0 1 Update-DR Exit2-IR 1 Update-IR Itanium 2

47 (TAP) TAP IEEE Test-Logic-Reset: IDCODE TAP (TAPFSM) TMS 5 Test-Logic-Reset TRST# TAP Test-Logic-Reset TRST# TAPFSM Run-Test/Idle: TMS Select-IR-Scan: Capture-IR: TCK ( 2 01 ) ( ) Shift-IR: TDI TDO TCK 1 TCK TDO Exit-IR: Pause-IR: Exit2-IR: Update-IR: TCK Update-IR ( TAPFSM ) Select-DR-Scan: Capture-DR: TCK Shift-DR: TDI TDO TCK 1 TCK TDO Exit1-DR: Pause-DR: TCK Itanium 2

48 Exit2-DR: Update-DR: TCK 6.3 TAP TAP 1. Itanium 2 TDI TDO 2. TDI TDO (ID) ID ID IEEE BYPASS EXTEST SAMPLE/PRELOAD IDCODE HIGHZ CLAMP TDI TDO 6.4 TAP 6-1 IEEE TAP IEEE BYPASS ( 1) TAP 0000 xxxx 6-1. Itanium 2 TAP (2 ) (16 ) IEEE BYPASS FFh EXTEST h SAMPLE/PRELOAD h IDCODE h HIGHZ h CLAMP Bh 6-4 Itanium 2

49 (TAP) BYPASS: 1 TDI TDO EXTEST: TDI SAMPLE/PRELOAD SAMPLE/PRELOAD: TDO EXTEST IDCODE: TDO TDI TDO ID ID TAP HIGHZ: HIGHZ TDI TDO CLAMP: 6.5 TAP TAP Test-Logic-Reset TAP ( TAP TAP ) TAP TAP Test-Logic-Reset TAP ( ) TRST# TAP TCK 5 TMS TAP Test-Logic-Reset Itanium 2

50 6-6 Itanium 2

51 7 Itanium 2 (ITP) ( (LAI) ) 7.1 (ITP) Itanium 2 / /IO ITP ITP ITP ITP ITP700 Debug Port Design Guide 7.2 (LAI) (LAI) Itanium 2 Itanium 2 / LAI LAI Itanium 2 2 Itanium 2

52 7-2 Itanium 2

53 A Itanium 2 ( I/O) Intel Itanium 2 Processor at 1 GHz and 900 MHz Datasheet A.1 A.1.1 A.1.2 A.1.3 A.1.4 A.1.5 A[49:3]# (I/O) (A[49:3]#) ( ) 2 50 ADS# ADS# Itanium 2 A[49:27]# AP1# A[26:3]# AP0# RESET# A[49:3]# A20M# (I) Itanium 2 A20M# ADS# (I/O) (ADS#) A[49:3]# REQ[5:0]# AP[1:0]# RP# ADS# ID AP[1:0]# (I/O) (AP[1:0]#) ADS# A[49:3]# AP[1]# A[49:27]# AP[0]# A[26:3]# ASZ[1:0]# (I/O) ASZ[1:0]# REQa[4:3]# 1 ASZ[1:0]# REQa[2:1]# 01B 10B 11B ( ) ASZ[1:0]# A-1 Itanium 2

54 A-1. ASZ[1:0]# (64G - 1) G (1P 1) GB ( Aa[49:36]# 0) ASZ[1:0]# 01 64GB 64GB ( Aa[49:36]# 0 ) ASZ[1:0]# 10 64G (36 ) ASZ[1:0]# 01 64G (36 ) ASZ[1:0]# A.1.6 A-2. ATTR[3:0]# (I/O) ATTR[3:0]# Ab[35:32]# 2 ATTR[3:0]# ATTR[3]# ATTR[2:0]# A-2 ATTR[2:0]# A.1.7 BCLKp/BCLKn (I) BCLKp BCLKn BCLKp BCLKn BCLKp BCLKn Itanium 2 Itanium 2 BCLKp BCLKn A-2 Itanium 2

55 A.1.8 A-3. BE[7:0]# (I/O) BE[7:0]# Ab[15:8]# 2 I/O 128 BE[0]# BE[7]# BE[7:0]# 16 8 A[3]# BE[7:0]# ((REQa[5:0]# = B) (REQb[1:0]# = 01B)) BE[7:0]# A-3 [7:0]# NOP (INVD) (WBINVD) xtpr BE[7:0]# BIL (Bus Invalidate Line) BIL 1 (128 ) A.1.9 BERR# (I/O) (BERR#) MCA BERR# BERR# BERR# BERR# BERR# OR Itanium 2

56 A.1.10 A.1.11 A.1.12 A.1.13 A.1.14 BINIT# (I/O) (BINIT#) BINIT# BINIT# ID L2 L3 BINIT# BINIT# BINIT# OR BNR# (I/O) (BNR#) BNR# OR OR BNR# BPM[5:0]# (I/O) BPM[5:0]# BPRI# (I) (BPRI#) BPRI# ( ) BPRI# BPRI# BR[0]# (I/O) BR[3:1]# (I) BR[3:0]# BREQ[3:0]# BREQ[3:0]# A-4 A-5 4P 2P A-4 Itanium 2

57 A-4. BR0# (I/O) BR1# BR2# BR3# (4P ) BREQ[0]# BR[0]# BR[3]# BR[2]# BR[1]# BREQ[1]# BR[1]# BR[0]# BR[3]# BR[2]# BREQ[2]# BR[2]# BR[1]# BR[0]# BR[3]# BREQ[3]# BR[3]# BR[2]# BR[1]# BR[0]# A-5. BR0# (I/O) BR1# BR2# BR3# (2P ) 0 3 BR[0]# ID BREQ[0]# BR[0]# BR[1]# BREQ[1]# BR[1]# BR[0]# BREQ[2]# BREQ[3]# RESET# BR[3:0]# A-6 A-6. BR[3:0]# ID RESET# ID ID BR[0]# 0 0 BR[3]# 1 2 BR[2]# 2 4 BR[1]# 3 6 A.1.15 BREQ[3:0]# (I/O) BREQ[3:0]# ( ) n BREQn# n BREQn# BREQ[3:0]# ID ID 3 0 ID ( ) ID ( BREQ[3:0]# ) BREQn# BREQn# n BREQ[3:0]# ID Itanium 2

58 ( ) BREQn# BREQn# BREQn# BPRI# ( ) BREQn# BREQn# 1 BREQn# A.1.16 A.1.17 A.1.18 A.1.19 A.1.20 A.1.21 A.1.22 CCL# (I/O) CCL# EXF[2]#/Ab[5]# 2 CCL# CPUPRES# (O) CPUPRES# Itanium 2 Itanium 2 Itanium 2 D[127:0]# (I/O) (D[127:0]#) ( BE[7:0]# A[3]# ) ECC ( ) DRDY# D/C# (I/O) / (D/C#) REQa[1]# (1) (0) DBSY# (I/O) (DBSY#) DBSY# DBSY# 3 (DBSY#) DBSY_C1# (O) DBSY# (DBSY_C1#) DBSY_C2# (O) DBSY# (DBSY_C2#) A-6 Itanium 2

59 A.1.23 A.1.24 A.1.25 A.1.26 A-7. DEFER# (I) DEFER# DEFER# DEN# (I/O) (DEN#) Ab[4]# 2 DEN# DEP[15:0]# (I/O) ECC (DEP[15:0]#) (D[127:0]#) ECC D[127:0]# ECC ECC ECC 4 DHIT# (I) (DHIT#) DHIT# ( HIT# ) DID[9:0]# (I/O) DID[9:0]# A[25:16]# 2 Ab[25:16]# Ab[20:16]# (DEN# ) DID[9:0]# 1 Aa[25:16]# DID[9]# DID[8:5]# ( ) DID[4:0]# (DEN# ) A-7 DID DID[9:0]# DID[9]# DID[8:5]# DID[4:0]# ID[3:0] ID[4:0] DID[9]# 0 1 DID[8:5]# ID ID DID[4:0]# ID ID DID[9:0]# (Ab[25:16]#) Aa[25:16]# Itanium 2

60 A.1.27 A.1.28 A.1.29 A.1.30 A.1.31 A.1.32 A-8. DPS# (I/O) (DPS#) Ab[3]# 2 DPS# DPS# DPS# DRDY# (I/O) (DRDY#) DRDY# DRDY# 3 (DRDY#) DRDY_C1# (O) DRDY# (DRDY_C1#) DRDY_C2# (O) DRDY# (DRDY_C2#) DSZ[1:0]# (I/O) (DSZ[1:0]#) 2 REQb[4:3]# DSZ[1:0]# Itanium 2 DSZ# = 01 EXF[4:0]# (I/O) (EXF[4:0]#) 2 A[7:3]# A-8 EXF[4]# EXF[3]# SPLCK#/FCL# / EXF[2]# OWN#/CCL# / EXF[1]# DEN# EXF[0]# DPS# A-8 Itanium 2

61 A.1.33 A.1.34 A.1.35 A.1.36 A.1.37 A.1.38 A.1.39 A.1.40 FCL# (I/O) (FCL#) A[6]# 2 FCL# (FC) FERR# (O) FERR# IA-32 GSEQ# (I) (GSEQ#) HIT# (I/O) HITM# (I/O) (HIT#) (HITM#) HIT# HITM# HIT# HITM# ID[9:0]# (I) ID (ID[9:0]#) 2 ID IDa[9:0]# IDb[9:0]# ID[9:0]# 2 1 IP0# 2 IP[1]# IDa[9:0]# Ab[25:16]# ID (DID[9:0]#) IDS# (I) ID (IDS#) ID[9:0]# DHIT# IP[1:0]# IGNNE# (I) Itanium 2 IGNNE# INIT# (I) (INIT#) INIT# PAL Itanium 2

62 A.1.41 A.1.42 A.1.43 A-9. INT (I) INT 8259 LINT[0] INT IP[1:0]# (I) ID (IP[1:0]#) 2 IP0# 1 IDa[9:0]# IDS# IP[1]# 2 IDb[9:2, 0]# IDS# LEN[2:0]# (I/O) (LEN[2:0]#) 2 REQb[2:0]# LEN[2:0]# A-9 LEN[2:0]# HITM# RS[2:0]# LEN[2:0]# A.1.44 A.1.45 LINT[1:0] (I) LINT[1:0] RESET# LINT[0] INT (8259 ) LINT[1] NMI ( ) LOCK# (I/O) Itanium 2 LOCK# A-10 Itanium 2

63 A.1.46 A.1.47 A.1.48 A.1.49 A.1.50 NMI (I) NMI NMI 2 NMI NMI NMI NMI EOI NMI 1 NMI NMI NMI NMI NMI 2 NMI (LINT1 ) OWN# (I/O) (OWN#) Ab[5]# 2 OWN# PMI# (I) (PMI#) PMI# PWRGOOD (I) (PWRGOOD) (L) RESET# (H) REQ[5:0]# (I/O) REQ[5:0]# REQa[5:0]# 2 REQb[5:0]# REQb[4:3]# DSZ[1:0]# REQb[2:0]# LEN[2:0]# ( ) 1 2 REQ[5:0]# ADS# RP# REQ[5:0]# A-10 Itanium 2

64 A-10. REQa#/REQb# REQa[5:0]# REQb[5:0]# x x x x x x x x x x DSZ[1:0]# DSZ[1:0]# DSZ[1:0]# 0 1 x DSZ[1:0]# 0 x x DSZ[1:0]# TC DSZ[1:0]# DSZ[1:0]# 1 1 x I/O DSZ[1:0]# x x x I/O DSZ[1:0]# x x x x 0 DSZ[1:0]# x x x 0 ASZ[1:0]# DSZ[1:0]# LEN[2:0]# 0 ASZ[1:0]# DSZ[1:0]# LEN[2:0]# 0 ASZ[1:0]# 1 D/C# 0 0 DSZ[1:0]# LEN[2:0]# 1 ASZ[1:0]# DSZ[1:0]# LEN[2:0]# ( ) 1 ASZ[1:0]# DSZ[1:0]# LEN[2:0]# 0 ASZ[1:0]# 1 WSNP# 1 0 DSZ[1:0]# LEN[2:0]# 1 ASZ[1:0]# 1 WSNP# 1 0 DSZ[1:0]# A.1.51 A.1.52 RESET# (I) RESET# (M ) RESET# 1 V CC BCLKp RESET# 1ms RESET# 2 RESET# RESET# RP# (I/O) (RP#) ADS# REQ[5:0]# A-12 Itanium 2

65 A.1.53 A.1.54 A.1.55 A.1.56 A.1.57 A.1.58 RS[2:0]# (I) (RS[2:0]#) ( ) RSP# (I) (RSP#) RS[2:0]# (RSP# ) ( ) RS[2:0]# (RS[2:0]#=000) RSP# RSP# SBSY# (I/O) (SBSY#) SBSY# DRDY# ( )DRDY# SBSY# DBSY# SBSY# 3 (SBSY#) SBSY_C1# (O) SBSY# (SBSY_C1#) SBSY_C2# (O) SBSY# (SBSY_C2#) SPLCK# (I/O) (SPLCK#) Ab[6]# 2 4 Itanium 2

66 A.1.59 A-11. STBn[7:0]# STBp[7:0]# (I/O) STBp[7:0]# STBn[7:0]# ( DRDY#) BCLKp 2 STBp[7:0]# STBn[7:0]# 2 DRDY# A ECC STBp[7:0]# STBn[7:0]# ECC STBp[7]# STBn[7]# D[127:112]# DEP[15:14]# STBp[6]# STBn[6]# D[111:96]# DEP[13:12]# STBp[5]# STBn[5]# D[95:80]# DEP[11:10]# STBp[4]# STBn[4]# D[79:64]# DEP[9:8]# STBp[3]# STBn[3]# D[63:48]# DEP[7:6]# STBp[2]# STBn[2]# D[47:32]# DEP[5:4]# STBp[1]# STBn[1]# D[31:16]# DEP[3:2]# STBp[0]# STBn[0]# D[15:0]# DEP[1:0]# A.1.60 A.1.61 A.1.62 A.1.63 TCK (I) (TCK) IEEE (TAP) TDI (I) (TDI) Itanium 2 TDI IEEE (TAP) TDO (O) (TDO) Itanium 2 TDO IEEE (TAP) THRMTRIP# (O) (THRM TRIP#) Itanium 2 ( THRMTRIP# ) THRMTRIP# RESET# A-14 Itanium 2

67 A.1.64 A.1.65 A.1.66 A.1.67 A.1.68 A.1.69 THRMALERT# (O) THRMALERT# (THIGH) (TLOW) TMS (I) (TMS) IEEE (TAP) TND# (I/O) TLB (TND#) TLB TLB TRDY# (I) (TRDY#) TRST# (I) TAP (TRST#) IEEE (TAP) WSNP# (I/O) (WSNP#) A.2 A-12 A-15 Itanium 2 I/O A-12. CPUPRES# DBSY_C1# BCLKp DBSY_C2# BCLKp DRDY_C1# BCLKp DRDY_C2# BCLKp FERR# PC SBSY_C1# BCLKp SBSY_C2# BCLKp TDO TCK TAP THRMTRIP# THRMALERT# Itanium 2

68 A-13. BPRI# BCLKp BR1# BCLKp BR2# BCLKp BR3# BCLKp BCLKp BCLKn D/C# BCLKp ( ) DEFER# BCLKp DHIT# BCLKp IDS#+1 GSEQ# BCLKp ID[9:0]# BCLKp IDS# IDS#+1 IDS# BCLKp INIT# 1 INT (LINT0) IP[1:0]# BCLKp IDS#+1 NMI (LINT1) RESET# BCLKp RS[2:0]# BCLKp RSP# BCLKp PMI# PWRGOOD TCK TDI TCK TMS TCK TRST# TRDY# BCLKp 1. RS[2:0]# A-16 Itanium 2

69 A-14. / ( ) A[49:3]# BCLKp ADS# ADS#+1 ADS# BCLKp AP[1:0]# BCLKp ADS# ADS#+1 ASZ[1:0]# BCLKp ADS# ATTR[3:0]# BCLKp ADS#+1 BE[7:0]# BCLKp ADS#+1 BR0# BCLKp BPM[5:0]# BCLKp CCL# BCLKp ADS#+1 D[127:0]# BCLKp DRDY# DBSY# BCLKp D/C# BCLKp ADS# DEN# BCLKp ADS#+1 DEP[15:0]# BCLKp DRDY# DID[9:0]# BCLKp ADS#+1 DRDY# BCLKp DPS# BCLKp ADS#+1 DSZ[1:0]# BCLKp ADS#+1 EXF[4:0]# BCLKp ADS#+1 FCL# BCLKp ADS#+1 LEN[2:0]# BCLKp ADS#+1 LOCK# BCLKp OWN# BCLKp ADS#+1 REQ[5:0]# BCLKp ADS# ADS#+1 RP# BCLKp ADS# ADS#+1 SBSY# BCLKp SPLCK# BCLKp ADS#+1 STBn[7:0]# STBp[7:0]# WSNP# BCLKp ADS# Itanium 2

70 A-15. / ( ) BNR# BCLKp BERR# BCLKp BINIT# BCLKp HIT# BCLKp HITM# BCLKp TND# BCLKp A-18 Itanium 2

71 A A[43:3]# , A-1 A20M#... A-1 ADS# , A-1 ALAT (Advanced Load Address Table) AP[1:0]# , A-1 ASZ[1:0]#... A-1 ATTR[7:0]#... A-2 B BCLK BCLKN , A-2 BCLKP , A-2 BE[7:0]#... A-3 BERR#...3-8, 5-3, A-3 BINIT#...3-8, 5-3, A-4 BNR# , A-4 BPM[5:0]# , A-4 BPRI# , A-4 BR[3:1]#... A-4 BR0#... A-4 BREQ[3:0]# , A-5 BREQ0# , A-5 BYPASS C CPUPRES#... A-6 D D/C#... A-6 D[63:0]#... A-6 DBSY# , A-6 DBSY#... A-6 DEFER# , A-6 DEN# , A-7 DEP[7:0]# , A-7 DHIT#... A-7 DID[7:0]#... A-7 DPS#... A-8 DRDY# , A-8 DSZ[1:0]#... A-8 E EXTEST F FCL#...A-9 FERR#...A-9 G GSEQ#...A-9 H HIT#...A-9 HITM#...A-9 I IA ID[7:0]#...A-9 IDCODE IDS#...A-9 IGNNE#...A-9 INIT#...3-9, 5-6, A-9 INT... A-10 IP[1:0]#... A-10 L L L LEN[1:0]#... A-10 LINT[1:0]...3-9, A-10 LOCK#...3-4, A-10 O OWN#... A-11 P PAL (Processor Abstraction Layer) PMI#... A-11 PWRGOOD... A-11 R REQ[4:0]#...3-5, A-11 RESET#...5-6, A-12 RESET# RP#...3-5, 4-1, A-12 RS[2:0]#...4-2, 5-2, A-13 RSP#...3-6, 4-1, A-13 Itanium 2-1

72 S SBSY#...3-7, A-13 SPLCK#... A-13 STBN[3:0]#...3-7, A-14 STBP[3:0]#...3-7, A-14 T TCK... A-14 TDI... A-14 TDO... A-14 THERMTRIP#...3-9, A-14 THRMALERT#... A-15 TMS... A-15 TND#... A-15 TRDY#...3-6, A-15 TRST#... A-15 W WSNP#... A-15 ID , A A A A (ECC) A , , (DSZ)...A A (TAP) TCK TDI TDO TMS Itanium 2

73 TRST# (RSE) (TLB) A , 6-4 OR A , 6-4 (FPU) (NMI)...A A (RP#) Itanium 2-3

74 -4 Itanium 2

75 Itanium PAL (Processor Abstraction Layer) Itanium EPIC (FPU) (RSE) L L L L ALAT (Advanced Load Address Table) (TLB) IA Itanium IA Itanium 2

76 A Itanium Itanium /ID / BERR# BERR# BERR# BINIT# BINIT# ID RESET# INIT (TAP) TAP TAP TAP (ITP) (LAI) A-1 A.1...A-1 A.1.1 A[49:3]# (I/O)...A-1 A.1.2 A20M# (I)...A-1 A.1.3 ADS# (I/O)...A-1 A.1.4 AP[1:0]# (I/O)...A-1 A.1.5 ASZ[1:0]# (I/O)...A-1 A.1.6 ATTR[3:0]# (I/O)...A-2 A.1.7 BCLKp/BCLKn (I)...A-2 A.1.8 BE[7:0]# (I/O)...A-3 A.1.9 BERR# (I/O)...A-3 A.1.10 BINIT# (I/O)...A-4 A.1.11 BNR# (I/O)...A-4 A.1.12 BPM[5:0]# (I/O)...A-4 A.1.13 BPRI# (I)...A-4 iv Itanium 2

77 A.1.14 BR[0]# (I/O) BR[3:1]# (I)... A-4 A.1.15 BREQ[3:0]# (I/O)... A-5 A.1.16 CCL# (I/O)... A-6 A.1.17 CPUPRES# (O)... A-6 A.1.18 D[127:0]# (I/O)... A-6 A.1.19 D/C# (I/O)... A-6 A.1.20 DBSY# (I/O)... A-6 A.1.21 DBSY_C1# (O)... A-6 A.1.22 DBSY_C2# (O)... A-6 A.1.23 DEFER# (I)... A-7 A.1.24 DEN# (I/O)... A-7 A.1.25 DEP[15:0]# (I/O)... A-7 A.1.26 DHIT# (I)... A-7 A.1.27 DPS# (I/O)... A-8 A.1.28 DRDY# (I/O)... A-8 A.1.29 DRDY_C1# (O)... A-8 A.1.30 DRDY_C2# (O)... A-8 A.1.31 DSZ[1:0]# (I/O)... A-8 A.1.32 EXF[4:0]# (I/O)... A-8 A.1.33 FCL# (I/O)... A-9 A.1.34 FERR# (O)... A-9 A.1.35 GSEQ# (I)... A-9 A.1.36 HIT# (I/O) HITM# (I/O)... A-9 A.1.37 ID[9:0]# (I)... A-9 A.1.38 IDS# (I)... A-9 A.1.39 IGNNE# (I)... A-9 A.1.40 INIT# (I)... A-9 A.1.41 INT (I)... A-10 A.1.42 IP[1:0]# (I)... A-10 A.1.43 LEN[2:0]# (I/O)... A-10 A.1.44 LINT[1:0] (I)... A-10 A.1.45 LOCK# (I/O)... A-10 A.1.46 NMI (I)... A-11 A.1.47 OWN# (I/O)... A-11 A.1.48 PMI# (I)... A-11 A.1.49 PWRGOOD (I)... A-11 A.1.50 REQ[5:0]# (I/O)... A-11 A.1.51 RESET# (I)... A-12 A.1.52 RP# (I/O)... A-12 A.1.53 RS[2:0]# (I)... A-13 A.1.54 RSP# (I)... A-13 A.1.55 SBSY# (I/O)... A-13 A.1.56 SBSY_C1# (O)... A-13 A.1.57 SBSY_C2# (O)... A-13 A.1.58 SPLCK# (I/O)... A-13 A.1.59 STBn[7:0]# STBp[7:0]# (I/O)... A-14 A.1.60 TCK (I)... A-14 A.1.61 TDI (I)... A-14 A.1.62 TDO (O)... A-14 A.1.63 THRMTRIP# (O)... A-14 A.1.64 THRMALERT# (O)... A-15 Itanium 2

78 A.1.65 TMS (I)...A-15 A.1.66 TND# (I/O)...A-15 A.1.67 TRDY# (I)...A-15 A.1.68 TRST# (I)...A-15 A.1.69 WSNP# (I/O)...A-15 A.2...A-15 vi Itanium 2

79 Itanium Itanium Itanium 2 FMAC Itanium BR[3:0]# (4 ) BR[3:0]# (2 ) TAP Itanium 2

80 viii Itanium 2

81 STBp[7:0]# STBn[7:0]# Itanium 2 BREQ[3:0]# (4 ) Itanium 2 BREQ[3:0]# (2 ) ID Itanium Itanium 2 (PAL ) Itanium INIT Itanium 2 TAP A-1...A-2 A-2...A-2 A-3...A-3 A-4 BR0# (I/O) BR1# BR2# BR3# (4P )...A-5 A-5 BR0# (I/O) BR1# BR2# BR3# (2P )...A-5 A-6 BR[3:0]# ID...A-5 A-7 DID[9:0]#...A-7 A-8...A-8 A-9...A-10 A-10 REQa#/REQb#...A-12 A-11 STBp[7:0]# STBn[7:0]#...A-14 A-12...A-15 A-13...A-16 A-14 / ( )...A-17 A-15 / ( )...A-18 viii Itanium 2

82 ix Itanium 2