DVI-D

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1 DVI-D

2 DVI-D i (VisA) FPGA PCI (VisA Pro ) DVI-D DVI-D Dual Link VisA 128 DVI-D 3.96Gbps Myrinet Imfiniband DVI-D PC TCP/IP Ethernet

3 ii VisA Pro 1 REQ 165MHz VisA Pro 166MHz, 3.97Gbps REQ 102ns 2 1 REQ

4 Abstract High Speed Low Latency Data Transmission on DVI-D Interface iii Yusuke NODA Recently, expectation of large-scale three-dimensional volume data for a highly accurate numerical simulation is rising as a computer performance improves rapidly. In the medical field etc., research of real-time visualization technologies of numerical simulation of large-scale three-dimensional data is being advanced. Volume rendering is a technique of three-dimensional visualization. Because of the characteristic of the processing, for real-time visualization of a large-scale data set, speedup by parallel computation must be required. We aim for construction of parallel volume rendering environment for real-time visualization of a large-scale data set. Now, some policies can be thought as a method of achiving an enviranment of visualization of a large-scale data set, corresponding to the amount of investment of the research resources. In this thesis, we describe a way to realize an environment by using a special hardware for visualization (VisA). And, we introduce the characteristic and the specification of the general-purpose PCI card loaded FPGA (VisA Pro card), which is the implementation object of this thesis, and introduce DVI-D Interface chiefly. Considering speedup in parallel volume rendering, data transmission for composition of intermediate value between each nodes is a bottleneck. realizing the high speed data transmission, we propose a technique with DVI-D Dual Link interface. In this thesis, VisA assumes the parallel pipeline processing with 128 nodes. Because of the node scalability, the parallel computation is not by a frame unit, but by a pixel unit. DVI-D interface can perform high speed data transmission of max 3.96Gbps at single link time. Compared with Myrinet and Imfiniband, it is inferior at the point of high-speed data transmission. But DVI-D Interface is low price and it is good enough in the proposal of this thesis. DVI-D interface is originally an interface aimed for display. In this thesis, we propose data transmission by a pixel unit. For So we propose the technique that cuts the overhead of the blank and margin with display. Opposed to

5 iv packet transmission by Ethernet with TCP/IP protocol in general-purpose PC Communication, Because of the reduction of the protocol overhead, low latency data transmission is enabled. We implemented and evaluated the data transmission with VisA Pro card. We implemented with 1 node first. The transmission is looped. When the high speed data transmission is implemented, at the time of the initial transmission, output of an unsettled value was detected and at the time of main data transmission, the data reception was out of timing. We trasfered the REQ signal that tells the begining of the data transmission so that we prevented reading unsettled data which is the initial output. We transfer standby data with some blank several times so that we could transfer the main data stably. As the result, though max movement frequency of transmission channel is specified to be 165MHz, data transmission was relized at 166MHz by the clock which is built-in VisA Pro card. We confirmed that Data transmission in 3.97Gbps that is more than the max bandwidth of the DVI-D Interface specification. REQ signal and standby data transmission was optimized to minimum so that it took 102ns from the begining of the data transmission to the really data output, so low latency transmission is realized. We implemented with the 2 nodes. Because of an unsettled REQ signal movement that was not detected with the 1 node implementation, the case that transmission was not performed correctly occurred randomly. It is thought that this random unsettled movement occurs unevenly in each of board, and the more number of the node increases, the more boards do unsettled movement. But this is the bug that occur at the initial data transmission state, so this give only the initial output of volume rendering some bug. The implementation of high speed transmission of a large-scale data between nodes is completed, so it is expected to apply to various kinds of parallel volume rendering.

6 DVI-D FPGA FPGA DVI-D Dual Link DVI-D DVI-D HSYNC REQ HSYNC 22

7 FIFO

8 1 3 3 PC / PC VisA(Visualization Accelerator) [1] [2] VisA Pro VisA ASIC (Application Specific Integrated Circuit) FPGA(Field Programmable Gate Array) FPGA PCI ( VisA Pro ) ( ) DVI(Digital Visual Interface)-D Dual Link DVI-D 1

9 2 VisA VisA Pro 3 DVI-D 4, 5 2 (Volume Rendering) VisA VisA Pro (Volume Space) (Voxel) ( ). (Screen) (Pixel) (Surface Rendering) 1 3 C t 3 2

10 1: (Ray Casting) 2 (Ray) v o, v 1, v 2, ( ) Pixel Screen Voxel Volume Space Ray 2: C k = k i 1 (1 t(v i )) c(v i ) t(v j ) i=0 j=0 3

11 T k = k t(v i ) (1) i=0 c(v i ), t(v i ) v i (1) C k = C k 1 + (1 t(v k )) c(v k ) T k 1 T k = t(v k ) T k 1 (2) 1) 3 ( ) 2) [3] VisA 2.2 N N L 1 N = PC (VisA) 4

12 VisA VisA 2 PC 3 VisA Processor Controll unit Mapper Network Cache VolumeMemory Memory VisA C & LookUpTable VisA 3: VisA 3 VisA PC CPU VisA PC 128 PC PCI VisA VisA Z 5

13 1GB/s DVI LVDS GB GB/s PC600 Rambus chanel 4 ( 4.8GB/s) (PCU) 32 PCU RGB 8bit 16bit ( pixel) (30frame/second), (pixel) 30(frame/second) = 128MHz Look Up Table ( C& LUT) RGB 8bit 8bit RAM Mapper CPU VisA Mapper CPU CPU Mapper Mapper FPGA 6

LUT 2.3 FPGA ( ) DDR-SDRAM 2 DVI-D Dual Link FPGA 4: VisA Pro ( ( )) DVI-D Dual Link 2.

14 LUT 2.3 FPGA ( ) DDR-SDRAM 2 DVI-D Dual Link FPGA 4: VisA Pro ( ( )) DVI-D Dual Link DDR-SDRAM SO-DIMM 2 DDR333MHz(PC2700 ) PC 1GB DDR SO-DIMM 128bit 2GB 64bit 1GB 2 2 7

15 5.2GB/s FPGA Xilinx VirtexII FPGA XC2V6000-5(600 ) FPGA 18bit 18bit 18Kbit MHz DVI-D Dual Link DVI-D Dual Link DVI-D LVDS(Low Voltage Different Signaling) SerDes(Serializer/Deserializer) Texas Instruments TFP401/TFP410 1 SerDes 5 [4] [5] DATA[23:0] DE HSYNC VSYNC CTL[3:1] CLK TFP410 Receiver Tx2 Tx1 Tx0 TxC Rx2 Rx1 Rx0 RxC TFP401 Transmitter DATA[23:0] DE HSYNC VSYNC CTL[3:1] CLK 5: SerDes 8bit Blue HSYNC VSYNC 1 8bit Green Ctl1 1 8bit Red Ctl2 Ctl3 1 (VisA Pro 8

16 FPGA ) PLL(Phase Lock Loop) 3 CLOCK 4 Dual Link 165MHz 24bit 165M(cycle) 24(bit/cycle) 2(dual) = 7.92Gbps Single Link 3.96Gbps PCI : PC PCI64/66 PCI32/33 SSRAM : 166MHz 512KB(128K 36bit)SSRAM ZBT(Zero Bus Turnaround) Read/Write Idle 2.4 VisA Pro VisA VisA 6 VisA Pro VisA Pro 1 (PCU) 16 8 PCU (VisA Pro 2 ) 1 VisA Pro DVI-D Dual Link 2.5 ATI GPU CrossFire GPU nvidia SLI 2 GPU 9

17 Volume Memory 0 512MB PC2100 DDR SDRAM 512KB ZBT SSRAM DVI Receiver (TI TFP401) x 2 DVI Transmitter (TI TFP410) x VisA VisA I/F OUT I/F IN Volume Memory Interface 0 PCU 0 PCU PCU 1 64 PCU 9... PCU 7 PCU 8 Volume Memory Interface 1 64 Mapper 0 LUT 32 Mapper 1 PCI Software Processor (32bit, 33MHz, 5V) (MicroBlaze) PCI Bus Volume Memory 1 512MB PC2100 DDR SDRAM FPGA (XC2V FF1517) 6: VisA Pro 2 GPU DVI ATI CrossFire nvidia SLI 2 GPU VisA 128 DVI 3 CrossFire SLI 3 DVI-D DVI-D RGB 8bit 24bit 10

18 DVI-D 3.1 DVI-D DVI-D [6] 7 1 (HSYNC) 1 (VSYNC) 2 7: RGB 8bit 24bit 11

19 HSYNC VSYNC ( ) 8 8: UXGA( ) (1 ) 60Hz CRT LCD VESA (pixel/f rame) 60(f rame/sec) 24(bit/pixel) = 2.76Gbps 60fps CRT LCD (pixel/f rame) 60(f rame/sec) 24(bit/pixel) = 3.87Gbps 12

20 1: UXGA( ) UXGA( ) CRT LCD 2160(pixel) 1760(pixel) 1600(pixel) 1600(pixel) 168(pixel) 32(pixel) 392(pixel) 128(pixel) 1245(pixel) 1245(pixel) 1200(pixel) 1200(pixel) 4(scanline) 4 (scanline) 41(scanline) 41(scanline) (pixel/f rame) 60(f rame/sec) 24(bit/pixel) = 3.13Gbps 2.76Gbps DVI-D bit RGB ( ) (HSYNC) (VSYNC) 2 ( 9 10 ) 11 SerDes 13

21 9: 10: FIFO FIFO FIFO SerDes DVI-D 3.1 REQ 14

22 11: Myrinet Infiniband 10Gbps DVI-D Ethernet PC TCP/IP µs ns RGB 24bit FPGA FPGA FPGA 15

23 3.4 Unreliable / FPGA 4.1 DVI-D 1 UXGA( ) (pixel) 24(bit) = 38.4kbit RGB 8bit 24bit Z UXGA RGB 8bit 8bit 16

24 (pixel/frame) 30(frame/seconf) 32(bit) = 4.03Gbps 1Gpixel 24bit 1 1G(pixel) 24(bit) = 24Gbit DVI-D 165MHz VisA Pro 166MHz 24bit (DATA) DE(Data Enable) 1G G DATA DE bit 8 ROM 8 (Transmitter) 166MHz CLK-Generator DCM(Digital Clock Manager) DCM DCM DLL(Delay Locked Loop) 17

25 12: FPGA EMI (EMI) 1 (Receiver) 18

26 24bit 8 RAM RAM ROM bit (DATA) DE 8 RAM DATA DE WE(Write Enable) RAM DATA DE RAM HSYNC REQ ( REQ ) HSYNC REQ HSYNC VSYNC DATA DE HSYNC VSYNC 4.4 HSYNC VSYNC REQ HSYNC VSYNC HSYNC UXGA HSYNC 4 4 DATA DE ( 13 ) 166MHz 166MHz DCM 100MHz 19

27 13: HSYNC REQ MHz 8 9 DATA DE DATA DE 1 2 RAM bit RGB 8bit DATA[7:0] Blue 14 DATA DE DATA, DE 1 20

28 14: DE DATA : 4(cycle) 2(cycle) 2( ) 4 24bit 1 HSYNC REQ DE DATA 166MHz 21

29 HSYNC : HSYNC REQ HSYNC HSYNC VSYNC Ctl[3:1] HSYNC VSYNC Ctl[3:1] 5bit 24bit DATA

30 24 8 ROM RAM 12 2 (4(branking) + 2(stanby)) 2( ) + 5(REQ) = 17cycle MHz (cycle)/8017(cycle) 166M(Hz) 24(bit) = 3.97Gbps 166MHz 17cycle 17(cycle)/166M(Hz) = 102ns 4.1 UXGA( ) FIFO FIFO 16 FIFO Receiver DATA (R-CLK) FIFO FIFO (T-CLK) FIFO

31 16: FIFO (R-CLK) FIFO (T-CLK) RAM DVI-D REQ HSYNC 1 HSYNC 1 24

32 4.2.1 DATA DE HSYNC 17 REQ ( 17 HSYNC) VSYNC, Ctl HSYNC REQ 17: REQ ( HSYNC) HSYNC

33 5 VisA VisA Pro FPGA DVI-D DVI-D 3.96Gbps 3.97Gbps 102ns REQ RGB ReVolver 2 26

34 4 [1] : VisA,, (2003). [2],,,, : FPGA PCI, CPSY , pp. 1 6 (2005). [3],,,,,,, Ma, K.-L.: VG :, Visual Computing CAD 2001 (2001). [4] : FPGA PC, : (2003). [5] : FPGA 640Mbps LVDS, Design Wave Magazine (2005). [6] : RGB, Interface (2006). 27

23 Fig. 2: hwmodulev2 3. Reconfigurable HPC 3.1 hw/sw hw/sw hw/sw FPGA PC FPGA PC FPGA HPC FPGA FPGA hw/sw hw/sw hw- Module FPGA hwmodule hw/sw FPGA h

23 Fig. 2: hwmodulev2 3. Reconfigurable HPC 3.1 hw/sw hw/sw hw/sw FPGA PC FPGA PC FPGA HPC FPGA FPGA hw/sw hw/sw hw- Module FPGA hwmodule hw/sw FPGA h 23 FPGA CUDA Performance Comparison of FPGA Array with CUDA on Poisson Equation (lijiang@sekine-lab.ei.tuat.ac.jp), (kazuki@sekine-lab.ei.tuat.ac.jp), (takahashi@sekine-lab.ei.tuat.ac.jp), (tamukoh@cc.tuat.ac.jp),