Maxim/D.S.197.J/3846

Transcription

1 ; Rev 1; 6/96 EVALUATION KIT MANUAL AVAILABLE SHDN µ µ µ PART TEMP. RANGE PIN-PACKAGE ACNI BCNI ACWI 0 C to +70 C 0 C to +70 C 0 C to +70 C 28 Narrow Plastic DIP 28 Narrow Plastic DIP 28 Wide SO BCWI 0 C to +70 C 28 Wide SO ACAI 0 C to +70 C 28 SSOP BCAI 0 C to +70 C 28 SSOP BC/D 0 C to +70 C Dice* Ordering Information continued at end of data sheet. *Dice are specified at TA = +25 C, DC parameters only. TOP VIEW CLK 1 CS 2 3 RD 4 HBEN 5 SHDN 6 D7 7 D6 8 D5 9 D4 10 D3/D11 11 D2/D10 12 D1/D9 13 D0/D DGND 27 V DD 26 REF INT 23 CH7 22 CH6 21 CH5 20 CH4 19 CH3 18 CH2 17 CH1 16 CH0 15 AGND DIP/SO/SSOP/Ceramic SB Maxim Integrated Products 1

2 ABSOLUTE MAXIMUM RATINGS V DD to AGND V to +7V AGND to DGND V to +0.3V REF to AGND V to (V DD + 0.3V) to AGND V to (V DD + 0.3V) Digital Inputs to DGND V to (V DD + 0.3V) Digital Outputs to DGND V to (V DD + 0.3V) CH0 CH7 to AGND...±16.5V Continuous Power Dissipation (T A = +70 C) Narrow Plastic DIP (derate 14.29mW/ C above +70 C) mW Wide SO (derate 12.50mW/ C above +70 C) mW SSOP (derate 9.52mW/ C above +70 C)...762mW Narrow Ceramic SB (derate 20.00mW/ C above +70 C)..1600mW Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated in the operational sectio of the specificatio is not implied. Exposure to absolute maximum rating conditio for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Operating Temperature Ranges _C...0 C to +70 C _E C to +85 C _M C to +125 C Storage Temperature Range C to +150 C Lead Temperature (soldering, 10sec) C ± µ PARAMETER ACCURACY (Note 1) Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Channel-to-Channel Offset Error Matching Gain Error (Note 2) Gain Temperature Coefficient (Note 2) Total Harmonic Distortion Spurious-Free Dynamic Range Channel-to-Channel Crosstalk Aperture Delay Aperture Jitter SYMBOL INL DNL THD SFDR A B Unipolar Bipolar Unipolar Bipolar Unipolar Bipolar Unipolar Bipolar Up to the 5th harmonic CONDITIONS A B A B A B A B DYNAMIC SPECIFICATIONS (10kHz sine-wave input, ±10Vp-p, f SAMPLE = 100ksps) Signal-to-Noise + Distortion Ratio SINAD A B 50kHz, V IN = ±5V (Note 3) External CLK mode/external acquisition control External CLK mode/external acquisition control Internal CLK mode/internal acquisition control (Note 4) MIN TYP MAX 12 ±1/2 ±1 ±1 ±3 ±5 ±5 ±10 ±0.1 ±0.5 ±7 ±10 ±7 ± <50 10 UNITS Bits LSB LSB LSB LSB LSB ppm/ C db db db db ps 2

3 ELECTRICAL CHARACTERISTICS (continued) ± µ PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ANALOG INPUT Track/Hold Acquisition Time f CLK = 2.0MHz 3 µs ±10V range 5 Small-Signal Bandwidth -3dB rolloff ±5V range 2.5 0V to 10V range 2.5 MHz 0V to 5V range Unipolar Input Voltage Range 0 5 (See Table 1) Bipolar -5 5 V Input Current Unipolar 0V to 10V range 720 0V to 5V range 360 Bipolar -10V to 10V range V to 5V range µa Input Dynamic Resistance Unipolar 21 Bipolar 16 kω Input Capacitance (Note 5) 40 pf INTERNAL REFERENCE REF Output Voltage V REF T A = +25 C V REF Output Tempco TC V REF 40 ppm/ C Output Short-Circuit Current 30 ma Load Regulation 0mA to 0.5mA output current (Note 6) 7.5 mv Capacitive Bypass at REF 4.7 µf Output Voltage V Adjustment Range With recommended circuit (Figure 1) ±1.5 % Buffer Voltage Gain V/V REFERENCE INPUT (Buffer disabled, reference input applied to REF pin) Input Voltage Range V Input Current V REF = 4.18V Normal or STANDBY power-down mode 400 FULL power-down mode 1 µa Input Resistance Normal or STANDBY power-down mode 10 kω FULL power-down mode 5 MΩ Threshold for Buffer Disable V DD - 50mV V 3

4 ELECTRICAL CHARACTERISTICS (continued) ± µ PARAMETER POWER REQUIREMENTS Supply Voltage Supply Current Power-Supply Rejection Ratio (Note 8) TIMING Internal Clock Frequency External Clock Frequency Range Acquisition Time Conversion Time Throughput Rate Bandgap Reference Start-Up Time SYMBOL V DD I DD PSRR f CLK f CLK t ACQI t ACQE t CONV CONDITIONS Normal mode, bipolar ranges Normal mode, unipolar ranges Standby power-down (STBYPD) Full power-down mode (FULLPD) (Note 7) External reference = 4.096V MIN TYP MAX ±1/ 2 Internal reference ±1/ 2 C CLK = 100pF Internal acquisition External CLK 3.0 Internal CLK External acquisition (Note 9) 3.0 After FULLPD or STBYPD 5 External CLK 6.0 Internal CLK, C CLK = 100pF External CLK 100 Internal CLK, C CLK = 100pF 62 UNITS Power-up (Note 10) 200 µs Reference Buffer Settling To 0.1mV REF bypass C REF = 4.7µF 8 capacitor fully discharged C REF = 33µF 60 ms DIGITAL INPUTS (D7 D0, CLK, RD,, CS, HBEN, SHDN) (Note 11) Input High Voltage V INH 2.4 V Input Low Voltage V INL 0.8 V Input Leakage Current I IN V IN = 0V or V DD ±10 µa Input Capacitance C IN (Note 5) 15 pf DIGITAL OUTPUTS (D7 D4, D3/D11, D2/D10, D1/D9, D0/D8, INT) Output Low Voltage V OL V DD = 4.75V, I SINK = 1.6mA 0.4 V Output High Voltage V OH V DD = 4.75V, I SOURCE = 1mA V DD - 1 V Three-State Output Capacitance C OUT (Note 5) 15 pf V ma µa LSB MHz MHz µs µs ksps 4

5 TIMING CHARACTERISTICS ± µ PARAMETER CS Pulse Width Pulse Width CS to Setup Time CS to Hold Time CS to RD Setup Time CS to RD Hold Time CLK to Setup Time CLK to Hold Time Data Valid to Setup Data Valid to Hold RD Low to Output Data Valid HBEN High or HBEN Low to Output Valid RD High to Output Disable RD Low to INT High Delay SYMBOL t CS t t CSWS t CSWH t CSRS t CSRH t CWS t CWH t DS t DH t DO t DO1 t TR t INT1 (Note 13) CONDITIONS Figure 2, C L = 100pF (Note 12) Figure 2, C L = 100pF (Note 12) MIN TYP MAX UNITS Note 1: Accuracy specificatio tested at V DD = 5.0V. Performance at power-supply tolerance limits guaranteed by Power-Supply Rejection test. Tested for the ±10V input range. Note 2: External reference: V REF = 4.096V, offset error nulled, ideal last code traition = FS - 3/2LSB. Note 3: Ground "on" channel; sine wave applied to all "off" channels. Note 4: Maximum full-power input frequency for 1LSB error with 10 jitter = 3kHz. Note 5: Guaranteed by design. Not tested. Note 6: Use static loads only. Note 7: Tested using internal reference. Note 8: PSRR measured at full-scale. Note 9: External acquisition timing: starts at data valid at ACQMOD = low control byte; ends at rising edge of with ACQMOD = high control byte. Note 10: Not subject to production testing. Provided for design guidance only. Note 11: All input control signals specified with t R = t F = 5 from a voltage level of 0.8V to 2.4V. Note 12: t DO and t DO1 are measured with the load circuits of Figure 2 and defined as the time required for an output to cross 0.8V or 2.4V. Note 13: t TR is defined as the time required for the data lines to change by 0.5V. 5

6 (T A = +25 C, unless otherwise noted.) INTEGRAL NONLINEARITY (LSB) INTEGRAL NONLINEARITY vs. DIGITAL CODE -1 AMPLITUDE (db) FFT PLOT f tone = 10kHz f sample = 100kHz -2 EFFECTIVE NUMBER OF BITS EFFECTIVE NUMBER OF BITS vs. INPUT FREQUENCY F SAMPLE = 100kHz DIGITAL CODE FREQUENCY (khz) INPUT FREQUENCY (khz) REFERENCE OUTPUT VOLTAGE (V REF) vs. TEMPERATURE POWER-SUPPLY REJECTION RATIO vs. TEMPERATURE V DD = 5V ±0.25V Hz V REF (V) A V = V INTERNAL REF REFERENCE TEMPERATURE ( C) PSRR (LSB) 0 100Hz TEMPERATURE ( C) CHANNEL-TO-CHANNEL OFFSET-ERROR MATCHING (LSB) CHANNEL-TO-CHANNEL OFFSET-ERROR MATCHING vs. TEMPERATURE CHANNEL-TO-CHANNEL GAIN-ERROR MATCHING (LSB) CHANNEL-TO-CHANNEL GAIN-ERROR MATCHING vs. TEMPERATURE TEMPERATURE ( C) TEMPERATURE ( C) 6

7 1 2 3 CLK CS CS CS RD HBEN SHDN D7 D4 D3/D11 D2/D10 D1/D9 D0/D8 AGND CH0 CH7 INT REF V DD DGND CSRD INT µ µ +5V 100k +5V 510k 0.01µF D OUT 3k C LOAD D OUT 3k C LOAD 24k a. High-Z to V OH and V OL to V OH b. High-Z to V OL and V OH to V OL 7

8 µ µ RANGE (V) ZERO SCALE (V) -FULL SCALE +FULL SCALE 0 to 5 0 V REF x to 10 0 V REF x ±5 -V REF x V REF x ±10 -V REF x V REF x µp CONTROL INPUTS 1 100pF CLK DGND CS RD HBEN SHDN D7 D6 D5 D4 D3/D11 D2/D10 D1/D9 D0/D8 V DD REF INT CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 AGND µF +5V V 4.7µF OUTPUT STATUS ANALOG INPUTS CH_ 12.5k 5.12k S1 S2 8.67k HOLD BIPOLAR UNIPOLAR OFF ON S3 C HOLD TRACK TRACK VOLTAGE REFERENCE S4 T/H OUT HOLD µp DATA BUS S1 = BIPOLAR/UNIPOLAR SWITCH S2 = INPUT MUX SWITCH S3, S4 = T/H SWITCH 8

9 µ CS RD CS µ RD CS RD D7 (MSB) D6 D5 D4 D3 D2 D1 D0 (LSB) PD1 PD0 ACQMOD RNG BIP A2 A1 A0 7, 6 PD1, PD0 5 ACQMOD 4 RNG 3 BIP 2, 1, 0 A2, A1, A0 BIP RNG INPUT RANGE (V) to to ±5 1 1 ±10 PD1 PD A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH

10 PIN HBEN = LOW HBEN = HIGH D0 B0 (LSB) B8 D1 B1 B9 D2 B2 B10 D3 B3 B11 (MSB) D4 B4 B11 (BIP = 1) / 0 (BIP = 0) D5 B5 B11 (BIP = 1) / 0 (BIP = 0) D6 B6 B11 (BIP = 1) / 0 (BIP = 0) D7 B7 B11 (BIP = 1) / 0 (BIP = 0) CS µ t CS t CSRS t CSRH CS t CSWS t t ACQI tconv t CSWH t DS t DH D7 D0 CONTROL BYTE ACQMOD ="0" t INT1 INT RD HBEN t D0 t D01 t TR DOUT HGH-Z HIGH / LOW BYTE VALID HIGH / LOW BYTE VALID HGH-Z 10

11 CS t CS t CSWS t t ACQI t CONV t CSHW t CSRS t CSRH t DS t DH D7 D0 CONTROL BYTE ACQMOD = "1" CONTROL BYTE ACQMOD = "0" t INT1 INT RD HBEN t D0 t D01 t TR DOUT HIGH / LOW BYTE VALID HIGH / LOW BYTE VALID µ INT INT µ INTERNAL CLOCK PERIOD () CLOCK PIN CAPACITANCE (pf) 11

12 ACQUISITION STARTS ACQUISITION ENDS CONVERSION STARTS CLK t CWS ACQMOD = "0" GOES HIGH WHEN CLK IS HIGH t CWH ACQUISITION STARTS ACQUISITION ENDS CONVERSION STARTS CLK ACQMOD = "0" GOES HIGH WHEN CLK IS LOW ACQUISITION STARTS ACQUISITION ENDS CONVERSION STARTS CLK t DH t CWS ACQMOD = "1" GOES HIGH WHEN CLK IS HIGH ACQMOD = "0" ACQUISITION STARTS ACQUISITION ENDS CONVERSION STARTS CLK t DH t CWH ACQMOD = "1" GOES HIGH WHEN CLK IS LOW ACQMOD = "0" 12

13 INT µ µ µ µ µ 2.5V A V = k REF V 4.7µF C REF V DD REF µF C REF REF µF C REF A V = A V = k µF 10k V 0.01µF 2.5V 2.5V 13

14 SHDN µ µ µ µ µ OUTPUT CODE FULL-SCALE TRANSITION 1 LSB = FS OUTPUT CODE 1 LSB = 2 FS FS INPUT VOLTAGE (LSB) FS - 3/ 2 LSB -FS 0V INPUT VOLTAGE (LSB) +FS - 1 LSB 14

15 µ µ PART AENI BENI AEWI BEWI AEAI BEAI AMYI BMYI TEMP. RANGE -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C -55 C to +125 C -55 C to +125 C PIN-PACKAGE 28 Narrow Plastic DIP 28 Narrow Plastic DIP 28 Wide SO 28 Wide SO 28 SSOP 28 SSOP 28 Narrow Ceramic SB** 28 Narrow Ceramic SB** ** Contact factory for availability and processing to MIL-STD-883. RD HBEN SHDN D7 CLK V DD CS DGND V CC REF INT CH7 CH " (5.870mm) D6 CH5 +5V SUPPLY GND D5 D4 D3 CH4 CH3 CH2 R* = 5Ω V DD 4.7µF 0.1µF AGND ** DGND +5V DGND D1 D2 D0 AGND 0.144" (3.659mm) CH0 CH1 TRANSISTOR COUNT: 2956 SUBSTRATE CONNECTED TO GND DIGITAL CIRCUITRY * OPTIONAL ** CONNECT AGND AND DGND WITH A GROUND PLANE OR A SHORT TRACE 15

16 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 CLK SIGNAL CONDITIONING BLOCK & OVERVOLTAGE TOLERANT MUX CLOCK REF T/H CHARGE REDISTRIBUTION 12-BIT DAC 12 A V = SUCCESSIVE- APPROXIMATION REGISTER 10k COMP +2.5V REFERENCE CS RD SHDN CONTROL LOGIC & LATCHES 4 4 MUX 8 8 HBEN INT 8 THREE-STATE, BIDIRECTIONAL I/O INTERFACE D0 D7 8-BIT DATA BUS 8 V DD AGND DGND 16 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA (408) Maxim Integrated Products is a registered trademark of Maxim Integrated Products.