AMR日本語版書式

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1 ISSN ISSN ( ) UMC LSI SoC Solution Foundry 90nm 65nm 100nm UMC TSMC UMC SoC SoC 90nm 200mm 300mm 300mm UMC UMC UMC UMC SoC GBRC GBRC 2006 Global Business Research Center 67

2 UMC UMC RF Radio Frequency UMC 8C 8D 8E 8F 12A UMCJ UMCi 2 8A 8B 0.25μm 0.35μm 12A UMCi 300mm 12A , ,000 90nm nm mm 36 UMCi , μm 90nm nm 90nm nm SP Standard Process LL Low Leakage Process L90G 3 90nm 65nm 2005 L80G 80nm 65nm L90G Shrink L80G 2. SoC RF 4 UMC 90nm Low-K FSG 2 A B C 3 L90G 4 RF m RF 68

3 nm UMC 90nm TI 90nm DSP 100nm SoC IR Drop Noise Margin Cross-Talk DFT Design for Testability DFM Design for Manufacturing EDA Electronic Design Automation IP IP Time-to-Market IP IDM Integrated Device Manufacturer IP IP 3G Reciever GPS RF Baseband Processor Audio CODEC DSP Processor SRAM DRAM Flash Memory 3G IP 3D Graphics FM MP3 DAB GPS EOTD MPEG4 JPEG Speech to Text Voice Recognition GSM GPRS EDGE WCDMA/CDMA2000/TDS-CDMA RISC DSP Protocol Stack System BIST WiFi Bluetooth UMC IP SoC 4. SoC UMC 1 UMC SoC High Speed Low Leakage Standard Performance Low Power /RF CMOS Zero Vt Low Vt I/O e-memories embedded Memories Libraries Standard Cell Libraries Standard I/O 69

4 SoC Platform Technology Logic Transistors High Speed Low Leakage Standard Performance Low Power Mixed Signal/RF CMOS Zero Vt,, Low Vt,, 3.3V/2.5V I/O Spiral Cu Inductors Metal-I-Metal Capacitors Poly Resistors Varactor e-memories e-sram e-flash 1T-SRAM, 1T-Q Q SRAM Libraries STD Cells, STD I/O Memory Compilers MM/RF Design Kits SOC Platform Sub-100 nm Cu Technology EDA Tools Technology Files: DRC, LVS, RC Extraction Gold IP Program IP Master Silicon Shuttle = Technology Features = Design Support Features 2 UMC IP Offering by Application Memory MM CPU/DSP Peripheral Application Specific Communication 1T-SRAM 1,3 efuse 1,3 esram 1 ADC/DAC AFE ARM 1,3 MIPS 1,3 MPU/DSP 1,3 Teak SSTL 3, LVDS 4 S-ATA 4, USB 1,3 PCI-Exp 4 Serdes 4 1G PHY/MAC 2 Bluetooth 4 QPSK Computing esram 1 ADC/DAC 3 ARM 1,3 MIPS 1,3 MPU/DSP 1,3 PCI-X/Exp 4 USB 1,3 1G PHY/MAC 2 Bluetooth 4 MPEG2/ , DMA IrDA Consumer 1T-SRAM 1,3 esram 4 ADC/DAC 3 eflash 1 ARM 1,3 MIPS 1,3 MPU/DSP 1,3 Teaklite 3 HSTL 4, USB 1,3 Smartcard DVI 4, LVDS 4 MPEG2/4 4 RSDS 4 AC3/4, QPSK UART 4, SPI4 4 QAM, TMDS IrDA 1: 0.13um 2: 0.15um 3: 0.18um 4: planned All trademarks owned by each individual vendor Memory Compilers MM/RF Design Kit Gold IP Program Silicon Shuttle EDA tools DRC RC Extraction technology files UMC IP UMC Silicon Shuttle Program IP UMC IP pool UMC IP Gold IP Program Bronze IP Silver IP Gold IP Bronze IP IP Soft Core UMC DRC Design Rule Check IP GDS Silver IP IP Gold IP IP 70

5 Off-the-Shelf Process Optimized Library Portfolio Technology Node Library G/SP 90nm LL 130nm HS/LL/ HS Fusion/SP LP 150nm SP ASIC 180nm GII LL Standard Cell Artisan I/O Artisan Single Port SRAM Compiler Dual Port SRAM Compiler Single Port Register File Dual Port Register File ROM Compiler PLL Note: Available or in development. Please check with an UMC representative for detailed status information 4 UMC Design Reference Flow I/O & Memory Simulation View Timing View Standard Cell Simulation View GDS View Power view Noise View Extraction Tech DRC/LVS Rule Deck Product Definition/Spec & Tech-dependent Setting RTL & Simulation Functional Verification Synthesis Physical Synthesis Static Timing Analysis Gate-level & Simulation Floorplan & Partition Block & Top Implementation Physical Verification UMC provides design methodology and flows. Collaboration with major EDA vendors for design flow development. Released Mixed Signal, Timing Closure and Low Power flows in 180/130nm process nodes. Tape-out IP 2 UMC IP Memory MM CPU/DSP Peripheral Application Specific Consumer Computing Communication IP 5 3 UMC Library Portfolio technology node Library 5 IP IP 71

6 UMC IP Cell Libraries 4 UMC Design Reference Flow EDA Cadence MAGMA Mentor Graphics Synopsys IP Bumping 6 UMC ChipPAC Amkor STATS UMC Web Based Solution UMC myumc UMC Virtual Fab UMC Real Fab 5. 5 Silicon Shuttle IP UMCJ 0.18 m 1P6M 6 Silicon Shuttle SRAM 90% TEG H90% 6 UMC UMCJ 0.13 m HDTV UMC IP DSP IP IP UMC IP UMC IP IP IP DAC ADC DDR-IF Analog SW UMC Gold IP Program 6 PCB PCB 1024Pin Flip Chip ASE SIP System in Packaging 72

2005 11 16 5 UMC Silicon Shuttle IP Verification I PE1 I PE2 I PE3 I PE4 A Real Life Example: I PE5 TEG 100% N MTP TEG 90% 1T SRAM a 1T SRAM c SRAM 100% SRAM SWL 100% F GII 100% SRAM 90%

18 um 1P6M H 90% 6 Working Model for SoC Solution An Example: 0.13 um HDTV UMC Manufacturing Customer DAC ADC DDR-IF PLL Analog SW etc.

7 UMC Silicon Shuttle IP Verification I PE1 I PE2 I PE3 I PE4 A Real Life Example: I PE5 TEG 100% N MTP TEG 90% 1T SRAM a 1T SRAM c SRAM 100% SRAM SWL 100% F GII 100% SRAM 90% F GII 90% 1T SRAM b Shuttle Passengers: I: MTP TEG1-5 N: MTP TEG H: 66XXXN 90% UMC: 1T-SRAM x 3 F: GII (100%/90%) UMCJ: SRAM etc. x um 1P6M H 90% 6 Working Model for SoC Solution An Example: 0.13 um HDTV UMC Manufacturing Customer DAC ADC DDR-IF PLL Analog SW etc. Customer s IP IP Partners Ultra926 project 7 UMC Ultra926 project UMC Multiple Transistors Vth Devices Models ARM IP Power Management Algorithms National Semiconductor IP Artisan Multi-Vth Multiple Supply Multiple Voltage (MSMV) Special Cells Libraries Synopsys Power Optimization Tool 73

8 ULTRA926 Project Collaboration System solution for power management IP, Power Management Algorithms IP Collaboration amongst industry leaders on low-power initiatives Libraries - Multi-Vth, Multiple Supply Multiple Voltage (MSMV), special cells Multiple Transistors with Vth Devices, models Power Optimization tool, Adaptive Voltage Scaling (AVS) Methodology Note: Trademarks & logos are owned by each individual company Adaptive Voltage Scaling (AVS) Methodology 6. UMC R&D 8 ITRS nm nm 193nm 90nm 65nm R&D 8 Continuous Efforts in R&D ITRS Lithography Roadmap CD (nm) Immersion?? DRAM half pitch ASIC/MPU half pitch ASIC physical gate length MPU physical gate length 157 EPL & EUV Year 74

2005 11 16 9 65nm 1P10M Cross-section 10 45 nm FinFET Device Structure Poly Poly Si Fin Si Fin (a) Single Fin FET (b)

1V 1.E-06 1.E-07 1.E-08 PMOS: 1.E-09 Id,sat = 560 ua/um Swing = 79 mv/dec 1.E-10 DIBL = 101 mv/v 1.E-11 Vd=0.

6 Gate Voltage, Vg-Vt (V) UMC 90nm->65nm->45nm Gate Dielectric: Ultra Thin Gate/High-K Material S/D Engineering: Raised

9 nm 1P10M Cross-section nm FinFET Device Structure Poly Poly Si Fin Si Fin (a) Single Fin FET (b) Multiple Fin FET 1.E-02 1.E-03 Vd=-1.0V Vd=1.0V 82.9 nm 11.4 nm 8.6 nm Drive Current, Id (A/um) 1.E-04 1.E-05 Vd=-0.1V 1.E-06 1.E-07 1.E-08 PMOS: 1.E-09 Id,sat = 560 ua/um Swing = 79 mv/dec 1.E-10 DIBL = 101 mv/v 1.E-11 Vd=0.1V Lg=30 nm NMOS: Id,sat = 692 ua/um Swing = 86 mv/dec DIBL = 122 mv/v BOX 1.E Gate Voltage, Vg-Vt (V) UMC 90nm->65nm->45nm Gate Dielectric: Ultra Thin Gate/High-K Material S/D Engineering: Raised S/D Device Structure: SOI/Strain Silicon/Fin FET Interconnect: Low-K Dielectric Material UMC 9 65nm 1P10M interconnect 2 interconnect 75

10 UMC 45nm Poly 7 UMC System Architecture Knowledge IP EDA 300mm UMC Pure Play Foundry IDM IP EDA Reference Design DFM 200mm 0.18 m 0.13 m 300mm 90nm 65nm 45nm UMC 300mm 100nm SoC Summary: Foundry s Solution for SoC Design 0.13um, 90nm Mixed Signal /RF E-Memories System Architecture Knowledge IP and Design Methodology SoC Process Platform World Class Manufacturing Test and Packaging Solutions 7 76

11 赤門マネジメントレビュー編集委員会編集長新宅純二郎編集委員阿部誠粕谷誠片平秀貴高橋伸夫藤本隆宏編集担当西田麻希赤門マネジメントレビュー 5 巻 2 号 2006 年 2 月 25 日発行編集東京大学大学院経済学研究科 ABAS/AMR 編集委員会発行特定非営利活動法人グローバルビジネスリサーチセンター理事長高橋伸夫東京都文京区本郷

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untitled ITRS2005 DFM STRJ : () 1 ITRS STRJ ITRS2005DFM STRJ DFM ITRS: International Technology Roadmap for Semiconductors STRJ: Semiconductor Technology Roadmap committee of Japan 2 ITRS STRJ 1990 1998 2000 2005