COINS 5 2.1

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1 COINS ( )

2 COINS COINS HIR VHDL HDL VHDL SPARK SPARK hir2c

3 RTL COINS HIR HIR LSI SPARK main while (5.3) (5.3) (5.3) ( ) case (5.7) SPARK ( )

4 LSI RTL 2 ( 1.1)( 1.2) 1.1: 1.2: RTL 1 HDL 2 Register Transfer Level 3

5 1.2 COINS [1] COINS COINS COINS 1.3 COINS COINS hir2c 3 C VHDL VHDL RTL RTL int if while 2 COINS HIR 3 SPARK HDL VHDL hir C 4

6 2 COINS COINS COmpiler INfraStructure COINS 2.1 COINS (front end) (back end) (source program) (intermediate code) (machine code) (lexical analyzer) (syntax analyzer) (semantic analyzer) (optimizer) (code generator) COINS ( 2.1) 2.1: COINS 5

7 (HIR) (LIR) (High-Level Intermediate Representation HIR) (Low-level intermediate representation LIR) Java Java Java 2 SSA 1 10 COINS LIR LIR LIR do-all SMP(symmetric multi-processor) SIMD SIMD(single-instruction multiple-data) [4] COINS [2] 1 Static Single Assignment form 6

8 2.2 HIR COINS HIR HIR C if HIR (High-level Intermediate Representation) HIR HIR C HIR C HIR HIR (symbol table) (HIR0.java Sym0.java) HIR HIR (2.2) 7

9 HIR //High-level Intermediate Representation. Program // Program definition node. SubpDefinition // Subprogram definition node. HirSeq // Sequence of definite number of HIR objects. HirList // List whose elements are HIR objects. Stmt LabeledStmt // Labeled statement. AssignStmt // Assignment statement. IfStmt // If-statement. JumpStmt // Jump (goto) statement (Jump unconditionally). LoopStmt // Loop statement. ReturnStmt // Return statement. SwitchStmt // Switch (case) statement. BlockStmt // Block representing a sequence of statements. ExpStmt // Expression treated as a statement. InfStmt // An information node (pragma, comment line, etc.) SetDataStmt // Statement to specify initial data. LabelDef // Label definition node. Exp // Expression ConstNode // Constant node SymNode // Symbol node VarNode // Variable name node. ElemNode // struct/union element name node SubpNode // Subprogram name node. LabelNode // Label reference node. TypeNode // Type name node. SubscriptedExp // Subscripted variable. PointedExp // Pointed object. QualifiedExp // Qualified variable. FunctionExp // Function call expression. PhiExp // Phi function used in SSA ExpListExp // Expression representing a list of expressions. NullNode // Null (no-operation) node 2.2: HIR 8

10 HIR, ( 1 2 n ) < >. HIR int fact( int p) /* fact0.c: Factorial function */ { if (p <= 1) return 1; else return p * fact(p - 1); } 2.3: 9

11 HIR (prog 1 <null 0 void> <nullnode 2> (subpdef 3 void <subp 4 <SUBP < int > false false int> fact> <null 0 void> (labeldst 5 void (list 6 <labeldef 7 _lab1>) (block 8 void file fact0.c line 2 (if 9 void file fact0.c line 4 (cmple 10 bool _XId1 <var 11 int p _XId2> <const 12 int 1>) (labeldst 13 int (list 14 <labeldef 15 _lab3>) (return 16 int file fact0.c line 5 <const 17 int 1>)) (labeldst 18 int (list 19 <labeldef 20 _lab4>) (return 21 int file fact0.c line 7 (mult 22 int _XId3 <var 23 int p _XId2> (call 24 int _XId4 (addr 25 <PTR <SUBP < int > false false int>> _XId5 <subp 26 <SUBP < int > false false int> fact>) (list 27 (sub 28 int _XId6 <var 29 int p _XId2> <const 30 int 1>)))))) (labeldst 31 void (list 32 <labeldef 33 _lab5>) <null 0 void>)))))) 2.4: HIR 10

12 HIR C OpenMp HIR HIR [3, 11] 11

13 3 VHDL SPARK 3.1 VHDL VHDL [12] CAD (Hardware Description Language:HDL) HDL HDL C HDL HDL HDL HDL VHDL Verilog-HDL VHDL Verilog-HDL 12

14 回路図手書き ( 紙ベース ) 標準ロジック CAD ツールの誕生設計量増加ネットリスト手書き ( 計算機ベース ) CADツールベンダーの誕生 ASIC CPLD 回路図エントリ ( 計算機ベース ) FPGA 合成ツールの誕生デバイスの歴史 HDL エントリ ( 計算機ベース ) 高速シュミレーション要求 C 言語エントリ ( 計算機ベース ) 3.1: (IEEE) HDL behavioral RTL(Register Transfer Level) Logic (SPARK) VHDL 13

15 3.1.3 HDL VHDL LSI (3.2) LSI 3.2: LSI ( ) 14

16 CPU DSP LSI LSI LSI RTL Verilog HDL VHDL RTL LSI RTL RTL HDL LSI LSI LSI LSI 15

LSI (3.2) RTL ( ) RTL RTL HDL LSI 3.1.4 VHDL VHDL 1.

17 LSI (3.2) RTL ( ) RTL RTL HDL LSI VHDL VHDL 1. ( ) 2. ( ) 3. ( ) 3.3: VHDL WORK VHDL STD IEEE VHDL 16

18 -- -- library IEEE; use IEEE.std_logic_1164.all; --IEEE use IEEE.std_logic_arith.all; -- ENTITY IS port( -- x: IN std_logic; y: IN std_logic; z: out std_logic); END ; ( ) ( ) (std logic ) ARCHITECTURE OF IS begin z <= x and y; end ; 17

3.2 SPARK SPARK [6, 5] ANSIC VHDL SPARK 3.4 SPARK 3.4: SPARK 3.2.1 SPARK 3.

19 3.2 SPARK SPARK [6, 5] ANSIC VHDL SPARK 3.4 SPARK 3.4: SPARK SPARK 3.5 C SPARK SP ARK hvbfile.c VHDL program int x; int add(int y){ int z; z = x+y; return z; } 3.5: 1 18

20 library IEEE; use IEEE.std logic 1164.all; use IEEE.std logic arith.all; use IEEE.std logic signed.all; library work; use work.spark pkg.all; IEEE SPARK SPARK ENTITY add IS port( y : IN wiredorint range to ; returnvar_ : OUT wiredorint range to ; -- global variables are x : INOUT wiredorint range to ; CLOCK : IN std_ logic ; RESET : IN std_ logic ; done : OUT std_ logic ); END add; main main main y port wiredorint return 19

21 return returnvar wiredorint x CLOCK RESET done CLOCK 1 RESET done ARCHITECTURE behav OF add IS PROCEDURE add ( y : IN wiredorint range to global variables are x : INOUT wiredorint range to ; ) IS signal z : wiredorint range to ; BEGIN z <= (x + y); returnvar_ <= z; END add; signal z : wiredorint range to ; BEGIN PROCESS BEGIN wait until CLOCK event and CLOCK = 1 ; z <= (x + y); returnvar_ <= z; END PROCESS; END behav; 20

22 PROCEDURE IF while PROCEDURE main 21

23 C COINS 2. C HIR 3. HIR VHDL 4. HIR VHDL int boolean if while hir2c hir2c HIR C HIR C hir2c hir2c C HIR HIR C HIR HIR C hir2c 22

24 hir2c AssociationList.java HIR Hir2C.java HirBaseToCImpl HirBaseToC.java HirBaseToCImpl HirBaseToCImpl.java KeyWords.java C LabelRef.java PrintDef.java 4.3 C HIR COINS HIR hir2c VHDL 4.1 COINS C ファイル HIR VHDL 変換ツール VHDL ファイル 4.1: 23

25 hir2c hir2c PrintDef String PrintDef HirBase2CImpl hir2c # define hir t short short # define hir XOR(a,b) (a) ˆ(b) library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_signed.all; CLOCK RESET returnvar done HIR HIR COINS HIR PROCEDURE main HIR main PROCESS 24

26 program int func1 (){... return 0; } int func2(){... return 0; } int func3(){ // main... return 0; } 4.2: main (+,-,*,/) hir2c KeyWord.java x + y; hir2c hir ADD(x, y) KeyWord.java hir ADD + +(x, y) 1 (<,, =,,>) (< =) if if boolean If else HIR if VHDL if else 1 VHDL == = 25

27 if signal st0_3 : wiredorboolean ;//st_03 BEGIN st0_3 <= (x = 0);//(X==0) if st0_3 then returnvar_ <= 0; else returnvar_ <= 1; end if; END branch; 4.3: while while if VHDL while loop end loop while BEGIN while st0_10 <= (i=0); if st0_10 then loop//while i <= (i+1); end loop// returnvar_ <= 0; END while1; 4.4: while 26

28 5 5.1 COINS SPARK if while 5.2 VHDL (5.3) (5.4) (5.5) (5.6) Xilinx [7] ISE10.1 test int a, b,c int main() { int a, b,c,d,e,f; a = 3; b = a+5; c = b-2; d = c*e; f = d/2; return (0); } 5.1: 27

29 vhdl // ENTITY main IS port( a : INOUT wiredorint range to ; b : INOUT wiredorint range to ; c : INOUT wiredorint range to ; returnvar_ : OUT wiredorint range to ; CLOCK : IN std_logic ; RESET : IN std_logic ; done : OUT std_logic ); END main; ARCHITECTURE behav OF main IS signal d : wiredorint range to ; signal e : wiredorint range to ; signal f : wiredorint range to ; BEGIN PROCESS BEGIN wait until CLOCK event and CLOCK = 1 ; a <= 3; b <= (a+5); c <= (b-2); d <= (c*e); f <= (d/2); returnvar_ <= 0; END PROCESS; END behav; 5.2: 28

30 5.3: 5.4: (5.3) 1 29

31 5.5: (5.3) 2 30

32 5.6: (5.3) ( ) 31

33 5.3 SPARK C2VHDL SPARK VHDL VHDL for SPARK case if case VHDL RTL C RTL case SPARK case (5.7) (5.8) if VHDL csae if case if hir2c HIR if case case (x) HIR case if ( 0) case if case case int x; int sw(){ switch(x){ case 0: return 0; case 1: return 1; break; } } 5.7: case 32

34 .... PROCEDURE sw ( x : INOUT wiredorint range to ; ) IS signal st0_3 : wiredorboolean ; signal st1_3 : wiredorboolean ; BEGIN st0_3 <= (x = 1); if st0_3 then returnvar_ <= 0; else st1_3 <= (x = 2); if st1_3 then returnvar_ <= 1; end if; END sw; : (5.7) SPARK ( ) 33

35 6 [10] 10 CAD CAD [9] C VHDL C C [8] C 34

36 7 COINS C2VHDL VHDL 20 COINS COINS 35

37 36

38 [1] COINS-Project. Coins homepage. [2].., [3] COINS Project. COINS HIR, org/coinsdoc/hir/hir-frame.html. [4].., [5] University of California. Spark homepage. [6] Gupta Sumit, Gupta Rajesh, Dutt Nikil, and Nicolau Alexandru. SPARK:: A Parallelizing Approach to the High-Level. Kluwer Academic Publishers, [7] Xilinx. Xilinx homepage. [8],,. C vhdl., [9],,,. C., [10]. : cyber., pp , [11],. hir (21 coins 8)., Vol. 47, No. 11, pp , [12],. VHDL.. 37

if clear = 1 then Q <= " "; elsif we = 1 then Q <= D; end rtl; regs.vhdl clk 0 1 rst clear we Write Enable we 1 we 0 if clk 1 Q if rst =

if clear = 1 then Q <= ; elsif we = 1 then Q <= D; end rtl; regs.vhdl clk 0 1 rst clear we Write Enable we 1 we 0 if clk 1 Q if rst = VHDL 2 1 VHDL 1 VHDL FPGA VHDL 2 HDL VHDL 2.1 D 1 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; regs.vhdl entity regs is clk, rst : in std_logic; clear : in std_logic; we