Z80 Z80 Z80 Z80 ROM RAM I/O 8255 8251 Z80PIO Z80CTC Z80SIO R C L Tr OP TTL
MCB Z MC Z
Z80 Z80 TMPZ84015BF KL5C8012 64180 H8 H8 PIC Microchip Technology PIC
Z80 F A A' ALU B D H C E L IX IY SP PC C E L IR
Z80 A A F F B C D E H L BCDEHL IX IY SP CALL PC I R
Z80 A15 A14 A13 A12 A11 A10 A9 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 A8 WR RD M1 MREQ IORQ RFSH HALT WAIT INT NMI RESET BUSRQ BUSAK V GND CPU CPU Z80 CPU
Z80CPU A0-A15 H D7-D0 H M1 L OP OPOP MERQ L IORQ L
Z80CPU RD L CPU WR L CPU RFSH L HALT L CPUHALT NOP
Z80CPU WAIT L Z80CPU CPU INT L FF) BUSRQ NMI INT T NMI CPUH
Z80CPU RESET L RESETCPU IH RH BUSRQ L CPU BUSAK L CPU TTL
CPU T1 T2 T3 T4 T1 T2 T3 T1 T2 T3 MI M2 M3 (OP) () () CPU
OP M1 T1 T2 T3 T4 T1 A0A15 MREQ RD WAIT M1 DB0DB7 RFSH OP(M1)
OP M1 T1 T2 TW TW T3 T4 A0A15 MREQ RD DB0DB M1 WAIT RFSH OP
T1 T2 T3 T1 T2 T3 A0A15 MREQ RD WR (D0D7) WAIT 4-3
T1 T2 TW TW T3 T1 A0A15 MREQ RD (D0D7) WR (D0D7) WAIT 4-3A
A0A7 T1 T2 TW T3 T1 IORQ RD WAIT WR 4-4
T1 T2 TW TW T3 A0A7 IORQ RD WAIT WR 4-4A
M T Tx Tx Tx T1 BUSRQ BUSAK A0A15 D0D7 MREQRD WRIORQ RFSH 4-5 /
M T M1 T1 T2 TW TW* T3 INT A0A15 M1 MREQ IORQ WAIT RD 4-6 /
NM1 M T T1 T1 T2 T3 T4 A0A15 M1 MREQ RD RFSH 4-7
HALT INT or NM1 M1 M1 T4 T1 T2 T4 T1 T3 M1 T2 4-8
M T T1 T2 TW TW TW T3 M1 IORQ IORQ WAIT 1 4-6B 1/
Z80 LD ddnn dd <= nn OP dd dd BC 00 DE 01 HL 10 SP 11 HEX 01+ C Z P/V S N H M T
Z80 memory register direct addressing register indirect addressing immediate addressing index addressing relative addressing bit addressing
Z80
OP OP LD A, 80H A <= 80H
OP HL LD HL nn HL nn LD HL H
OP RST H H RST H H RST H H RST H H
OP OP OP JR e PC PC+e JRe
OP LD A nn A nn LD A H HA
OP OP OP LD A IX A IX A
OP OP LD B C B C
OP OP ADD A B A A+B EX DE HL DE HL
OP LD A, HL A HL) HLA
Z80 CPU BIT A A F RES HL SET IX HL
1. ADD A, B A <= A + B 2. LD A, (0100H) A <= (0100H)
Z80 data transfer instruction ) ( operation instruction ) ( branch instruction ) ( subroutine call / returninstruction ) ( input / output instruction ) CPU( CPU control instruction )
LD LD LD nn nn LD nn) (nn) LD nn (nn) LD A A LD A A ABCDEHL n nn BC,DEHL PUSH SP H SPL POP L SP H SP
ADD ADD A,n A A+n ADC ADC A,n A A n + CY SUB SUB s A A - s SBC SBC s A A s - CY AND AND s A A s XOR XOR s A A s OR OR s A A s CP CP s A - s ( INC INC r r DEC DEC r r r 1
JP nn JP ccnn PC nn if cc = true, PC <= nn cc NZ Z= Z Z= NC CY MSB C CY MSB PO P= PE P P S MSB M S MSB
CALL nn PC PC<=nn SP-1)PCH SP-2PCL PCnn RET PC PCLSPPCHSPSPSP+1 CALL ccnn RET cc cccall ccret NZ Z= Z Z= NC CY MSB C CY MSB PO P= PE P P S MSB M S MSB
IN A, (n) A IN r, ( C ) r <= ( C ) C OUT (n)a A OUT C)A CA OTIROUTDOTDRINIINIRINDINDR
CPU NOP HALT DI EI IM0 IM1 IM A H I
CY RLC CY SLA CY RRC CY SRA CY RL CY SRL CY RR B3 B0 B7 B B3 B0 B3 B0 B7 B B3 B0 Acc HL) RLD Acc HL) RRD
CPI ; CPIR ; A(HL) HL <= HL+1 BC <= BC++1 HL)A A(HL) HL <= HL+1 BC <= BC++1 HL)A BC CPD A=(HL), HL <= HL-1, BC <= BC-1 HL)A CPDR ; A=(HL), HL <= HL-1, BC <= BC-1 HL)A BC
EXX BC BC DE DE HL HL EX DE, HL DE HL EX AF, AF AF AF EX SP), HL L SP) H SP+1) EX SP), IX IXL SP) IXH SP+1) EX SP) IY IYL SP) IYH SP+1)
RST 0 H C7H RST 8 H CFH RST 16 H D7H RST 24 H DFH RST 32 H E7h RST 40 H EFH RST 48 H F7H RST 56 H FFH
DAA A CPL A NEG CCF SCF AA A CY
LDI (DE) <= (HL), DE <= DE+1, HL <= HL+1, BC <= BC-1 HL)DE LDIR (DE) <= (HL), DE <= DE+1, HL <= HL+1, BC <= BC-1 HL)DEBC LDD (DE) <= (HL), DE <= DE1, HL <= HL1, BC <= BC1 HL)DE LDDR (DE) <= (HL), DE <= DE1, HL <= HL1, BC <= BC1 HL)DEBC
Σ
CPU
MSB LSB S Z X H X P/V N CY S MSB=1 Z X H X P/V N ADD SUB CY MSB
START CALL CALL CALL CALL CALL CALL N START START RETI START RETI CALL START START N RETI RETI
Z80 INT Z80 CPU Vcc I/O I/O I/O I/O4 06H 00H 02H 04H IEI IEO IEI IEO IEI IEO IEI IEO I H H H H L L L L L 0000H IO2 H I IO2 H ;PIO MODO 0 2800H 00H ORG 0000H 2802H 30H LD SP, 0000H 00H 40H IM 2 2804H 00H LD A, 28H 50H LD I, A 3000H 4000H 5000H FFFFH LD A, 00001111B OUT (PIOCON), A LD A,00H OUT (PIOCON),A LD A, 1000111B ; OUT (PIOCON), A
Z80 Vcc H H H H H IEI IEO IEI IEO IEI IEO IEI IEO Vcc H H H L L IEI IEO IEI IEO IEI IEO IEI IEO Vcc H H L L L IEI IEO IEI IEO IEI IEO IEI IEO Vcc H H H L L IEI IEO RETI IEI IEO IEI IEO RETI Vcc H H H H IEI IEO IEI IEO RETI IEI IEO H RETI
16 Add BUS Data BUS 8 13 Control BUS CPU ROM RAM I/O1 I/O2 I/O i8255 Z80PIO CPU ROM RAM I/O INPUT/OUTPUT CPU etc
CPU CPU ON CPU
IC Read write memory RWM read only memory ROM
IC IC RAM RAM random access memory PROM programmable ROM ROM read only memory SAM sequential access memory EPROM erasable PROM DRAM dynamic RAM SRAM static RAM EEPROM electrically erasable PROM EPROM ROM CCD charge coupled device)
Kbit 4 Kbit KB Kbit KB Mbit 131KB = Gbit MB
K D7 D0 Bit bit bit
ROM KB H 1FFFH 2764 RAM KB H FFFH 6264
i i C
D7 PA7 A D0 PA0 PC7 CS RD WR PC4 PC3 PC0 PB7 A1 A0 B RESET PB0
i CPU CPU A A PA A PA-PA7 PC4-PC7 RD PC-PC WR A1 A0 RESET PB-PB CS
i PA PC PC PB PAPA PC PB PC PB PA A CPC7-PC3
i D6D5 D6D5 D6D5X A OUTPUT INPUT C B OUTPUT INPUT A,B A,B A B C D7 D6 D5 D4 D3 D2 D1 D0 OUTPUT INPUT
i C D3 D2 D1 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 H") L") D7 D6 D5 D4 D3 D2 D1 D0
Z80PIO Z80PIO
Z80PIO
PIO D7 D6 D5 D4 D3 D2 D1 D0 M1 M0 X X 1 1 1 1 NO YES D7 D6 D5 D4 D3 D2 D1 D0 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 D7 D6 D5 D4 D3 D2 D1 D0 EI A/O H/L MF 0 1 1 1 NO YES D7 D6 D5 D4 D3 D2 D1 D0 MB7 MB6 MB5 MB4 MB3 MB2 MB1 MB0 NO YES D7 D6 D5 D4 D3 D2 D1 D0 V7 V6 V5 V4 V3 V2 V1 V0 Z80PIO D0
i
(transmitter data (receiver data (data set read) data terminal ready) clear to send) request to send) TxE (transmitter empty) (transmitter ready) xe=1 RxRDY(receiver ready) TxC (transmitter clock) receiver clock)
Z80CTC
Z80SIO
PNPNPN
TTL
OP
OP
OP
OP
OP
OP
OP
OP
FET
OR,NOR)
(AND NAND)
(BUFFER NOR)
ONH
i
LED