Lattice MachXO Lattice Lattice MachXO_design_guide_rev2.2.ppt Page: 2
1. MachXO 1-1. 1-2. PLL 1-3. JTAG 1-4. 2. MachXO I/O Bank I/O 2-1. I/O BANK 2-2. I/O I/F 2-3. I/F 2-4 I/F 2-5. 2-6. LVDS I/F 2-7. I/F 3. MachXO 3-1. MachXO 3-2. SRAM 3-3. ispjtag 3-4. JTAG (XO ) 3-5. JTAG () 3-6. 3-7. 4. 4-1. 4-2. 5. 5-1. 6. 6-1. I/O Type Pull 6-2. MachXO_design_guide_rev2.2.ppt Page: 3
MachXO MachXO_design_guide_rev2.2.ppt Page: 4
1-1 Vcc 1.2V/1.8V/2.5V/3.3V E 1.2VC 1.8V/2.5V/3.3V Vccaux 3.3V 3.3V Vccio 1.2V/1.5V/1.8V/2.5V/ 3.3V Bank 1.2V,1.5V,1.8V,2.5V,3.3V Vccio Vcc Vcc Vccio 2.5V 2.5V Vcc Vccaux Vccio3.3V 3.3V MachXO_design_guide_rev2.2.ppt Page: 5
1-1 Power Up Vccio Vcc Vccaux Vcc,Vccaux VCCIO JTAG JTAG VCCIO MachXO256 Bank1 MachXO640 Bank2 MachXO1200 Bank5 MachXO2280 Bank5 E VCC = 1.2V)(VCC = 1.8 or 2.5 or 3.3V) VCC = 3.3V MachXO_design_guide_rev2.2.ppt Page: 6
MachXO_design_guide_rev2.2.ppt Page: 7 1-1
1-1 (1) Vccaux=3.3V (2) Vccaux=3.3V 2.5V Vcc=2.5V 2.5V 1.71V Vccio=1.8V 1.14V Vcc,Vccio=1.2V Vcc VccauxVccaux 2.5V Vcc MinimumVccio Vcc Vccaux V =3.3V Vcc Vccaux (Vccio ) MachXO_design_guide_rev2.2.ppt Page: 8
1-2 PLL PLL [LOC][num]_PLL[T, C]_IN [LOC][num]_PLL[T, C]_FB PCLK[n]_[1:0] PLL PLL I/O 1200,2280 PLL PLL I/O 1200,2280 Global I/O MachXO_design_guide_rev2.2.ppt Page: 9
1-2 PLL PLL MachXO_design_guide_rev2.2.ppt Page: 10
1-2 PLL PLL PLL PLLT(True),C(Complemen) T C UserI/O n_clki n_clki n_clki PLL PLL n_clki Tco PLL Tco CLKI PLL PLL Secondury MachXO_design_guide_rev2.2.ppt Page: 11
1-3 JTAG TMS TCK TDI TDO TAP TAP 3-3. ispjtag MachXO_design_guide_rev2.2.ppt Page: 12
1-4 SLEEPN TSALL GSRN ActiveLow 5k-10K Global RESETI/O I/O Global RESET OK. GSRN Distributed-RamFF GSRN GSRN GSRN Place & Route Report Device utilization summary RST Signal RST is selected as Global Set/Reset MachXO_design_guide_rev2.2.ppt Page: 13
MachXO I/O Bank I/O MachXO_design_guide_rev2.2.ppt Page: 14
2-11 I/O Bank LatticeMachXO Bank MachXO2280 MachXO1200 MachXO256,640 PCI MachXO1200,2280 TopBank MachXO256,640 MachXO1200,2280 Bank MachXO1200,2280 50 LVDS LVDS LVPECL MachXO640 MachXO256 Mach256,640 LVCMOSBuffer Emulate MachXO_design_guide_rev2.2.ppt Page: 15
2-2 I/O I/O I/F MaxhXO256 MachXO640 MachXO1200 MachXO2280 I/O LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 LVDS 1 2 LVPECL 1 2 BLVDS 1 2 RSDS 1 2 LVDS 1 2 LVPECL 1 2 BLVDS 1 2 RSDS 1 2 PCI33 LVDS 1 LVPECL 1 BLVDS 1 RSDS 1 PCI33 LVDS 1 LVPECL 1 BLVDS 1 RSDS 1 Bank Bank Bank Bank Bank Bank PCI PCI33 PCI33 PCI33 (TopBank Bank Bank PCI33 (TopBank Emulate Bank Bank Bank Bank LVDS No No (LEFT,RIGTHBank ) (LEFT,RIGTHBank ) I/FLVCMOS Emulate MachXO_design_guide_rev2.2.ppt Page: 16
2-3 I/F I/F MachXO Mixed Voltage LVCMOS18,LVCMOS15,PCI VCCIO I/F I/F DesignPlanner LVCMOS18,LVCMOS15,PCI Vccio 5V MachXO_design_guide_rev2.2.ppt Page: 17
2-4 I/F I/F I/F Vccio Vccio I/F MachXO_design_guide_rev2.2.ppt Page: 18
2-5 MachXO DataSheet sysio Single-Ended DC Electrical Characteristics MachXO I/F MachXO I/O The average DC current drawn by I/Os between GND connections, or between the last GND in an I/O bank and the end of an I/O bank, as shown in the logic signal connections table shall not exceed n * 8mA, where n is the number of I/Os between bank GND connections or between the last GND in a bank and the end of a bank. Bank GND I/O I/O Bank GND I/O Bank I/O ( ) 8mA MachXO640 256fpBGA I/O GNDI/O8mA 64mAI/O64mA BallNo.J4 I/O 16mA 7 48mA MachXO Datasheet MachXO_design_guide_rev2.2.ppt Page: 19
2-6 LVDS I/F LVDS (MachXO1200,2280 Top,Bottom,Right,LeftLVDS I/O PL2A,PL2BT True,C Complementary LVDS 100 LVDS Pull-up Floating FAE 100 Design Planner LVDS25 LVDS25E MachXO Device MachXO_design_guide_rev2.2.ppt Page: 20
2-6 LVDS I/F LVDS LVDS LVDSLVDS 2 LVDSMachXO1200,2280 LEFT,Right 50% Differencial LVDS I/O I/O LVDS VCCIO 2.5V LVDS 2.5V DesignPlanner I/O Type LVDS25 LVDSEmulated LVDS) Top,Botto,Left,RightLVDS I/OLVDS LVDS VCCIO 2.5V LVDS 2.5V DesignPlanner I/O Type LVDS25E 8mA MachXO_design_guide_rev2.2.ppt Page: 21
2-6 LVDS I/F LVDS LVDS LVDS LVDS LVDS MachXO_design_guide_rev2.2.ppt Page: 22
2-7 I/F BLVDS MachXO_design_guide_rev2.2.ppt Page: 23
2-7 I/F LVPECL RSDS MachXO_design_guide_rev2.2.ppt Page: 24
2-8 ON ON I/O MachXO ON VCC=VCCIO=VCCAUX) I/O ON I/O *1 DONE High) Hign LowHigh (1k ) ON Low I/OPull-Down I/O FF Reset PowerOnResetLow High MachXO_design_guide_rev2.2.ppt Page: 25
MachXO MachXO_design_guide_rev2.2.ppt Page: 26
3-1 MachXO Flash Flash Flash SRAM SRAM () ispjtag ispjtag SRAM Flash Flash MachXO_design_guide_rev2.2.ppt Page: 27
3-22 SRAM MachXO_design_guide_rev2.2.ppt Page: 28
3-3 ispjtag Vccio 3.3V 22K R 110K 1.8V 12K R 60K MachXO_design_guide_rev2.2.ppt Page: 29
3-44 JTAG (XO ) TCK Programming TCK / MachXO VCCIO JTAG MachXO256 Bank1 MachXO640 Bank2 MachXO1200 Bank5 MachXO2280 Bank5 MachXO_design_guide_rev2.2.ppt Page: 30
MachXO_design_guide_rev2.2.ppt Page: 31 (R) (N) 0.75K R 20K/N 5 2.2K-4.7K JTAGXO Vccio JTAG JTAG JTAG 3.3V 1.2V 3.3V TDO 1.2V TDI I/F3.3V JTAG TCK Programming 3-5 JTAG JTAG ( ) MachXO VCCIO JTAG MachXO256 Bank1 MachXO640 Bank2 MachXO1200 Bank5 MachXO2280 Bank5
3-6 Start POR MachXO_design_guide_rev2.2.ppt Page: 32
3-7 MachXO_design_guide_rev2.2.ppt Page: 33
MachXO_design_guide_rev2.2.ppt Page: 34
4-1 MachXO C (1.8/2.5/3.3V ) SLEEPN Low SLEEPNLow 400ns SLEEPNHigh SLEEPN <400ns MachXO256 400ns MachXO640 600ns MachXO1200 800ns MachXO2280 1000ns MachXO_design_guide_rev2.2.ppt Page: 35
4-2 I/O MachXO_design_guide_rev2.2.ppt Page: 36
MachXO_design_guide_rev2.2.ppt Page: 37
5-1 100TQFP 256 640 1200 2280 640 1200 256 640 100TQFP100csBGA 256 78I/O 640 74I/O I/O 4 640Vccio GNDio 2 256 640 640 Vccio GNDio MachXO_design_guide_rev2.2.ppt Page: 38
5-1 256fpBGA 640 1200,2280 I/O NC( ) 256fpBGA 1200,2280 640 NC NC MachXO_design_guide_rev2.2.ppt Page: 39
MachXO_design_guide_rev2.2.ppt Page: 40
6-1 I/O Type Pull Pull MachXO I/O Type LVCMOS2.5 I/O IF LVCMOS2.5 PULLMODE PullUp PullUp PullDown PullOff BusKeeper MachXO_design_guide_rev2.2.ppt Page: 41
6-2 DRIVE 12mA N/A I/O I/F 2-4 I/F SLEWRATE FAST FAST SLOW 2 OPENDRAIN OFF OUTLOAD 0pF Tco 0~100pF MachXO_design_guide_rev2.2.ppt Page: 42
Revision History MachXO_design_guide_rev2.2.ppt Page: 43