1. Internet of Things (IoT) mw µw [1] LSI (NTC) [2][3] LSI 2 [3] CMOS ( 0.2V ) CMOS SOI(Silicon On Insulater) SOI (LEAP) Silicon on Thin BOX MOSFET (S
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- けんじ おえづか
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1 SOTB MOSFET V850 1,a) 1,b) 2,c) 1,d) , FD-SOI Silicon on Thin BOX(SOTB) MOSFET SOTB MOS-FET V850Estar 89.7% :Break Even Time 2.177ms 19.30ms 229.3µs SPICE SOTB A Research of Dynamic Body Bias Control on Micro Controller V850 Using SOTB MOSFET Hayate Okuhara 1,a) Kuniaki Kitamori 1,b) Kimiyoshi Usami 2,c) Hideharu Amano 1,d) Received: May 19, 2015, Accepted: November 6, 2015 Abstract: Silicon on Thin BOX (SOTB) MOS-FET is a low power FD-SOI device than can control the leakage power and operational speed by scaling body bias voltage. A low power micro-controller using the SOTB technology can save the energy by giving a large reverse bias to reduce the leakage power in the sleep mode, and waking up when it is requested. The paper makes the fundamental issues clear for using the above bias control method based on the measurement of a micro-controller V850 Estar. Real chip evaluation appears that 89.7% of leakage can be saved in the sleep mode. Break Even Time (BET) on which the leakage reduction overcomes power overhead of body bias control is 2.177ms in the core macro and is 19.30ms in the memory macro. Also, the response delay of body bias control is at most 229.3µs. These evaluation results must be concerned in the bias control. Finally, a leak monitor which can detect the wake up from the sleep mode is proposed. The target active body bias voltage to be detected can be given from outside the chip according to the setting voltage given by the proposed expression with almost no error to the SPICE simulation results. Keywords: Low power design, Dynamic body bias control, SOTB, micro controller 1 Hiyoshi, Kohokuku, Kanagawa , Japan 2 Toyosu, Koutouku, Tokyo 3-7-5, Japan a) hayate@am.ics.keio.ac.jp b) kitamori@am.ics.keio.ac.jp c) usami@shibaura-it.ac.jp d) hunga@am.ics.keio.ac.jp c 2016 Information Processing Society of Japan 1
2 1. Internet of Things (IoT) mw µw [1] LSI (NTC) [2][3] LSI 2 [3] CMOS ( 0.2V ) CMOS SOI(Silicon On Insulater) SOI (LEAP) Silicon on Thin BOX MOSFET (SOTB MOS- FET) [4] BOX 10nm [5][6][7] ( ) (BET:Break Even Time)[8] BET [9] SOTB V850 [10] BET 2. SOTB LSI 2.1 SOTB CMOSFET SOTB MOSFET FD-SOI(Fully Depleted-Sillicon On Insulater) 1 10nm BOX SOTB MOSFET BOX (SCE) (V DD ) BOX pn- CMOS BOX 2.2 MOSFET (V T H ) ( ) V T H MOSFET nmosfet V sn V BN pmosfet c 2016 Information Processing Society of Japan 2
3 VBP Drain Gate Source Gate Drain VBN STI N-well P-well Deep n-well 1 SOTB MOSFET P-sub V sp V BP V sn > V BN, (1) V sp < V BP, (2) MOS FET V T H (I leak ) V sn < V BN, (3) V sp > V BP, (4) V T H 2.3 SOI [5] SOTB MOSFET [11] [12] FPGA [6] [7] FPGA [9] [13][14] BET V850E-Star 32bit V850E-Star[10] SOTB 65nm 2 1 V850 RISC CPU K 128-Kbyte CPU nmos pmos V BN V BP V DD nmos pmos V BNM V BP M V DDM CMOS nmos pmos V BP + V BN = V DD (5) V BP M + V BNM = V DDM (6) V BN V BNM V MiBench[15] c 2016 Information Processing Society of Japan 3
4 情報処理学会論文誌 表 1 対象 V850 の実装諸元 process 65-nm FD-SOI (LEAP SOTB) logic gates 46.2K local memory 128K + 128K Logic Synthesis Design Compiler Routing of Layout IC Compiler Package 208PIN QFP Standard Voltage 0.4V Maximum operational freaqency[mhz] Vol.57 No (Feb. 2016) 50 VBNM=0.2V VDD =0.4V VDDM=0.4V 40 VBNM=0.1 VBNM=0 VBNM=-0.1 VBNM=-0.2 VBNM= VBNM= VBN[V] 0.2 図 3 実チップ評価による V850 の最高動作周波数 [MHz] 図 2 V850 のチップ写真 表 2 V850 の電圧定義 V BP CPU コア pmos ボディ電圧 V BN CPU コア nmos ボディ電圧 VDD CPU コア電源電圧 V BP M メモリ pmos ボディ電圧 V BN M メモリ nmos ボディ電圧 VDDM メモリ電源電圧 Standby Power[W] 10 2 MEM 10 4 CORE VDD =0.4V VDDM=0.4V VBN VBNM[V] 図 4 V850 で消費されるリーク電流による消費電力 [W] 加している ここでボディバイアスが待機時にゼロバイア プログラム Dijkstra を動作させた際の最高動作周波数のボ スのままであると仮定すると コアに流れるリーク電流 ディバイアス特性を示す Dijkstra は メモリのアクセス は mA でメモリに流れるリーク電流は 4.623mA で が多いアプリケーションであるが 演算が多い離散コサイ ある 従って これらのリーク電流を足し合わせて電源電 ン変換のアプリケーションでも最大動作周波数がほぼ変わ 圧を掛ければリーク電流による消費電力はチップ全体に らなかったことから 今回の評価は Dijkstra を用いた結果 対して 2.018mW である これに対して V BN = 1.1V のみを示す および V BN M = 1.1V のリバースバイアス時は コア VDD および VDDM は 0.4V とし 横軸をコアのボディバ に流れるリーク電流が 8.036µA で メモリに流れるリー イアスの電圧 V BN 縦軸を最高動作周波数とした パラ ク電流が 43.89µA である 従ってリーク電流による消費 メータとして メモリのボディバイアス電圧 V BN M を変 電力は 20.77µW となり ゼロバイアス時の 10.3%である 化させている ボディバイアスをフォワード方向に上昇さ すなわち 本例において動作時のボディバイアスをゼロ せると 最高動作周波数が向上している V BN =-0.4V で バイアスとし 待機時に動的に V BN = 1.1V および V BN M =-0.4V のとき 最高動作周波数は 22MHz である V BN M = 1.1V に切り替えた場合 待機時間が十分長け のに対して V BN = 0.2V V BN M = 0.2V に変更した れば 待機時の消費電力は約 89.7%削減される ときの最高動作周波数は 47MHz まで向上した 3.4 温度特性 3.3 リーク電流 以上 プロセッサで問題となる動作周波数と消費電力に 図 4 にリーク電流による消費電力を示す 横軸が V BN ついて調べたが 命令の実行時に生じる消費電力によって および V BN M 縦軸がリーク電流による消費電力 (PST ) 発生する発熱が影響を与える場合がある [16] 発熱により である VDD および VDDM は 0.4V とした リーク電流 基板の温度が上昇する場合 閾値電圧が変動し 動作時に はチップのクロックを全て停止しリセットした状態で流 与えなければならないボディバイアスの値が変化する 動 れる電流を取得した チップのボディバイアスがフォワー 作時に与えるボディバイアスが変化すると その変化に追 ド方向にバイアスされると リーク電流は指数関数的に増 従して適切なボディバイアスを与える必要が生じる そこ c 2016 Information Processing Society of Japan 4
5 i VBN VBP Thermal of the V850[ ] Operating Time[s] VBN=0.4V VBN=0.2 VBN=0 VBN=-0.2 V DD =0.4V V DDM =0.4V V850 [ C] A chip is sleep. BET Reverse Bias Time 6 Operations are done. Wake up time Operational Bias MiBench[15] Dijkstra 5 V DD V DDM 0.4V 20MHz V850Estar 4. 6 i V BN V BP i V DD i Chip VBP VBN 4.1 Break Even Time MOSFET V BP V BP M V BN V BNM (Overhead) Break Even Time (BET) Overhead = BET 0 i leakgain (t)dt (7) t i leakgain t = 0 7 V BN V BNM -1.1V BET 8 BET 27 C 0.2V BET 3.903ms BET -0.3V BET 19.30ms msec 20msec BET 0.2V c 2016 Information Processing Society of Japan 5
6 7 8 Energy of Overhead [µj] for Body Biasing CORE MEM VBN VBNM at Operational state [V] (Stand by state : VBN=-1.1V VBNM =-1.1V) [µj] Break Even Time[s] CORE MEM MEM+CORE V DD =0.4V V DDM =0.4V VBN VBNM at Operational state [V] (Stand by state : VBN=-1.1V VBNM =-1.1V) Break Even Time[s] BET ms -0.3V BET 2.177ms BET -0.3V 3.962ms BET 4.2 V850 3 [µs] MEM CORE V BP V BP M sleep wake up V BN V BNM sleep wake up LM2904DR 1.1µF 0.4V 10% 90% ( ) 219.7µs ( ) 229.3µs V BNM 118.5µs 229.3µs [17][18] [17] SOTB pn [18] SOTB SOTB c 2016 Information Processing Society of Japan 6
7 V DD In a target macro : MEM, CORE VBP M3 M5 VEN V DD VOUT DOUT M1 M4 M6 VGND VREF Vsbn M2 VEN Vsbn M7 Put outside a taget macro Detection Part Amplifier 9 CMOS (VBP ) [14] 9 Detection Part Differential amplifier M1 V BP M1 V GND 0 V BP M1 M1 V GND V GND V REF 10 HSPICE V DD = 0.4V V BP 0.5V V BP = 1.5V V REF V DD /2 0.17V V sbn pmos V BP 1.5V 0.5V V GND V REF DOUT V BN V BP 5.2 OUTPUT[V] 0.4V Standby Operation Standby Operation V 1.5V 1.5V 0.5V 0.5V 0.5V VEN VBP 0.2V 0.2V 0.2V VGND 0.4V 0.4V 0.4V Time [s] 0.4V 0.4V (HSPICE ) VOUT DOUT V REF CMOS V REF V sbn V sbn V GND V REF M1 M2 V BP V sbn M1 M2 I sub = I off 10 Vgs+η(V ds V DD ) kγ V sb S {1 exp( V ds )}(8) v T [19] I off V DD S k γ η DIBL v T M1 M2 M1 M2 V gs 0 c 2016 Information Processing Society of Japan 7
8 I offn 10 {ηn(v GND V DD ) kγnv sbn } V GND Sn {1 exp( )} (9) v T { ηp(v GND) kγpv bsp } = I offp 10 Sp {1 exp( V DD + V GND )} v T M1 pmos p M2 nmos n pmos (V bsp ) V BP target V REF = V GND = V DD /2 V OUT V sbn V sbn = S ( n I offn log 10 η nv DD k γn I offp 2S n η pv DD 2 + k γp (V BP target V DD )) + S p (10) (11) SPICE 11 (a) (b) pmos SPICE η p = η n = K γn = 0.17 K γp = I off SPICE (11) V sbn SPICE V sbn 12 V sbn V bsn M1 V bsn SPICE 13.78mV(V BP target = 1.2V) V BP target = 0.3V 1.797mV V BP V bsn M1 V BP target V bsn (25 C Threshold Voltage[V] nmosfet: y= x pmosfet: y= x Vds[V] (a) Threshold Voltage[V] nmosfet: y=0.17x pmosfet: y=0.1223x Reverse Body Bias[V] (11) (a)v T H vsv ds (b)v T H vs Reverse Body Bias Vbsn (-Vsbn)[V] VDD=0.4V VGND=0.2V : Equation : SPICE VBPtarget[V] (11) V bsn HSPICE V bsn V BP target 0.5V V DD 0.4V V BP V bsn V bsn 3 V sbn C(T ) (11) V bsn = S n k γn ( log 10 I offn I offp η nv DD 2S n (11) + η pv DD 2 + k γp (V BP target V DD )) + C(T ) S p V bsn 13 C(T ) C(T ) = T T T T C SPICE mV (b) c 2016 Information Processing Society of Japan 8
9 14 13 Dynamic power [nw] Vbsn(T)-Vbsn(25: ) VGND=VDD/2 VBPtarget=0.5V VDD=0.4V Temperature[ ] V bsn [V] VGND=VDD/2 VBP= V VDD=0.4V Frequency of VBP [khz] [nw] BET 19.30ms BET 2.177ms BET 3.962ms BET ms BET JSPS (S) V BP 1kHz 10kHz 1ms 100µs 14 43nW 6. V850 V DD (0.4V) 22MHz 47MHz 89.7% 229.3µs BET [1] Low-Power Electronics Association & Project.: THE 4th.REPORT Ultra Low Voltage Device Project for Low-Carbon Society, [2] Ronald G. Dreslinski, et. al.: Reclaiming Moore s Law Through Energy Efficient Integrated Circuits, Proceedings of the IEEE, pp (2010). [3] David Fick, et. al.: Centip3De: A3930DMIPS/W Configurable Near-Threshold 3D Stacked System with 64 ARM Cortex-M3 Cores, Proceedings of International Solid-State Circuits Conference, pp (2012). [4] Takashi Ishigaki, et al.: Ultralow-power LSI Technology with Silicon on Thin Buried Oxide (SOTB) CMOSFET, Solid State Circuits Technologies, Jacobus W. Swart (Ed.), ISBN: , InTech, pp (2010). [5] Koichiro Ishibashi, et. al.: A Perpetuum Mobile 32bit CPU with 13.4pj/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology, Proceedings of COOL Chips XVII, pp. 1 3 (2014). [6] Hongliang Su, et. al.: Body Bias Control for a Coarse Grained Reconfigurable Accelerator Implemented with Silicon on Thin BOX technology, Proceedings of Field Programmable Logic and Applications, pp. 1 6 (2014). [7] Masakazu Hioki, et. al.: SOTB Implementation of a Field Programmable Gate Array with Fine-Grained Vt Programmability, J. Low Power Electroappl., pp (2014). [8] Daisuke Ikebuchi, et. al.: Geyser-1: A MIPS R3000 CPU c 2016 Information Processing Society of Japan 9
10 core with Fine Grain Runtime Power Gating, Proceedings of the IEEE Asian Solid-State Circuits Conference, pp (2009). [9] Johannes Maximilian Kuehn, et. al.: Spatial and Temporal Granularity Limits of Body Biasing in UTBB-FDSOI, Proceedings of the 2015 Design Automation & Test in Europe Conference(DATE15), pp (2015). [10] Kuniaki Kitamori, et. al.: Power optimization of a microcontroller with Silicon On Thin Buried Oxide, Proceedings of The 18th Workshop on Synthesis And System Integration of Mixed Information technologies, pp (2013). [11] Shohei Nakamura, et. al.: Measurement of the Minimum Energy Point in Silicon on Thin-BOX(SOTB) and Bulk MOSFET, Proceedings of International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, pp (2015). [12] Toshihiro Takeshita, et. al.: Analyzing the Impacts of Simultaneous Supply and Threshold Voltage Tuning on Energy Dissipation in VLSI Circuits, IEICE Technical Report (IEICE-VLD ), Vol. 114, No. 426, pp (2015). [13] Hayate Okuhara, et. al.: Time Analysis of Applying Back Gate Bias for Reconfigurable Architectures with SOTB MOSFET, Proceedings of The Workshop on Synthesis And System Integration of Mixed Information Technologies(SASIMI2015), pp (2015). [14] Hayate Okuhara, et. al.: A Leakage Current Monitor Circuit Using Silicon on Thin BOX MOSFET for Dynamic Back Gate BIas Control, Proceedings of the COOLChipsXVIII, pp. 1 3 (2015). [15] Matthew Guthaus, et. al.: MiBench Version 1.0, [16] David Brooks, et. al.: Dynamic Thermal Management for High-Performance Microprocessors, Proceedings of High-Performance Computer Architecture, pp (2001). [17] Tadahiro Kuroda, et. al.: A -1.9-V, 150-MHz, 10-mW, 4 mm 2, 2-D Discrete Cosine Transform Core Processor with Variable threshold -Voltage (VT) Scheme, IEEE Journal of Solid-State Circuits., pp (1996). [18] HeungJun Jeon, et. al.: Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems, IEEE Transactions on Instrumentation And Measurement, pp (2010). [19] Neil H.E. Weste, et. al.: CMOS VLSI Design A Circuits and Systems Perspective, Addison Wesley, 4 edition (2010) ( ) IEEE ACM LSI LSI c 2016 Information Processing Society of Japan 10
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Tiny Power On Reset Circuit Literature Number: JAJS547 IC ( C) CMOS IC 2.63V 2.93V 3.08V 3.65V 4.00V 4.38V 4.63V 6 (V RTH ) 2.4V 5.0V V CC (L ow ) ( ) V CC ( ) IC SOT23-5 1 : 2.63V 2.93V 3.08V 3.65V 4.00V
MAX665S//X ABSOLUTE MAXIMUM ATINGS B4P to PKN (MAX665X) to 24 B3P to PKN (MAX665) to 8 B2P to PKN (MAX665S) to 2 BP to PKN, B2P to B
9-65; ev ; / µ µ MAX665S//X PAT MAX665SESA MAX665ESA MAX665XESA TEMP. ANGE -4 C to 85 C -4 C to 85 C -4 C to 85 C PIN- PACKAGE 8 SO 8 SO 8 SO CELL COUNT 2 3 4 TOP IEW () I.C. (B4P) 8 I.C. [B3P] B4P B3P
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Overture 68W ( ) 0.1 (THD N) 20Hz 20kHz 4 68W 8 38W SPiKe (Self Peak Instantaneous Temperature ( Ke)) SOA (Safe Operating Area) SPiKe 2.0 V ( ) 92dB (min) SN 0.03 THD N IMD (SMTPE) 0.004 V CC 28V 4 68W
Unidirectional Measurement Current-Shunt Monitor with Dual Comparators (Rev. B
www.tij.co.jp INA206 INA207 INA208 INA206-INA208 INA206-INA208 V S 1 14 V IN+ V S 1 10 V IN+ OUT CMP1 IN /0.6V REF 2 3 1.2V REF 13 12 V IN 1.2V REF OUT OUT CMP1 IN+ 2 3 9 8 V IN CMP1 OUT CMP1 IN+ 4 11
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NJU72501 チャージポンプ内蔵 圧電用スイッチングドライバ 概要 NJU72501はチャージポンプ回路を内蔵し 最大で3V 入力から 18Vppで圧電サウンダを駆動することができます このチャージポンプ回路には1 倍 2 倍 3 倍昇圧切り替え機能を備えており 圧電サウンダの音量を変更すること
チャージポンプ内蔵 圧電用スイッチングドライバ 概要 はチャージポンプ回路を内蔵し 最大で3 入力から 18ppで圧電サウンダを駆動することができます このチャージポンプ回路には1 倍 2 倍 3 倍昇圧切り替え機能を備えており 圧電サウンダの音量を変更することができます また シャットダウン機能を備えており 入力信号を検出し無信号入力時には内部回路を停止することでバッテリーの長寿命化に貢献します
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Vol. 52 No. 1 257 268 (Jan. 2011) 1 2, 1 1 measurement. In this paper, a dynamic road map making system is proposed. The proposition system uses probe-cars which has an in-vehicle camera and a GPS receiver.
alternating current component and two transient components. Both transient components are direct currents at starting of the motor and are sinusoidal
Inrush Current of Induction Motor on Applying Electric Power by Takao Itoi Abstract The transient currents flow into the windings of the induction motors when electric sources are suddenly applied to the
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DS90LV019 DS90LV019 3.3V or 5V LVDS Driver/Receiver Literature Number: JAJS563 DS90LV019 LVDS 1 / DS90LV019 Low Voltage Differential Signaling (LVDS) 1 CMOS / DS90LV019 EIA-644 IEEE1596.3 (SCI LVDS) 2
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(a) 1 (b) 3. Gilbert Pernicka[2] Treibitz Schechner[3] Narasimhan [4] Kim [5] Nayar [6] [7][8][9] 2. X X X [10] [11] L L t L s L = L t + L s
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1.0 1. Display Format 8*2 Character 2. Power Supply 3.3V 3. Overall Module Size 30.0mm(W) x 19.5mm(H) x max 5.5mm(D) 4. Viewing Aera(W*H) 27.0mm(W) x 10.5mm(H) 5. Dot Size (W*H) 0.45mm(W) x 0.50mm(H) 6.
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お客様各位 カタログ等資料中の旧社名の扱いについて 2010 年 4 月 1 日を以って NEC エレクトロニクス株式会社及び株式会社ルネサステクノロジが合併し 両社の全ての事業が当社に承継されております 従いまして 本資料中には旧社名での表記が残っておりますが 当社の資料として有効ですので ご理解の程宜しくお願い申し上げます ルネサスエレクトロニクスホームページ (http://www.renesas.com)
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