Low Power SoC Technology Development at STARC 2 Koichiro Ishibashi 3 4 Semiconductor» 5 Technology Academic Research Center (STARC) Yokohama, Japan Th

Size: px

Start display at page:

Download "Low Power SoC Technology Development at STARC 2 Koichiro Ishibashi 3 4 Semiconductor» 5 Technology Academic Research Center (STARC) Yokohama, Japan Th"

そうけいれい
5 years ago
Views:

1 Low Power SoC Technology Development at STARC Koichiro Ishibashi Semiconductor Technology Academic Research Center (STARC) Yokohama, Japan The 2nd Hiroshima International Workshop on Nanoelectronics for Terra-Bit Information Processing, Jan. 3, Outline Outline of Project ASUKA Low Power Technology Development at STARC 2 Developed Low Power Technology - Self-Adjusted Forward Body Bias - Body Gating - High speed ADC Device Model Issues Summary 2 2 Project ASUKA Development Scheme JEITA Semiconductors Executive Committee ASUKA Device and 2 Design Process Technology Technology STARC Selete Established» December, Established February,1996 Members (12 companies) Related Research Organization NEDO MIRAI ASET HALCA EUVA ASPLA Overseas consortium (IMEC,SRC etc.) Universities Equipment & materials suppliers, EDA vendors 3 3 Design Technology Development in STARC - SoC Design Flow - System-Level System level design technology System Level System description Architecture design Design Group RTL generation SW generation 4HW/SW co-verification System Library RTL/Gate-Level RTL design verification IP reuse circulation IP IPTechnology Logic synthesis IP Library Group Layout DR/library standardization Timing analysis Cell library Circuit/Layout-Level TEG Distribution Model Physical Device model Design Group Physical optimization Ultra low power technology System Circuit -Level Low Low Power Technology Group 4 4

Low power CPU Low power 2 hardware macro Low voltage ADC Low Power SoC Low power and high density memory Hard IP Analog CPU Memory 5 5 Target - Low voltage operation of each IP block - Digital -.

2 Low power CPU Low power 2 hardware macro Low voltage ADC Low Power SoC Low power and high density memory Hard IP Analog CPU Memory 5 5 Target - Low voltage operation of each IP block - Digital -.5V digital circuit -3 Power Management Analog - 1V operation ADC - Noise suppression scheme Memory -.5V operation on-chip RAM 6 6 Gate Leak Reduction by Super Low Voltage Ref.S.H.Lo et al., Gate leakage current is reduced by 2 orders of mag. when suply voltage is decreased from 1.2V to.5v 7 7 Supply Voltage V High Speed Analog Circuit using Low Vdd Logic Transistors Frequency (Hz) 2 1 1G 1G 1G 1M 1M Analog PRML Video Voice High speed application Gate Length m Logic.7 Ft for Logic Tr. Ft for Analog Tr. 8 8

3 New Applications of Low Power SoCs Ultra-small AV machine Wearable computer SoC(System on Chip) Ultra-low power consumption PDC on your wrist Low Power Project Time Line Fiscal Year Master Plan Building Block Development (13nm) SoC Development (9nm) T.T. Intelligent card Intelligent robot 4G cellular phone Contribution to realize these applications by decreasing the power of SoC to 1/ Presentation at International Conferences T. Yamashita et al., A V-driver Circuit for Lowering Power of sub-.1 m Bus, 22 AP-ASIC, Taipei K. Ishibashi et al., A 9 W 5MHz 32b Adder Using a Self-Adjusted Forward Body Bias in SoCs, 23 ISSCC, San Francisco H. Okada et al., Offset Calibrating Comparator Array for 1.2-V, 6- bit, 4-Gsample/s Flash ADCs using.13- m generic CMOS technology, 23 Ess. 4 Circ., Lisbon K.Ishibashi et al.,» "Low 5 Power SoC Project in STARC, 23 VLSI- TSA, Taipei Y. Arima et al., A Cosmic-Ray Immune Latch Circuit for 9-nm Technology and Beyond, 24 ISSCC, San Francisco T. Tsukada et al., "An On-Chip Active Decoupling Circuit to Suppress Crosstalk in Deep Sub-Micron CMOS Mixed-Signal SOCs, 24 ISSCC, San Francisco Strategy to Obtain Low Power Digital Circuit Combination of High Performance Device and Super Low Voltage Operation Ultra 2low AC power with relatively high performance Gate leakage and DIBL is reduced Variation due to PVT Self-adjusted Forward body bias Large subthreshold leakage current Power management by body gating 12 12

4 SAFBB Technique (Self-Adjusted Forward Body Bias) 9 W 3 32bit Simple body bias circuit Self - Adjusted Forward Body Bias Concept Vbn Forward body bias as Vbe Ibn n+ p+ P WELL n+ Self-adjusted I depending on Ibn temperature Vbn Practical Implementation of SAFBB Cbn Ibn Vbn Body bias Controller p+ P well well Logic cells n+ Vbp 15 Ibp m 41 m Test Chip Structure Body bias.13 m CMOS controller - P-sub, twin well - VT:.16V/.25V 595 m 154 m 32 - bit adder - Binary CLA k transistors - Static CMOS circuits 16 16

5 Measured 32-bit Adder Delay 21 7 Delay (ns) -2 1 VT =.25 V -61% Bias SAFBB -25% Supply Voltage (V) Consuming Current of 32-bit Adder A) AC (SAFBB) DC (SAFBB) DC ( body bias) Consuming Current ( 6 VT =.16 V A 5 MHz 4 MHz Supply Voltage (V) z 5 MH Power Delay Product of 32 - bit Adder m SOI 32-b ALU m 32-b ALU prop. Delay (ns) 1pJ mw MPEG2 Body Gating Leakage Current Control.3pJ Power ( W)

6 Body Gating Technique Leakage reduction by controlling body bias 2 Vdd» Body 5 bias controller Load Body Power AC DC Control CPU conv. signals 1 KGate 32 MCycle/s ME 5 KGate 64 MCycle/s PMU DF Body bias controller SoC with Body Gating 3 KGate 64 MCycle/s DCT 3 KGate 64 MCycle/s VLD 1 KGate 32 MCycle/s Clock Power prop. Clock Body Power 32/64 MHz 4 MHz 4 MHz Power Estimation for MPEG2 CODEC CPU Standard V Body Gating with V ME DF DCT/ IDCT 3.6 mw (DC leak.75 mw) VLD 16.4 mw High Speed ADC 2Gsample/s Offset Voltage Reduction

7 Issues of Low-Voltage ADC Comparator Array Architecture of ADC - Offset Canceling Circuit - (1) High impedance of switching transistor Avoid switching transistor (2) Large Vth mismatch of paired transistors Offset voltage cancel circuit (3) Limited number of transistors in cascade configuration Simple current source circuit Vin Vref_top Vref+.25LSB Vref Vref-.25LSB SW Controller VRA Vref_n Counter /Operation TCA2 Regular comparator array TCA Vref_btm Resolution : +/-.25 LSB Adjustable range: +/-1.75 LSB Block Diagram of 4-bit Flash ADC Block Diagram of 4 Vref_btm Vref_top Vin Circuits of Amplifiers Circuits of Amplifiers VRA TCA Pre- amplifier 2 Comparatorlatch NAND (Error Correctin) Selector Gray Code Encoder SW Controller TCA Counter /Operation VDD Vin A B biasp Vref M1 M2 Output A M3 VDD biasp Output B M4 Vlatch Memory Digital Output Digital Output (Selectable rate) GND GND (a) Low-voltage pre-amplifier (b) Low-voltage comparator-latch 28 28

Chip Micrograph of ADC. VRA Comparator-latch SW Controller Memory Effect of Offset Calibration 3 2 1 offset (mv) -1-2 no cal with cal -3 4 8 12 16 comparator number Pre-amp.

8 Chip Micrograph of ADC. VRA Comparator-latch SW Controller Memory Effect of Offset Calibration offset (mv) -1-2 no cal with cal comparator number Pre-amp. Encoder 12 8um Regenerated Waveforms Position of ADC binary code sample point (a) 2.15 GSample/s and 2.-MHz input frequency at Vdd=.9 V. binary code sample point (b) 4. GSample/s and 5.-MHz input frequency at Vdd=1.2 V. 1 Conversion Rate [GHz] 8b 1 6b b 1b 7b 1b 1b Analog Supply Voltage [V] 4b THIS WORK 6b

9 Device Model Issues Digital Circuit - Leak Model - Substrate bias effect Forward body bias Diode 2 model for forward body bias - Expansion of parameter set - Best and 4 worst model ADC - Accuracy in triode and saturation, and their boundary region - High speed simulation(after LPE) - Channel Leakage - GIDL (Gate Induce Drain Leakage) - Gate 2 Tunneling Current Gate Source Sub Leak Model Drain Junction Leak Gate Leak Channel Leak Substrate Bias Effect Necessary model for SAFBB technique - Accurate transistor model at forward body bias condition - Accurate source and drain diode model including forward direction Argument Which approach is better for high speed and low power operation - Low substrate 2 bias constant MOSFET without body bias technique - High substrate bias constant MOSFET with body bias technique Scalable MOS parameter helps to solve the argument 36 36

10 Expansion of parameter set - Each device model is assigned depending on L and W(13nm), and gate - diffusion edge distance (9nm) - hard to handle 4 poly diffusion What are the best and the worst model - The best and the worst model are depending on circuits (Random Logic, Clock Distribution, Memory, and Analog) - How to handle the distribution of characteristics of MOS transistors Accuracy of the model - Accuracy of model in triode, saturation and their boundary. - Normally accuracy in saturation region has a priority for logic design. Analog designers must first design circuits using inaccurate model for triode region. High Speed Circuit Simulation - ADC was designed first by Hspice simulation - Layout - LPE - fast circuit simulation - High speed 4simulation is necessary - Usage of Hsim (Nassda) two days simulation for 116K Tr. 4bit ADC

11 Conclusions Low Power SoC in Project ASUKA - Low voltage Logic, Analog, and Memory 3 Low Power Techniques - SA-FBB Technique - Body gating - High-speed ADC Various Device Model Issues at design 41 41

LMC6022 Low Power CMOS Dual Operational Amplifier (jp)

LMC6022 Low Power CMOS Dual Operational Amplifier (jp) Low Power CMOS Dual Operational Amplifier Literature Number: JAJS754 CMOS CMOS (100k 5k ) 0.5mW CMOS CMOS LMC6024 100k 5k 120dB 2.5 V/ 40fA Low Power CMOS Dual Operational Amplifier 19910530 33020 23900