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2 S ANIRTAO ANIR HAWAII-2 Rockwell Scientific Company(RSC: Teledyne) HAWAII-2 HAWAII HgCdTe HAWAII-2 1 HAWAII HAWAII-2 Rockwell Parameter Measured Performance Units Detector Interface Circuit SFD Cell Pitch 18 µm Die Size 1600 mm2 Integration Capacity 1.0x105 Carriers Integration Capacitance ff Signal Conversion Gain µv/e- Output Signal Excursion V Maximum Data Rate >1 MHz Maximum Slew Rate 400 nsec Minimum Read Noise (CDS) <10 e- Minimum Read Noise (Fowler Sampling) <3 e- Quantum Efficiency >60 % Spectral Response µm Dark <0.03 <10e-/sec Power Dissipation <2 mw

3 1 Rockwell 1.2. HAWAII-2 Power Supplies (7): 2 Rockwell VDD Digital high VSS Digital low MUXSUB Multiplexer substrate VDDA Analog high DSUB Detector substrate DRAIN Amp drain voltage, pulled up to VDDA internally CELLDRAINAnalog low in the unit cell Control Signals (13): 3 Rockwell CLK1 Clock for horizontal register (Pixel)

4 CLKB1 CLK2 CLKB2 VCLK LSYNC FSYNC RESET READ O1 O2 LRST Clock for horizontal register (Pixel) Clock for horizontal register (Pixel) Clock for horizontal register (Pixel) Master clock for the vertical register External line sync External frame sync Control signal for reseting all the pixels Control signal for the readout Control signal for the output option Control signal for the output option Reset for horizontal shift register Optional control signal to reset the column bus to RESETEN celldrain while no readout Biases (3): 4 Rockwell BIASPWR Source voltage of bias P-fet BIASGATEGate voltage of bias P-fet VRESET Zero signal reference in the cell Outputs (9): 5 Rockwell OUTPUT[1:8]The final outputs for 8 buses OUTPUT9 Output of reference signal Test Pads (3): 6 Rockwell Horizontal testing signal output when TESTEN = LINECHK high Vertical testing signal having output when FRAMECHK TESTEN = high

5 2 HAWAII-2 Rockwell 3 Rockwell

6 4 HAWAII-2 HAWAII-2

7 LINUX PCI PCI PCI2772C Interface DMA 20 MHz 32 USB Bias Dewar D F E O T B Bias Clock ADC MUX Out Sw Clk Sw Bias Check DRV Bias Clk LS CPLD Bias Setup DAC Clock Setup/Monitor USB LINUX DIO Clock Clock (Trigger) Output (Serial) Ch0 FPGA S/P LVDS (Optional) Output (Parallel) Output (Analog) ADC Pre AMP Output (Serial) AD Ch16 x 17 ADC Pre AMP SF SF 5 DRV ADC DRV DRV 12 ANIR 7

8 Low, Mid, High ( 4 ) DAC HAWAII-2 5 V V 1 7 Mid High DRV ADC ADC AD DRV 17 ANIR ANIR HAWAII-2 ZIF HAWAII-2 1 /1 5µs10µs200 khz100 khz1k 1k 5~ MB ( bit) MOIRCS CISCO 2.3. Linux ADC (1)

9 ika.mtk.ioa.s.u-tokyo.ac.jp 2.4. (1) ZIF 6 HAWAII HAWAII-2 NIFS Rockwell

10 Heater Window Detector Cassette MDM Connector Detector 8 mm ZIF 10 mm Board 1.5 mm Detector Heat Path Heat Sink 8 mm Heat Path Sensor Heater MDM Connector Detector Heat Path 7 MDM 8

11 2.5. ANIR LINUX Motor Controller DIO USB Clock Bias setup/monitor USB Motor Driver Motor Driver Hall Sensor Interface Clock Bias Check Bias DRV Power Hermetic 18-1 H1 15 Hermetic Motor 4 10 Hall sensor Pt2 Detector 4 AD Output Power Hermetic Dewar H2 Cold Head Pt1 Hermetic Pt3 Heater 2 4 H4 H3 Pt4 4 Lake Shore Radiation Shield 9 ANIR

12 10

13 2.6. TEXIO KENWOOD) PWR1.8Q BRAIN 4

14 2.7. (1) Linux PCI PCI2772C Interface DMA 20 MHz 32 Linux RTAI RTAI ANIR PC OS Vine Linux 4.1 kernel RTAI 3.5 DSP OS (2) TAO array controller (TAC) Ver /2 developers manual (3) MySQL MySQL uni ika uni uni

15 HAWAII-2 DRAIN, VDDA, VDD, VRESET VFET, FETBIAS, FETGATE3 RESET, READ, FSYNC, LSYNC, VCLK, CLK1, CLK2, CLKB1, CLKB2, LRST, RESETEN, O1 12 TESETEN O2 GND ANIR 2 Eagle 4.1 CadSoft Computer LINUX 11 ANIR MOIRCS CISCO HAWAII-2 J270 HAWAII Rockwell(Teledyne) mm 71 mm 12 Top Bottom PWR GND Top Bottom PWR

16 11 ANIR

17 12 ANIR mm

18 P-ban.com 13 ZIF HAWAII-2 13 (4)

19 14 ZIF ( 41 ZIF ZIF MUXSUB GND ZIF (

20 15

21 HAWAII-2 16 DRV

22 HAWAII-2 OSW ANIR OSW ON DRV 17 DRV

23 2 IC USB FT232Xilinx ds013 Windows Xilinx ISE7.1i 1 USB Xilinx (:)LINUX USB 17 DRV Max38 ANIR 18 DRV

30 5ANIR 19 AD 19 AD

31 (1 ADC a. R R A 2 2 ' = 1 + Vout Voff R1 R 1 R B 2 ' = 1 + Vref R1 b. 1 R A '' = 2OCM ( A' B' ) 2 R B A 1 R B '' = 2OCM + ( A' B' ) 2 R B A A A 2 A(Vout) Voff B (Vref) R1 R2 B RA RB B b a 20 A' ' B' ' 1 RB R R Vout Vref Voff + OCM R A R ( ) 2 1 R = 1 1 RB R R + Vout Vref Voff + OCM R A R ( ) 2 1 R = 1 R = = B R + 2 R2 B' ' A'' V ADC 1 ( Vout Vref ) Voff (1) RA R1 R1

32 [ ] 2 ( A" + B" ) B" A" = / 2 = OCM ( A' B' ) R R B A DARK A V B SAT B A DARK DARK SAT OCM SAT ADC A IN-B IN+ 3 < 0 < IN 0 < IN ( IN IN ) + + < 3 < 3 < + 3 ADC OCM = 1/23 V = 1.5 V A DARK B DARK SAT 3 V B OCM SAT A DARK SAT 0 V DARK B A SAT B A DARK DARK SAT OCM SAT 3 V 0 V

33 3V OCM 1.5 V 2.1 V (70) HAWAII-2 Vout = 2.5 V dark, Vout = 2.0 full, Vref = 2.5 V Vout Vref = 0.5 V Vout Vref = 0.0 V (1) R R B A 1 = R 1+ R V off R = 2 R R1 R1 IC B < 4V Vref = 2.5 V 1R2/R1 < 1.6 IC 1R2/R1 = 1.3 Voff1.083 V RB/RA = 6.46 B = 3.25 V A = V B = 2.55 V A = V B = 0.45 V 2 f0 = 500 khz 10 5 e- = 0.5 V, ADC 16, ADC 6 V 2.18 [ e- / ADU ] (2) ADC 21 ADC

34 [ ] Vout : 2.0 ~ 2.5 V sin 200 khz Vref : 2.5 V Voff : 1.3 V [ ] A : 2.93 ~ 3.58 V sin B : 3.25 V A : 0.45 ~ 2.5 V sin B : A 22

35 ADC-DRV 23 5PCI ADC DRV DRV HAWAII-2 12 HIGH = 5V, LOW = 0V 24

36 25 DRV

37 26 CLK1, CLK2, CLKB1, CLKB2

AD8212: 高電圧の電流シャント・モニタ

AD8212: 高電圧の電流シャント・モニタ 7 V typ 7 0 V MSOP : 40 V+ V SENSE DC/DC BIAS CIRCUIT CURRENT COMPENSATION I OUT COM BIAS ALPHA 094-00 V PNP 0 7 V typ PNP PNP REV. A REVISION 007 Analog Devices, Inc. All rights reserved. 0-9 -- 0 40