IPSJ SIG Technical Report Vol.2015-ARC-215 No.13 Vol.2015-OS-133 No /5/ ,a) % 13.9% 1. Transactional Memory: TM [1] TM TM 1 Nag
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1 ,a) % 13.9% 1. Transactional Memory: TM [1] TM TM 1 Nagoya Institute of Technology, Nagoya, Aichi, , Japan a) tsumura@computer.org Hardware Transactional Memory: HTM HTM Read Write Read Write HTM 2. HTM 2.1 Read Write c 2015 Information Processing Society of Japan 1
2 1 Futile Stall Read Write HTM 1 Tx.X 2 thr.1 thr.2 A load A thr.2 store A LogTM[2] Eager Conflict Detection HTM thr.2 Nack Tx.X t1 thr.1 store A t2 thr.2 thr.1 Nack thr.1 Nack Tx.X t3 thr.2 Tx.X thr.1 thr.2 Futile Stall[3] HTM 2.2 Futile Stall Read Write Read Read Read 2 [4][5]Read Write Read Read Read Read Nack 2 3 thr.1 3 Read Write Tx.X thr.2 A load A thr.1 thr.3 load A t1 t2 thr.1 thr.3 Read thr.2 A Read thr.1 thr.3 Nack Nack t3 t4 thr.1 thr.3 A Read thr.2 A Write Tx.X 1 Futile Stall thr.2 Tx.X thr.1 A Read t5 thr.3 thr.1 Nack thr.1 Tx.X thr.3 Read t7 Read Write Read Nack c 2015 Information Processing Society of Japan 2
3 3 thr.1 A thr.2 thr.1 thr.2 Tx.X thr.1 Tx.X thr.2 thr.1 Tx.X thr.2 Tx.X thr.1 Committed Tx.X t4 2.2 Wait Committed Read Write write Read Write 3 2 thr.1 thr.2 2 thr.2 load A A Read thr.1 load A t1 thr.1 thr.2 A A thr.2 Read thr.2 thr.1 Wait thr.1 t2 thr.2 store A thr.2 Tx.X A A thr.2 thr.1 Ack thr.1 t3 thr L1 Combined-Control bit C : Read Write [5] Lock bit L : Read Write Read Write Read Write Write Read Write ID Write 2 2 Address List(A-List) Dependence Table(D-Table) Address List Read Write Dependence Table 4 Prev-Core(Prev): Address List c 2015 Information Processing Society of Japan 3
4 4 Read Write 5 Wait Next-Core(Next): Address List Target-TxID(TxID): Address List Read Write ID Target-PC(PC): Address List Read Write Write PC Read Write Dependence Table Target-TxID Target-PC Read Write Read Write C Address List 4 A Read Write Tx.X 2 thr.1 thr.2 Dependence Table Target-TxID Target-PC 1 load A thr.2 store A thr.1 A Read t1thr.1 Nack thr.2 Tx.X thr.1 store A A Req.A thr.2 thr.1 Nack t2 thr.1 Tx.X t3 A Read Write thr.1 A R 4 Core.1 L1 A R thr.1 A Read Write thr.1 A C A Address List t3 thr.1 store A A Read Write ID X Dependence Table thr.1 Tx.X A Write thr.1 A C-bit A-List Dependence Table Info. thr.2 t4 Info Read Write c 2015 Information Processing Society of Japan 4
5 6 7 A Read Write Tx.X 2 thr.1 thr.2 L1 A C 2 A ID X 0xf80 5 thr.2 load A C A Read thr.2 A Read Write Read Write A L t1 thr.1 load A A Req.A thr.2 Req.A thr.2 A C L thr.2 thr.1 thr.2 thr.1 Wait thr.1 A Read t2 thr.2 thr.1 thr.1 1 Dependence Table Next-Core C L A thr.2 store A 6 t4 thr.2 Read Write A Write Dependence Table thr.2 ID Dependence Table Target-TxID Target-PC thr.2 A Write A L thr.1 A thr.2 thr.2 Dependence Table Next-Core t4 thr.2 1 Core.1 Read thr.1 Ack Ack thr.1 A Read thr.2 Read t5 thr.2 thr.1 thr.2 Tx.X thr.1 Tx.X thr.2 thr.1 Tx.X thr.1 thr.2 2 Dependence Table Prev-Core t5 thr.1 Tx.X 7 t6 thr.1 Dependence Table Prev-Core 2 Core.2 thr.2 thr.1 Tx.X thr.2 Tx.X t7 thr.2 Dependence Table Next-Core thr.2 1 Tx.X Core.1 Core.1 Committed Dependence Table Next-Core t7 Committed thr.1 thr.2 Tx.X Dependence Table Prev-Core Tx.X c 2015 Information Processing Society of Japan 5
6 t8 4. Yoo [6] HTM Adaptive Transaction Scheduling Geoffrey [7] similarity Akpinar [8] HTM Bobba [3] Store Predictor Store Predictor Read Write Bobba Read Read Write Read Write after Read Nack Read Futile Stall Store Predictor Read Write Read Write Bobba HTM LogTM[2] Simics[9] GEMS[10] Simics GEMS 32 SPARC V9 OS Processor #cores clock issue width issue order 1 non-memory IPC 1 D1 cache ways latency D2 cache ways latency Memory latency Interconnect network latency SPARC V9 32 cores 1 GHz single in-order 32 KBytes 4 ways 1 cycle 8 MBytes 8 ways 20 cycles 8 GBytes 450 cycles 14 cycles Solaris 10 1 GEMS microbench SPLASH-2[11] STAMP[12] (B) (R) (E) (P) LogTM Store Predictor Read Write Read Write (B) 1 [13] 10 95% 4 (R) Store Predictor Read Write (R) Read Write Store Predictor (R) Non trans Good trans c 2015 Information Processing Society of Japan 6
7 8 2 GEMS SPLASH-2 STAMP All (E) 28.4% 9.4% 3.0% 13.6% 72.3% 25.7% 7.5% 72.3% (P) 28.6% 10.4% 2.7% 13.9% 67.2% 23.1% 6.4% 67.2% Bad trans Aborting Backoff Stall Barrier MagicWaiting 8 Btree (R) (E) (P) (B) Futile Stall (E) (P) (E) (B) 72.3% 13.6% (P) (B) 67.2% 13.9% 5.3 (E) (P) Prioque Radiosity (P) (E) 9 (E) 9(a) Tx.P Tx.Q Tx.R 3 thr.1 thr.3 thr.2 thr.3 Nack possible cycle t1 possible cycle thr.2 load A t2 thr.1 load A thr.1 (E) thr.2 Nack c 2015 Information Processing Society of Japan 7
8 t3 (P) (E) 10 thr.2 possible cycle thr.1 Nack Tx.Q t3 (P) 9(b) t3 thr.2 thr.1 Nack Wait thr.2 thr.1 thr.2 Prioque Radiosity (P) (E) Btree Contention Deque Raytrace Kmeans+ 4 (E) (P) (P) 10 Tx.J Tx.K 2 thr.1 thr.2 thr.1 thr.2 load A t1 thr.1 thr.2 thr.2 t2 thr.2 store B thr.1 load B thr.1 thr.2 Nack Nack thr.2 thr.1 thr.1 Tx.J C L Address List Dependence Table 2 Address List Dependence Table Futile Stall Dependence Table Target-TxID Target-PC Address List 10 Dependence Table 10 3 Target-TxID Target-PC Address List 1 1 Target-Address 64bits Dependence Table 1 Prev-Core Next-Core Target-TxID Target-PC 4bits 4bits 4bits 64bits Address List CAM Dependence Table Address List Address List RAM Address List 1 64bits 10 CAM Dependence Table 1 4bits + 4bits + (4bits + 64bits) 3 = 212bits 10 RAM L1 C L 1 2bits KBytes 1 350Bytes 350Bytes 1 L1 32KBytes c 2015 Information Processing Society of Japan 8
9 1% (P) 2 2 C T C T Address List 10 CAM TLB 1cycle Dependence Table 212bits 10 RAM Dependence Table Address List 1cycle Dependence Table 1cycle Dependence Table 3 ID 3 Dependence Table 1cycle + (1cycle + 1cycle) 3 = 7cycles 2 Prioque 0.89% 2 6. Read Write HTM HTM GEMS microbench SPLASH-2 STAMP HTM % 13.9% 6KBytes Read Write Read Write [1] Herlihy, M. and Moss, J. E. B.: Transactional Memory: Architectural Support for Lock-Free Data Structures, Proc. 20th Annual Int l Symp. on Computer Architecture, pp (1993). [2] Moore, K. E., Bobba, J., Moravan, M. J., Hill, M. D. and Wood, D. A.: LogTM: Log-based Transactional Memory, Proc. 12th Int l Symp. on High-Performance Computer Architecture, pp (2006). [3] Bobba, J., Moore, K. E., Volos, H., Yen, L., Hill, M. D., Swift, M. M. and Wood, D. A.: Performance Pathologies in Hardware Transactional Memory, Proc. 34th Annual Int l Symp. on Computer Architecture (ISCA 07), pp (2007). [4] Read-after-Read (ACS44) Vol. 6, No. 4, pp (2013). [5] (ARC200) Vol ARC-208, No. 22, pp. 1 8 (2014). [6] Yoo, R. M. and Lee, H.-H. S.: Adaptive Transaction Scheduling for Transactional Memory Systems, Proc. 20th Annual Symp. on Parallelism in Algorithms and Architectures (SPAA 08), pp (2008). [7] Blake, G., Dreslinski, R. G. and Mudge, T.: Bloom Filter Guided Transaction Scheduling, Proc. 17th International Conference on High-Performance Computer Architecture (HPCA ), pp (2011). [8] Akpinar, E., Tomić, S., Cristal, A., Unsal, O. and Valero, M.: A Comprehensive Study of Conflict Resolution Policies in Hardware Transactional Memory, Proc. 6th ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 11) (2011). [9] Magnusson, P. S., Christensson, M., Eskilson, J., Forsgren, D., Hållberg, G., Högberg, J., Larsson, F., Moestedt, A. and Werner, B.: Simics: A Full System Simulation Platform, Computer, Vol. 35, No. 2, pp (2002). [10] Martin, M. M. K., Sorin, D. J., Beckmann, B. M., Marty, M. R., Xu, M., Alameldeen, A. R., Moore, K. E., Hill, M. D. and Wood., D. A.: Multifacet s General Execution-driven Multiprocessor Simulator (GEMS) Toolset, ACM SIGARCH Computer Architecture News, Vol. 33, No. 4, pp (2005). [11] Woo, S. C., Ohara, M., Torrie, E., Singh, J. P. and Gupta, A.: The SPLASH-2 Programs: Characterization and Methodological Considerations, Proc. 22nd Annual Int l. Symp. on Computer Architecture (ISCA 95), pp. c 2015 Information Processing Society of Japan 9
10 24 36 (1995). [12] Minh, C. C., Chung, J., Kozyrakis, C. and Olukotun, K.: STAMP: Stanford Transactional Applications for Multi- Processing, Proc. IEEE Int l Symp. on Workload Characterization (IISWC 08) (2008). [13] Alameldeen, A. R. and Wood, D. A.: Variability in Architectural Simulations of Multi-Threaded Workloads, Proc. 9th Int l Symp. on High-Performance Computer Architecture (HPCA 03), pp (2003). c 2015 Information Processing Society of Japan 10
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