IPSJ SIG Technical Report Vol.2018-ARC-231 No /6/ TM HTM Tx HTM Tx read write Tx Tx Tx read write LogTM 63.6% 38.8% 1. Transaction
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1 TM HTM Tx HTM Tx read write Tx Tx Tx read write LogTM 63.6% 38.8% 1. Transactional Memory TM [1] TM Transaction Tx TM 1 Nagoya Institute of Technology 2 Nagoya University 3 National Institute of Informatics Hardware Transactional Memory HTM HTM Tx read write Tx Tx Tx read write c 2018 Information Processing Society of Japan 1
![2. HTM Tx Tx [2], [3], [4] [5], [6], [7] Yoo [8] HTM Adaptive](/docs-images/101/151333863/images/2-0.jpg "Transaction Scheduling Tx lake [9] Tx Similarity Tx Tx [10] Tx")
![Tx read write Tx Tx [11], [12] Tx Tx 3.](/docs-images/101/151333863/images/2-1.jpg "HTM HTM t5 t6 1 Stall Commit N N Core1 Thread1 Req.")
2 2. HTM Tx Tx [2], [3], [4] [5], [6], [7] Yoo [8] HTM Adaptive Transaction Scheduling Tx lake [9] Tx Similarity Tx Tx [10] Tx Tx read write Tx Tx [11], [12] Tx Tx 3. HTM HTM t5 t6 1 Stall Commit N N Core1 Thread1 Req.A Restart HTM HTM 3.1 HTM HTM Tx Atomicity Tx Isolation Tx Tx Tx Tx HTM Tx HTM 1 T hread0 T hread1 T x.x T x.y Tx ID T x.x T x.y X Y ID Tx T hread0 T x.x T hread1 T x.y T hread0 T hread1 T hread1 T x.y T hread0 Isolation T hread1 T hread0 N T hread0 N c 2018 Information Processing Society of Japan 2
3 T x.x T hread1 T hread0 T hread0 T hread1 N T hread1 T hread0 N T hread1 T hread1 store Atomicity T hread1 T x.y T hread1 T x.y T x.y T hread0 t5 T hread1 T hread0 T x.y t6 HTM HTM Tx Log Tx Log Tx Log Tx Tx Tx 3.2 HTM Isolation Tx GEMS microbench [13] Deque 2 Deque Tx 1 EGIN TRANSACTION() 17 COMMIT TRANSACTION() Tx Tx 2 count 4 switch deque Tx count Isolation count Tx count 2 1 EGIN_TRANSACTION(); 2 count++; 3 4 switch(op){ 5 case 0: 6 enqueue_right(); 7 break; 8 case 1: 9 dequeue_right(); 10 break; 11 case 2: 12 enqueue_left(); 13 break; 14 case 3: 15 dequeue_left(); 16 break; 17 } 18 COMMIT_TRANSACTION(); 2 Deque 3 4. Tx 3.2 Tx Tx Tx Tx Tx Tx Tx Tx ID Tx 3 T hread0 T x.x Tx ID X A Tx c 2018 Information Processing Society of Japan 3
4 X A 1 Core1 Thread1 X A 1 X 2 store C X A 4 X 2 X C 3 3 store C X A 4 X 2 X C 3 Commit 3 1 T hread0 Tx ID X 2 T hread0 A T x.y T hread1 T hread0 T hread0 T hread0 T x.x 3 2 T x.x T hread0 T hread1 permitter requester Tx permitter permitter requester requester Tx permitter X A 4 X 4 X C 3 Commit 4 permitter 4 3 permitter T hread0 requester T hread1 T hread1 T hread0 T x.y T hread0 requester permitter ID requester T hread1 permitter T hread0 T hread1 T hread0 requester permitter ID HTM LogTM [14] permitter Tx Isolation c 2018 Information Processing Society of Japan 4
5 Core1 Thread1 Memory Core1 Thread1 更新したアドレス の値を破棄 load 処理を継続すると Isolation が保証されないためアボート A 5 A 10 A 5 Log() Req.A Log(Thread1) Req. A 5 5 Isolation 6 Isolation Isolation 5.1 Isolation Permitter Tx Isolation 5 T hread1 T hread0 permitter T hread0 T hread0 T hread0 T hread0 T hread1 Isolation permitter T hread0 Tx requester T hread1 Tx Isolation Tx Req. permitter Tx Req. requester requester Tx Isolation permitter requester requester ID requester permitter permitter Tx permitter requester Committed Tx permitter requester Committed requester Tx Committed requester permitter Tx 5.2 Tx Tx 6 Log A 3 T hread0 A A 3 T hread0 Log 5 A T hread1 A T hread0 A 5 T hread1 Log A 10 permitter T hread0 T hread0 T hread1 Tx A T hread0 Log 3 T hread1 Log 5 A 5 Tx c 2018 Information Processing Society of Japan 5
6 Memory A 5 A 10 Log() Core1 Thread1 Req.A Log(Thread1) Req. A 5 7 permitter requester Tx requester permitter 7 6 T hread0 T hread0 permitter requester T hread1 T hread0 T hread1 Req. T hread1 T hread0 T hread1 Log 5 A T hread1 T hread0 T hread0 T hread0 Log 3 A - requester permitter ID permitter requester ID requester requester permitter ID ID requester requester ID ID - permitter Req. 4 4 permitter ID HTM LogTM [14] Simics [15] GEMS Simics GEMS 32 SPARC V9 OS Solaris 10 1 GEMS microbench tree Contention Deque SPLASH-2 [16] Raytrace STAMP [17] Kmeans () LogTM (R1) [10] (R2) [11], [12] (P) c 2018 Information Processing Society of Japan 6
7 1 Processor SPARC V9 #cores 32 cores clock 4 GHz issue width single issue order in-order non-memory IPC 1 L1 cache 32 Kytes ways 4 ways latency 3 cycles L2 cache 8 Mytes ways 8 ways latency 20 cycles Memory 4 Gytes latency 450 cycles Interconnect network latency 14 cycles 1 int A[1]; 2 int [1024]; 3 4 EGIN_TRANSACTION(); 5 // A[0] 6 for( i = 0; i < 10; i++ ){ 7 if( access_type[i] == READ ) 8 var = A[0]; 9 else 10 A[0] = 0; 11 } // A[0] 14 for( i = 10; i < 100; i++ ){ 15 if( access_type[i] == READ ) 16 var = [index[i]]; 17 else 18 [index[i]] = 0; 19 } 20 COMMIT_TRANSACTION(); Ratio of cycles () LogTM (R1) 競合を未然に予測し回避する参考モデル フェーズを考慮して競合アクセスを (R2) 投機的に許可する参考モデル (P) 共有変数に対する最終アクセスを検出し競合アクセスを投機的に許可する提案モデル Wait ackoff ad_trans Non_trans Stall ing Good_trans 9 Contention requester Tx (P) () 63.6% 38.8% (R1) (R2) tree Contention Deque tree Contention Deque Raytrace Kmeans GEMS microbench SPLASH-2 STAMP 8 () 1 (R2) [18] 10 95% Non trans Tx Good trans Tx ad trans Tx ing ackoff Stall (R1) Wait Tx (R2) (P) Wait permitter 6.3 tree (P) (R1) Wait (R1) Tx Tx (P) tree tree (R1) Tx Tx (P) Contention (P) () (R1) (R2) Contention Tx for A[0] 14 c 2018 Information Processing Society of Japan 7
8 19 for (R1) A[0] Tx (P) tree () (R1) Wait Stall (R2) 2 for A[0] A[0] (P) (R2) (P). Deque (P) () (R1) (R2) () (R1) Contention 3.2 count (P) (R2) (R2) (P) 2 Tx count (R2) Tx count switch (P) Raytrace () ad trans ing ackoff Stall Raytrace Tx Tx Tx Kmeans () (R1) (P) Non trans 6.4 Tx ID Tx Tx Tx Tx 8 3bit Tx ID 4,807 13bit Tx LogTM 26bit = 42bit Tx Tx tree 15, bit 15, ,018 = 630,756bit c 2018 Information Processing Society of Japan 8
9 permitter requester ID ID permitter requester ID = 32bit ID 1 630, = 630,788bit 77.1Kyte = 1,233.6Kyte 1.2Myte L1 32Kyte Kyte Tx 7. Tx Tx Isolation Isolation GEMS microbench SPLASH-2 STAMP HTM % 38.8% JSPS JP17H01711 JP17H01764 JP17K19971 [1] Herlihy, M. et al.: Transactional Memory: Architectural Support for Lock-Free Data Structures, Proc. 20th Int l Symp. on Computer Architecture (ISCA 93), pp (1993). [2] Moss, E. and Hosking., T.: Nested Transactional Memory: Model and Preliminary Architecture Sketches., Science of Computer Programming, pp (2006). [3] Moravan, M. J., obba, J., Moore, K. E., Yen, L., Hill, M. D., Liblit,., Swift, M. M. and Wood, D. A.: Supporting Nested Transactional Memory in LogTM, Proc. 12th Int l Conf. on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pp (2006). [4] McDonald, A., Chung, J., Caristrom,. D., Minh, C. C., Chafi, H., Kozyrakis, C. and Olukotun., K.: Architectural Semantics for Practical Transactional Memory, Proc. 33rd Annual Int l Symp. on Computer Architecture (ISCA 06), pp (2006). [5] Shriraman, A., Dwarkadas, S. and Scott., M. L.: Flexible Decoupled Transactional Memory Support, Proc. 35th Annual Int l Symp. on Computer Architecture (ISCA 08), pp (2008). [6] Tomic, S., Perfumo, C., Kulkami, C., Armejach, A., Cristal, A., Unsal, O., Harris, T. and Valero., M.: Eazyhtm, Eager-lazy Hardware Transactional Memory, Proc. 42nd Annual IEEE/ACM Int l Symp. on Microarchitecture (MICRO-42), pp (2009). [7] Lupon, M., Magklis, G. and González, A.: A Dynamically Adaptable Hardware Transactional Memory, Proc. 43rd Annual IEEE/ACM Int l Symp. on Microarchitecture (MICRO-43), pp (2010). [8] Yoo, R. M. and Lee, H.-H. S.: Adaptive Transaction Scheduling for Transactional Memory Systems, Proc. 20th Annual Symp. on Parallelism in Algorithms and Architectures (SPAA 08), pp (2008). [9] lake, G., Dreslinski, R. G. and Mudge, T.: loom Filter Guided Transaction Scheduling, Proc. 17th Int l Conf. on High-Performance Computer Architecture (HPCA- 17), pp (2011). [10] Hirota, A., Mashita, K. and Tsumura, T.: A Concurrency Control in Hardware Transactional Memory Considering Execution Path Variation, Proc. 4th Int l Symp. on Computing and Networking (CANDAR 16), pp (2016). [11] (SWoPP2017) Vol ARC-227, No. 40, pp. 1 9 (2017). [12] Tajimi, T., Hirota, A., Shioya, R., Goshima, M. and Tsumura, T.: Initial Study of a Phase-Aware Scheduling for Hardware Transactinal Memory, Proc. IEEE Pacific Rim Conf. on Communications, Computers and Signal Processing (PacRim 2017), pp. 1 6 (2017). [13] Martin, M. M. K. et al.: Multifacet s General Executiondriven Multiprocessor Simulator (GEMS) Toolset, ACM SIGARCH Computer Architecture News, Vol. 33, No. 4, pp (2005). [14] Moore, K. E., obba, J., Moravan, M. J., Hill, M. D. and Wood, D. A.: LogTM: Log-based Transactional Memory, Proc. 12th Int l Symp. on High-Performance Computer Architecture (HPCA 06), pp (2006). [15] Magnusson, P. S. et al.: Simics: A Full System Simulation Platform, Computer, Vol. 35, No. 2, pp (2002). [16] Woo, S. C. et al.: The SPLASH-2 Programs: Characterization and Methodological Considerations, Proc. 22nd Int l. Symp. on Computer Architecture (ISCA 95), pp (1995). [17] Minh, C. C. et al.: STAMP: Stanford Transactional Applications for Multi-Processing, Proc. IEEE Int l Symp. on Workload Characterization (IISWC 08) (2008). [18] Alameldeen, A. R. et al.: Variability in Architectural Simulations of Multi-Threaded Workloads, Proc. 9th Int l Symp. on High-Performance Computer Architecture (HPCA 03), pp (2003). c 2018 Information Processing Society of Japan 9
IPSJ SIG Technical Report Vol.2015-ARC-215 No.13 Vol.2015-OS-133 No /5/ ,a) % 13.9% 1. Transactional Memory: TM [1] TM TM 1 Nag
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