Silicon Storage Technology, Inc. SuperFlash SEIKO EPSON CORPORATION 2011, All rights reserved.
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1 CMOS 16-BIT SINGLE CHIP MICROCONTROLLER S1C17601 Rev. 1.1
2 Silicon Storage Technology, Inc. SuperFlash SEIKO EPSON CORPORATION 2011, All rights reserved.
3 S1 C F 00E : & 0A : TCP BL 2 0B : & BACK 0C : TCP BR 2 0D : TCP BT 2 0E : TCP BD 2 0F : & FRONT 0G: TCP BT 4 0H : TCP BD 4 0J : TCP SL 2 0K : TCP SR 2 0L : & LEFT 0M: TCP ST 2 0N : TCP SD 2 0P : TCP ST 4 0Q: TCP SD 4 0R : & RIGHT 99 : D: F: QFP B: BGA C: S1: S5U1 C H : 1: Version 1 Hx : ICE Dx : Ex : ROM Mx: ROM Tx : Cx : Sx : 33L01: S1C33L01 C: S5U1:
4 CPU S1C CPU PSR , Flash Flash Flash xfffc 0xfffe: Flash Protect Bits Flash x5320: FLASHC Control Register (MISC_FL) RAM RAM x5326: IRAM Size Select Register (MISC_IRAMSZ) RAM RAM x4000~ x5000~ I/O x5120: VD1 Control Register (VD1_CTL) x50a3: LCD Voltage Regulator Control Register (LCD_VREG) #RESET P S1C17601 TECHNICAL MANUAL Seiko Epson Corporation i
5 ITC ITC ITC S1C NMI HALT, SLEEP x4306: Interrupt Level Setup Register 0 (ITC_LV0) x4308: Interrupt Level Setup Register 1 (ITC_LV1) x430a: Interrupt Level Setup Register 2 (ITC_LV2) x430c: Interrupt Level Setup Register 3 (ITC_LV3) x430e: Interrupt Level Setup Register 4 (ITC_LV4) x4310: Interrupt Level Setup Register 5 (ITC_LV5) x4312: Interrupt Level Setup Register 6 (ITC_LV6) x4314: Interrupt Level Setup Register 7 (ITC_LV7) x4316: Interrupt Level Setup Register 8 (ITC_LV8) x4318: Interrupt Level Setup Register 9 (ITC_LV9) OSC OSC IOSC OSC OSC LCD OSC SVD RFC FOUTH, FOUT RESET, NMI x5060: Clock Source Select Register (OSC_SRC) x5061: Oscillation Control Register (OSC_CTL) x5062: Noise Filter Enable Register (OSC_NFEN) x5063: LCD Clock Setup Register (OSC_LCLK) x5064: FOUT Control Register (OSC_FOUT) x5065: T8OSC1 Clock Control Register (OSC_T8OSC1) x5066: SVD Clock Control Register (OSC_SVD) x5067: RFC Clock Control Register (OSC_RFC) CLG CPU CCLK PCLK ii Seiko Epson Corporation S1C17601 TECHNICAL MANUAL
6 0x5080: PCLK Control Register (CLG_PCLK) x5081: CCLK Control Register (CLG_CCLK) PSC x4020: Prescaler Control Register (PSC_CTL) P MUX P0/P x5200/0x5210/0x5220: Px Port Input Data Registers (Px_IN) x5201/0x5211/0x5221: Px Port Output Data Registers (Px_OUT) x5202/0x5212/0x5222: Px Port Output Enable Registers (Px_OEN) x5203/0x5213/0x5223: Px Port Pull-up Control Registers (Px_PU) x5204/0x5214/0x5224: Px Port Schmitt Trigger Control Registers (Px_SM) x5205/0x5215: Px Port Interrupt Mask Registers (Px_IMSK) x5206/0x5216: Px Port Interrupt Edge Select Registers (Px_EDGE) x5207/0x5217: Px Port Interrupt Flag Registers (Px_IFLG) x5208/0x5218: Px Port Chattering Filter Control Register (Px_CHAT) x5209: P0 Port Key-Entry Reset Configuration Register (P0_KRST) x520a/0x521a/0x522a: Px Port Input Enable Registers (Px_IEN) x52a0: P0 Port Function Select Register (P0_PMUX) x52a1: P0 Port Function Select Register (P0_PMUX) x52a2: P1 Port Function Select Register (P1_PMUX) x52a3: P1 Port Function Select Register (P1_PMUX) x52a4: P2 Port Function Select Register (P2_PMUX) x52a5: P2 Port Function Select Register (P2_PMUX) T RUN/STOP x4220/0x4240/0x4260: 16-bit Timer Ch.x Input Clock Select Registers (T16_CLKx) x4222/0x4242/0x4262: 16-bit Timer Ch.x Reload Data Registers (T16_TRx) x4224/0x4244/0x4264: 16-bit Timer Ch.x Counter Data Registers (T16_TCx) x4226/0x4246/0x4266: 16-bit Timer Ch.x Control Registers (T16_CTLx) S1C17601 TECHNICAL MANUAL Seiko Epson Corporation iii
7 0x4228/0x4248/0x4268: 16-bit Timer Ch.x Interrupt Control Registers (T16_INTx) T8F RUN/STOP x4200: 8-bit Timer Input Clock Select Register (T8F_CLK) x4202: 8-bit Timer Reload Data Register (T8F_TR) x4204: 8-bit Timer Counter Data Register (T8F_TC) x4206: 8-bit Timer Control Register (T8F_CTL) x4208: 8-bit Timer Interrupt Control Register (T8F_INT) PWMT16E PWM PWM / PWM RUN/STOP PWM x5300/0x5360: PWM Timer Ch.x Compare Data A Registers (T16E_CAx) x5302/0x5362: PWM Timer Ch.x Compare Data B Registers (T16E_CBx) x5304/0x5364: PWM Timer Ch.x Counter Data Registers (T16E_TCx) x5306/0x5366: PWM Timer Ch.x Control Registers (T16E_CTLx) x5308/0x5368: PWM Timer Ch.x Input Clock Select Registers (T16E_CLKx) x530a/0x536a: PWM Timer Ch.x Interrupt Mask Registers (T16E_IMSKx) x530c/0x536c: PWM Timer Ch.x Interrupt Flag Registers (T16E_IFLGx) OSC1T8OSC OSC OSC OSC OSC1 RUN/STOP OSC PWM x50c0: 8-bit OSC1 Timer Control Register (T8OSC1_CTL) x50c1: 8-bit OSC1 Timer Counter Data Register (T8OSC1_CNT) x50c2: 8-bit OSC1 Timer Compare Data Register (T8OSC1_CMP) x50c3: 8-bit OSC1 Timer Interrupt Mask Register (T8OSC1_IMSK) iv Seiko Epson Corporation S1C17601 TECHNICAL MANUAL
8 0x50c4: 8-bit OSC1 Timer Interrupt Flag Register (T8OSC1_IFLG) x50c5: 8-bit OSC1 Timer PWM Duty Data Register (T8OSC1_DUTY) CT RUN/STOP x5000: Clock Timer Control Register (CT_CTL) x5001: Clock Timer Counter Register (CT_CNT) x5002: Clock Timer Interrupt Mask Register (CT_IMSK) x5003: Clock Timer Interrupt Flag Register (CT_IFLG) SWT BCD RUN/STOP x5020: Stopwatch Timer Control Register (SWT_CTL) x5021: Stopwatch Timer BCD Counter Register (SWT_BCNT) x5022: Stopwatch Timer Interrupt Mask Register (SWT_IMSK) x5023: Stopwatch Timer Interrupt Flag Register (SWT_IFLG) WDT NMI/ RUN/STOP x5040: Watchdog Timer Control Register (WDT_CTL) x5041: Watchdog Timer Status Register (WDT_ST) UART UART UART UART IrDA S1C17601 TECHNICAL MANUAL Seiko Epson Corporation v
9 x4100: UART Status Registers (UART_ST) x4101: UART Transmit Data Registers (UART_TXD) x4102: UART Receive Data Registers (UART_RXD) x4103: UART Mode Registers (UART_MOD) x4104: UART Control Registers (UART_CTL) x4105: UART Expansion Registers (UART_EXP) SPI SPI SPI SPI SPI x4320: SPI Status Register (SPI_ST) x4322: SPI Transmit Data Register (SPI_TXD) x4324: SPI Receive Data Register (SPI_RXD) x4326: SPI Control Register (SPI_CTL) I 2 CI 2 CM I 2 C I 2 C I 2 C I 2 C x4340: I 2 C Enable Register (I2C_EN) x4342: I 2 C Control Register (I2C_CTL) x4344: I 2 C Data Register (I2C_DAT) x4346: I 2 C Interrupt Control Register (I2C_ICTL) I 2 C I 2 CS I 2 C I 2 C I 2 C I 2 C I 2 C x4360: I 2 C Slave Transmit Data Register (I2CS_TRNS) x4362: I 2 C Slave Receive Data Register (I2CS_RECV) x4364: I 2 C Slave Address Setup Register (I2CS_SADRS) x4366: I 2 C Slave Control Register (I2CS_CTL) x4368: I 2 C Slave Status Register (I2CS_STAT) x436a: I 2 C Slave Access Status Register (I2CS_ASTAT) x436c: I 2 C Slave Interrupt Control Register (I2CS_ICTL) vi Seiko Epson Corporation S1C17601 TECHNICAL MANUAL
10 LCD LCD LCD LCD LCD LCD On/Off LCD LCD x50a0: LCD Display Control Register (LCD_DCTL) x50a1: LCD Contrast Adjust Register (LCD_CADJ) x50a2: LCD Clock Control Register (LCD_CCTL) x50a3: LCD Voltage Regulator Control Register (LCD_VREG) x50a5: LCD Interrupt Mask Register (LCD_IMSK) x50a6: LCD Interrupt Flag Register (LCD_IFLG) A/DADC10SA A/D ADC A/D A/D A/D x5380: ADC10 Conversion Result Register (ADC10_ADD) x5382: ADC10 Trigger/Channel Select Register (ADC10_TRG) x5384: ADC10 Control/Status Register (ADC10_CTL) x5386: ADC10 Divided Frequency Register (ADC10_DIV) R/FRFC R/F RFC R/F x53a0: RFC Control Register (RFC_CTL) x53a2: RFC Oscillation Start Register (RFC_TRG) x53a4/0x53a6: RFC measurement Counter Data Register (RFC_MC) x53a8/0x53aa: RFC Time Base Counter Data Register (RFC_TC) x53ac: RFC Interrupt Mask Register (RFC_IMSK) x53ae: RFC Interrupt Flag Register (RFC_IFLG) SVD SVD S1C17601 TECHNICAL MANUAL Seiko Epson Corporation vii
11 25.2 SVD SVD SVD x5100: SVD Enable Register (SVD_EN) x5101: SVD Compare Voltage Register (SVD_CMP) x5102: SVD Detection Result Register (SVD_RSLT) x5103: SVD Interrupt Mask Register (SVD_IMSK) x5104: SVD Interrupt Flag Register (SVD_IFLG) DBG x5322: OSC1 Peripheral Control Register (MISC_OSC1) x5326: IRAM Size Select Register (MISC_IRAMSZ) xffff90: Debug RAM Base Register (DBRAM) xffffa0: Debug Control Register (DCR) xffffb8: Instruction Break Address Register 2 (IBAR2) xffffbc: Instruction Break Address Register 3 (IBAR3) xffffd0: Instruction Break Address Register 4 (IBAR4) LCD SVD A/D Flash SPI I 2 C R/F Appendix A I/O... AP-1 0x4020 Prescaler... AP-5 viii Seiko Epson Corporation S1C17601 TECHNICAL MANUAL
12 0x4100 0x4105 UART (with IrDA)... AP-6 0x4200 0x bit Timer (with Fine Mode)... AP-7 0x4220 0x bit Timer... AP-8 0x4306 0x4318 Interrupt Controller... AP-10 0x4320 0x4326 SPI... AP-11 0x4340 0x4346 I 2 C Master... AP-12 0x4360 0x436c I 2 C Slave... AP-13 0x5000 0x5003 Clock Timer... AP-14 0x5020 0x5023 Stopwatch Timer... AP-15 0x5040 0x5041 Watchdog Timer... AP-16 0x5060 0x5067 Oscillator... AP-17 0x5080 0x5081 Clock Generator... AP-18 0x50a0 0x50a6 LCD Driver... AP-19 0x50c0 0x50c5 8-bit OSC1 Timer... AP-20 0x5100 0x5104 SVD Circuit... AP-21 0x5120 Power Generator... AP-22 0x5200 0x52a5 P Port & Port MUX... AP-23 0x5300 0x530c PWM Timer Ch.0... AP-27 0x5320 0x532c MISC Registers... AP-28 0x5360 0x536c PWM Timer Ch.1... AP-29 0x5380 0x5386 ADC10SA... AP-30 0x53a0 0x53ae RFC... AP-31 0x53c0 0x53d3 SEGRAM... AP-32 0xffff84 0xffffd0 S1C17 Core I/O... AP-33 Appendix B Flash... AP-34 B.1... AP-34 B.2... AP-35 Appendix C... AP-36 C.1... AP-36 C.2... AP-39 Appendix D... AP-40 Appendix E... AP-44 Appendix F... AP-46 S1C17601 TECHNICAL MANUAL Seiko Epson Corporation ix
13 1 1 S1C17601 ICE 16 MCU A/DR/F I/F S1C17601 Technical Manual Seiko Epson Corporation 1-1
14 1 1.1 S1C17601 CPU EPSON 16 RISC CPU S1C IOSC 2.7MHz typ. 5μS max. OSC3 / 8.2MHz max. OSC kHz typ. Flash 32K / 1,000 min. / ICD Mini S5U1C17001H RAM 2K RAM 20 A/D 10 4ch. RF DC /AC / 1ch. 24 SPI/ 1ch. I 2 C 1ch. I 2 C 1ch. UART bps IrDA1.0 1ch. 8 T8F 1ch. 16 T16 3ch. PWMT16E 2ch. CT 1ch. SWT 1ch. WDT 1ch. 8 OSC1 PWMT8OSC1 1ch. LCD 16SEG 8COM 20SEG 4COM 1/3 16 SVD V 3.2V NMI P LCD SVD ADC RFC 1.8V 3.6V 2.7V 3.6V Flash / 2-25 C 70 C SLEEP 0.6μA typ. OSC1=OFF, IOSC=OFF, OSC3=OFF HALT 2.0μA typ. OSC1=32kHz, IOSC=OFF, OSC3=OFF, PCKEN=0x0, LCD OFF 2.7μA typ. OSC1=32kHz, IOSC=OFF, OSC3=OFF, PCKEN=0x0, LCD ON,, VC2 12μA typ. OSC1=32kHz, IOSC=OFF, OSC3=OFF, LCD OFF 340μA typ. OSC1=OFF, IOSC=OFF, OSC3=1MHz TQFP mm 10mm 0.5mm VFBGA8H-81 8mm 8mm 0.8mm 100μm 1-2 Seiko Epson Corporation S1C17601 Technical Manual
15 1 1.2 TEST bits 1 cycle Internal RAM (2K bytes) Flash memory (32K bytes) Display RAM (20 bytes) CPU Core S1C17 16 bits 1 5 cycles 16 bits 1 cycles 8/16 bits 1 cycle I/O 2 (0x5000 ) Power generator R/F converter A/D converter DCLK, DST2, DSIO(P27 25) VDD, VSS, VD1, VC1 VC3, CA CB RFIN, REF, SENA, SENB(P15 12) RFCLKO(P00) AIN0 3, #ADTRG (P07 04, P03) SVD circuit #TEST Test circuit #RESET Reset circuit I/O 1 (0x4000 ) Interrupt controller 8/16 bits 1 cycle Interrupt system LCD driver MISC register Oscillator/ Clock generator 8-bit OSC1 PWM timer SEG0 16/19, COM0 7/4 LFRO(P00) OSC1 2, OSC3 4 FOUT1(P16), FOUTH(P22) TOUT5(P24) Prescaler Clock timer 8-bit timer Stopwatch timer EXCL0 2 (P02, P4, P5) SIN, SOUT(P21 20 or P24-23) SCLK(P17) 16-bit timer UART (1ch) Watchdog timer 16-bit PWM timer (2ch) EXCL3(P06), EXCL4(P07), TOUT3(P23), TOUT4(P02), TOUTN3(P24) TOUTN4(P01) SDI, SDO, SPICLK(P21 20, P17) #SPISS(P22) SPI SDA0, SCL0(P11 10) I 2 C master (1ch) I/O port/ I/O MUX P00 07, P10 17, P20 27 SDA1, SCL1(P11 10 or P13-14) #BFR(P12) I 2 C slave (1ch) S1C17601 Technical Manual Seiko Epson Corporation 1-3
16 1 1-4 Seiko Epson Corporation S1C17601 Technical Manual TQFP13-64pin INDEX DSIO/P25 DST2/P26 DCLK/P27 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 VC1 VC2 VC3 CA CB COM0 COM1 COM2 COM3 COM4/SEG19 COM5/SEG18 COM6/SEG17 COM7/SEG16 SEG15 SEG14 SEG13 AVDD VSS P05/AIN2/EXCL2 P04/AIN3/EXCL1 P03/#ADTRG P02/TOUT4/EXCL0 P01/TOUTN4 P00/RFCLKO/LFRO #TEST #RESET OSC1 OSC2 VD1 OSC3 OSC4 VDD P06/AIN1/EXCL3 P07/AIN0/EXCL4 P10/SCL0/SCL1 P11/SDA0/SDA1 VDD P12/SENB/#BFR P13/SENA/SDA1 P14/REF/SCL1 P15/RFIN P16/FOUT1 P17/SPICLK/SCLK P20/SDO/SOUT P21/SDI/SIN P22/#SPISS/FOUTH P23/TOUT3/SOUT P24/TOUTN3/SIN/T8OUT TQFP13-64pin
17 1 VFBGA8H-81 A1 Corner Top View Bottom View A1 Corner A B C D E F G H J Index A B C D E F G H J A B P24 P23 P16 P15 P13 P11 P06 N.C. N.C. DST2 DSIO P22 P17 P14 P12 P10 P07 P05 A B C DCLK SEG0 P21 P20 VSS VDD AVDD P04 P03 C D SEG1 SEG2 SEG3 VSS VSS VSS P02 P01 P00 D E SEG6 SEG5 SEG4 VSS VSS VSS #TEST OSC2 OSC1 E F SEG7 SEG8 SEG9 VSS VSS VSS #RESET VSS VD1 F G SEG10 SEG11 SEG15 COM5 COM2 TEST1 VC3 VDD OSC3 G H SEG12 SEG13 COM7 COM4 COM0 TEST2 CA VC1 OSC4 H J SEG14 COM6 COM3 COM1 TEST3 CB VC2 N.C. N.C J VFBGA8H-81 S1C17601 Technical Manual Seiko Epson Corporation 1-5
18 1 CHIP-102pad Y (0,0) X 3.056mm Die No. CJ601D mm 1-6 Seiko Epson Corporation S1C17601 Technical Manual
19 1 PAD No. X (mm) Y (mm) PAD No. X (mm) Y (mm) PAD No. X (mm) Y (mm) DSIO VSS NC DST VDD P NC OSC DCLK OSC NC VSS SEG VD NC OSC SEG OSC NC NC SEG NC NC XRESET SEG NC NC NC SEG XTEST NC NC SEG NC NC P SEG NC NC P SEG NC NC NC SEG P NC NC SEG P NC NC SEG P NC NC SEG P SEG VSS SEG AVDD NC P SEG P NC P SEG P COM NC COM VDD COM P COM P COM P COM P COM VSS COM P TEST NC TEST P TEST P CB P CA NC VC P VC NC VC P23 S1C17601 Technical Manual Seiko Epson Corporation 1-7
20 PAD/ / No. CHIP TQFP VFBGA I/O 1 1 B2 DSIO/P25 I/O I(Pull-UP) *1 / 2 2 B1 DST2/P26 I/O O(L) *1 / 4 3 C1 DCLK/P27 I/O O(H) *1 / * *2 SEG0-15 O O(L) LCD * *3 COM7-4/ O O(L) LCD *1 /LCD SEG16-19 * *3 COM3-0 O O(L) LCD 43 - J6 TEST3 - - OPEN 44 - H6 TEST2 - - OPEN 45 - G6 TEST1 - - OPEN H7 CB - - LCD J7 CA - - LCD G7 VC3 - - LCD J8 VC2 - - LCD H8 VC1 - - LCD 51 - *4 VSS - - (-) *5 VDD - - (+) H9 OSC4 O O OSC G9 OSC3 I I OSC3 VDD-VSS 55 - *4 VSS - - (-) 36 F9 VD E8 OSC2 O O OSC E9 OSC1 I I OSC F7 #RESET I I(Pull-UP) E7 #TEST I I(Pull-UP) (VDD ) D9 P00/RFCLKO/ LFRO I/O I(Pull-UP) *1 /RF /LCD D8 P01/TOUTN4 I/O I(Pull-UP) *1 /T16E Ch1PWM( ) D7 P02/TOUT4/ EXCL0 I/O I(Pull-UP) *1 /T16E Ch1PWM( )/T16 Ch C9 P03/#ADTRG I/O I(Pull-UP) *1 /AD D8 P04/AIN3/ I/O I(Pull-UP) *1 /AD Ch3 /T16 EXCL1 Ch B9 P05/AIN2/ EXCL *4 VSS - - (-) C7 AVDD - - (+) A8 P06/AIN1/ EXCL B8 P07/AIN0/ EXCL B7 P10/SCL0/ SCL A7 P11/SDA0/ SDA1 I/O I(Pull-UP) *1 /AD Ch2 /T16 Ch2 I/O I(Pull-UP) *1 /AD Ch1 /T16E Ch0 I/O I(Pull-UP) *1 /AD Ch0 /T16E Ch1 I/O I(Pull-UP) *1 /I 2 C /I 2 C I/O I(Pull-UP) *1 /I 2 C /I 2 C *4 VDD - - (+) B6 P12/SENB/ I/O I(Pull-UP) *1 /RF/I 2 C #BFR A6 P13/SENA/ SDA1 I/O I(Pull-UP) *1 /RF/I 2 C B5 P14/REF/SCL1 I/O I(Pull-UP) *1 /RF/I 2 C A5 P15/RFIN I/O I(Pull-UP) *1 /RF 91 - *4 VSS - - (-) A4 P16/FOUT1 I/O I(Pull-UP) *1 /OSC B4 P17/SPICLK/ SCLK C4 P20/SDO/ SOUT I/O I(Pull-UP) *1 /SPI /UART I/O I(Pull-UP) *1 /SPI /UART C3 P21/SDI/SIN I/O I(Pull-UP) *1 /SPI /UART 1-8 Seiko Epson Corporation S1C17601 Technical Manual
21 1 PAD/ / No. CHIP TQFP VFBGA B3 P22/#SPISS/ FOUTH A3 P23/TOUT3/ SOUT A2 P24/TOUTN3/ SIN/T8OUT *1: I/O I/O I(Pull-UP) *1 /SPI /HSCLK () I/O I(Pull-UP) *1 /T16E Ch0 PWM( )/UART I/O I(Pull-UP) *1 /T16E Ch0 PWM( )/UART /T8(OSC1) PWM *2: SEG0~15No. VFBGA SEG No No. C2 D1 D2 D3 E3 E2 E1 F1 F2 F3 G1 G2 H1 H2 J2 G3 *3: COM7~0No. VFBGA COM No No. H3 J3 G4 H4 J4 G5 J5 H5 *4: VSSNo. C5, D4, D5, D6, E4, E5, E6, F4, F5, F6, F8 *5: VSSNo. B6, G8 *6: SEG0~15 PAD No. CHIP SEG No PAD No *7: COM7~0 PAD No. CHIP COM No PAD No : VFBGA, CHIP NC pin S1C17601 Technical Manual Seiko Epson Corporation 1-9
22 2 CPU 2 CPU S1C17601 S1C17 S1C17 16 RISC 1 8 CPU S1C17 S1C17 Family S1C S1C17 16 RISC μm CMOS C , 16M NMI 32 HALT halt SLEEP slp S1C17601 Technical Manual Seiko Epson Corporation 2-1
23 2 CPU 2.2 CPU S1C PC 7 SP 6 PSR IL[2:0] IE C V Z N R7 R6 R5 R4 R3 R2 R1 R Seiko Epson Corporation S1C17601 Technical Manual
24 2 CPU 2.3 S1C S1C17 Family S1C S1C17 ld.b %rd,%rs ( ) () %rd,[%rb] %rd,[%rb]+ %rd,[%rb]- %rd,-[%rb] %rd,[%sp+imm7] %rd,[imm7] [%rb],%rs [%rb]+,%rs [%rb]-,%rs -[%rb],%rs [%sp+imm7],%rs ( ) () ( ) () ( ) () ( ) ( ) [imm7],%rs ( ) ld.ub %rd,%rs ( ) () %rd,[%rb] %rd,[%rb]+ %rd,[%rb]- %rd,-[%rb] %rd,[%sp+imm7] ( ) () ( ) () %rd,[imm7] ( ) () ld %rd,%rs (16 ) %rd,sign7 () %rd,[%rb] %rd,[%rb]+ %rd,[%rb]- %rd,-[%rb] %rd,[%sp+imm7] %rd,[imm7] [%rb],%rs [%rb]+,%rs [%rb]-,%rs -[%rb],%rs [%sp+imm7],%rs (16 ) (16 ) (16 ) (16 ) (16 ) [imm7],%rs (16 ) ld.a %rd,%rs (24 ) %rd,imm7 () %rd,[%rb] (32 ) (*1) %rd,[%rb]+ %rd,[%rb]- %rd,-[%rb] %rd,[%sp+imm7] (32 ) (*1) %rd,[imm7] (32 ) (*1) [%rb],%rs (32) (*1) [%rb]+,%rs [%rb]-,%rs -[%rb],%rs [%sp+imm7],%rs (32) (*1) [imm7],%rs (32) (*1) %rd,%sp SP %rd,%pc PC %rd,[%sp] (32 ) (*1) %rd,[%sp]+ %rd,[%sp]- %rd,-[%sp] S1C17601 Technical Manual Seiko Epson Corporation 2-3
25 2 CPU ld.a [%sp],%rs (32) (*1) [%sp]+,%rs [%sp]-,%rs -[%sp],%rs %sp,%rs (24 ) SP %sp,imm7 SP add %rd,%rs 16 add/c add/nc add %rd,imm7 (/c: C = 1, /nc: C = 0 ) 16 add.a %rd,%rs 24 add.a/c (/c: C = 1, /nc: C = 0 ) add.a/nc add.a %sp,%rs SP24 %rd,imm7 24 %sp,imm7 SP24 adc %rd,%rs 16 adc/c adc/nc adc %rd,imm7 (/c: C = 1, /nc: C = 0 ) 16 sub %rd,%rs 16 sub/c sub/nc sub %rd,imm7 (/c: C = 1, /nc: C = 0 ) 16 sub.a %rd,%rs 24 sub.a/c sub.a/nc sub.a %sp,%rs (/c: C = 1, /nc: C = 0 ) SP24 %rd,imm7 24 %sp,imm7 SP24 sbc %rd,%rs 16 sbc/c sbc/nc sbc %rd,imm7 (/c: C = 1, /nc: C = 0 ) 16 cmp %rd,%rs 16 cmp/c cmp/nc cmp %rd,sign7 (/c: C = 1, /nc: C = 0 ) 16 cmp.a %rd,%rs 24 cmp.a/c cmp.a/nc cmp.a %rd,imm7 (/c: C = 1, /nc: C = 0 ) 24 cmc %rd,%rs 16 cmc/c cmc/nc cmc %rd,sign7 (/c: C = 1, /nc: C = 0 ) 16 and %rd,%rs and/c and/nc and %rd,sign7 (/c: C = 1, /nc: C = 0 ) or %rd,%rs or/c or/nc or %rd,sign7 (/c: C = 1, /nc: C = 0 ) xor %rd,%rs xor/c xor/nc xor %rd,sign7 (/c: C = 1, /nc: C = 0 ) not %rd,%rs (1 ) not/c not/nc not %rd,sign7 (/c: C = 1, /nc: C = 0 ) (1 ) 2-4 Seiko Epson Corporation S1C17601 Technical Manual
26 2 CPU & sr %rd,%rs () %rd,imm7 ( ) sa %rd,%rs () %rd,imm7 ( ) sl %rd,%rs () %rd,imm7 ( ) swap %rd,%rs 16 ext imm13 cv.ab %rd,%rs 8 24 cv.as %rd,%rs cv.al %rd,%rs cv.la %rd,%rs cv.ls %rd,%rs sign10 jpr jpr.d jpa jpa.d jrgt jrgt.d jrge jrge.d jrlt jrlt.d jrle jrle.d jrugt jrugt.d jruge jruge.d jrult jrult.d jrule jrule.d jreq jreq.d jrne jrne.d call call.d calla calla.d ret ret.d PC %rb imm7 %rb sign7 PC :!Z &!(N ^ V) sign7 PC :!(N ^ V) sign7 PC : N ^ V sign7 PC : Z N ^ V sign7 PC :!Z &!C sign7 PC :!C sign7 PC : C sign7 PC : Z C sign7 PC : Z sign7 PC :!Z sign10 PC %rb imm7 %rb int imm5 intl imm5,imm3 reti reti.d brk retd nop halt HALT slp SLEEP ei di ld.cw %rd,%rs %rd,imm7 ld.ca %rd,%rs %rd,imm7 ld.cf %rd,%rs %rd,imm7 *1 ld.a S1C17601 Technical Manual Seiko Epson Corporation 2-5
27 2 CPU %rs %rd [%rb] [%rb]+ [%rb]- -[%rb] %sp [%sp],[%sp+imm7] [%sp]+ [%sp]- -[%sp] imm3,imm5,imm7,imm13 sign7,sign () ( ) ( ) () ( ) ( ) ( ) ( ) 2-6 Seiko Epson Corporation S1C17601 Technical Manual
28 2 CPU 2.4 S1C17 6. ITC MISC_TTBRL MISC_TTBRH 0x5328 0x532a TTBR MISC_TTBRL/MISC_TTBRH 0x8000 MISC_TTBRL x5328 0x532a: Vector Table Address Low/High Registers (MISC_TTBRL, MISC_TTBRH) Register name Address Bit Name Function Setting Init. R/W Remarks Vector Table 0x5328 D15 8 TTBR[15:8] Vector table base address A[15:8] 0x0 0xff 0x80 R/W Address Low Register (MISC_TTBRL) (16 bits) D7 0 TTBR[7:0] Vector table base address A[7:0] (fixed at 0) 0x0 0x0 R Vector Table Address High Register (MISC_TTBRH) 0x532a (16 bits) D15 8 reserved 0 when being read. D7 0 TTBR[23:16] Vector table base address A[23:16] 0x0 0xff 0x0 R/W : MISC_TTBRL/MISC_TTBRH MISC Protect Register 0x5324 0x96 MISC_TTBRL/MISC_TTBRH MISC Protect Register 0x5324 0x96 S1C17601 Technical Manual Seiko Epson Corporation 2-7
29 2 CPU 2.5 PSR S1C17601 S1C17 PSR Processor Status RegisterPSR Register 0x532c PSR PSR 0x532c: PSR Register (MISC_PSR) Register name Address Bit Name Function Setting Init. R/W Remarks PSR Register (MISC_PSR) 0x532c (16 bits) D15 8 reserved 0 when being read. D7 5 PSRIL[2:0] PSR interrupt level (IL) bits 0x0 to 0x7 0x0 R D4 PSRIE PSR interrupt enable (IE) bit 1 1 (enable) 0 0 (disable) 0 R D3 PSRC PSR carry (C) flag 1 1 (set) 0 0 (cleared) 0 R D2 PSRV PSR overflow (V) flag 1 1 (set) 0 0 (cleared) 0 R D1 PSRZ PSR zero (Z) flag 1 1 (set) 0 0 (cleared) 0 R D0 PSRN PSR negative (N) flag 1 1 (set) 0 0 (cleared) 0 R D[7:5] D4 D3 D2 D1 D0 PSRIL[2:0]: PSR Interrupt Level (IL) Bits PSR IL: 0x0 PSRIE: PSR Interrup Enable (IE) Bit PSR IE 1 R : 1 0 R : 0 PSRC: PSR Carry (C) Flag PSR C 1 R : 1 0 R : 0 PSRV: PSR Overflow (V) Flag PSR V 1 R : 1 0 R : 0 PSRZ: PSR Zero (Z) Flag PSR Z 1 R : 1 0 R : 0 PSRN: PSR Negative (N) Flag PSR N 1 R : 1 0 R : Seiko Epson Corporation S1C17601 Technical Manual
30 2 CPU 2.6 S1C17601 Processor ID Register 0xffff84 CPU 0xffff84: Processor ID Register (IDIR) Register name Address Bit Name Function Setting Init. R/W Remarks Processor ID Register (IDIR) 0xffff84 (8 bits) D7 0 IDIR[7:0] Processor ID 0x10: S1C17 Core 0x10 0x10 R ID S1C17 ID 0x10 S1C17601 Technical Manual Seiko Epson Corporation 2-9
31 3, 3, 3.1 S1C17601 ( ) 0xff ffff 0xff fc00 0xff fbff 0x x00 ffff 0x x00 7fff 0x x00 5fff 0x x00 4fff 0x x00 43ff 0x x00 3fff 0x x00 07ff 0x00 07c0 0x I/O (1K, 1) reserved Flash (32K, 1~5) ( : 16 ) reserved 2 (4K, 1) reserved 1 (1K, 1) reserved RAM (64 ) RAM (2K, 1) ( : 32 ) 0x5400~0x5fff reserved 0x53c0~0x53ff LCD 0x53a0~0x53bf R/F 0x5380~0x539f A/D 0x5360~0x537f PWM Ch.1 0x5340~0x535f reserved 0x5320~0x533f MISC 0x5300~0x531f PWM Ch.0 0x52c0~0x52ff reserved 0x52a0~0x52bf MUX 0x5280~0x529f reserved 0x5200~0x527f P 0x5140~0x51ff reserved 0x5120~0x513f 0x5100~0x511f SVD 0x50e0~0x50ff reserved 0x50c0~0x50df 8 OSC1 0x50a0~0x50bf LCD 0x5080~0x509f 0x5060~0x507f 0x5040~0x505f 0x5020~0x503f 0x5000~0x501f 0x4380~0x43ff reserved 0x4360~0x437f I 2 C 0x4340~0x435f I 2 C 0x4320~0x433f SPI 0x42c0~0x431f 0x4280~0x42ff reserved 0x4260~0x427f 16 Ch.2 0x4240~0x425f 16 Ch.1 0x4220~0x423f 16 Ch.0 0x4200~0x421f 8 0x4120~0x41ff reserved 0x4100~0x411f UART 0x4040~0x40ff reserved 0x4020~0x403f 0x4000~0x401f reserved (16 ) (16 ) (16 ) (16 ) (16 ) (16 ) (8 ) (8 ) (8 ) (8 ) (8 ) (8 ) (8 ) (8 ) (8 ) (8 ) (8 ) (16 ) (16 ) (16 ) (16 ) (16 ) (16 ) (16 ) (16 ) (8 ) (8 ) 3.1 S1C17601 S1C17601 Technical Manual Seiko Epson Corporation 3-1
32 3, 3.1 CPU CCLK CCLK 8.2 CPU CCLK CCLK 1 CCLK CPU CPU * * * 1 * PSR / Flash Flash Flash Flash RAM RAM 3-2 Seiko Epson Corporation S1C17601 Technical Manual
33 3, 3.2 Flash Flash 0x80000xffff 32KFlash4K 8 0x MISC_TTBRL/MISC_TTBRH 0x5328 0x532a Flash Flash S1C17601 FlashICD S5U1C17001H / 16 Flash Appendix B Flash 2 : Flash S1C17601 Flash 0xf000~0xffff 7 0xe000~0xefff 6 0xd000~0xdfff 5 0xc000~0xcfff 4 0xb000~0xbfff 3 0xa000~0xafff 2 0x9000~0x9fff 1 0x8000~0x8fff 0 : 7 320xfffc 0xffff Flash 2 16K 0x0000 CPU 0 S1C17601 Technical Manual Seiko Epson Corporation 3-3
34 3, 0xfffc 0xfffe: Flash Protect Bits Address Bit Function Setting Init. R/W Remarks 0xfffc (16 bits) 0xfffe (16 bits) D15 2 reserved D1 Flash write-protect bit for 0x0c000 0x0ffff 1 Writable 0 Protected 1 R/W D0 Flash write-protect bit for 0x x0bfff 1 Writable 0 Protected 1 R/W D15 2 reserved D1 Flash data-read-protect bit for 0x0c000 0x0ffff 1 Readable 0 Protected 1 R/W D0 reserved 1 1 R/W 1 :.data.rodata 0xfffe D Flash S1C17601 FlashFlash MISC Flash Flash CCLK FLCYC[2:0] D[2:0]/MISC_FL 0x5320: FLASHC Control Register (MISC_FL) Register name Address Bit Name Function Setting Init. R/W Remarks FLASHC/ SRAMC Control Register (MISC_FL) 0x5320 (16 bits) D15 10 reserved 0 when being read. D9 8 reserved 0x3 D7 3 reserved 0 when being read. D2 0 FLCYC[2:0] FLASHC read access cycle FLCYC[2:0] Read cycle 0x3 R/W 0x7 0x5 0x4 0x3 0x2 0x1 0x0 reserved 1 cycles 5 cycles 4 cycles 3 cycles 2 cycles D[2:0] FLCYC[2:0]: FLASHC Read Access Cycle Setup Bits Flash Flash FLCYC[2:0] CCLK 0x7 0x5 Reserved 0x MHz max. 0x MHz max. 0x MHz max. 0x MHz max. 0x MHz max. : 0x3 : CCLK FLCYC[2:0]=0x4 3-4 Seiko Epson Corporation S1C17601 Technical Manual
35 3, 3.3 RAM RAM 0x00x7ff 2KRAMRAM/ 1RAM : RAM 640x7c0 0x7ff S1C17601 RAM 2KB 1KB 512B S1C17601 ROM RAM RAM IRAMSZ[2:0] D[2:0]/MISC_IRAMSZ RAM2KB 0x5326: IRAM Size Select Register (MISC_IRAMSZ) Register name Address Bit Name Function Setting Init. R/W Remarks IRAM Size 0x5326 D15 3 reserved 0 when being read. Select Register (16 bits) D8 DBADR Debug base address select 1 0x0 0 0xfffc00 0 R/W (MISC_IRAMSZ) D6 4 IRAMACTSZ IRAM actual size register 0x3:2KB 0x3 R [2:0] D2 0 IRAMSZ[2:0] IRAM size select IRAMSZ[2:0] Read cycle 0x3 R/W 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reserved reserved 512B 1KB 2KB reserved reserved reserved D[6:4] D[2:0] IRAMACTSZ[2:0]: IRAM Actual Size Bits RAM IRAMSZ[2:0]: IRAM Size Select Bits RAM RAM IRAMSZ[2:0] RAM 0x7 reserved 0x6 reserved 0x5 512B 0x4 1KB 0x3 2KB 0x2 reserved 0x1 reserved 0x0 reserved : 0x3 : IRAM Size Select Register MISC Protect Register 0x5324 0x96 IRAM Size Select Register MISC Protect Register 0x5324 0x96 S1C17601 Technical Manual Seiko Epson Corporation 3-5
36 3, 3.4 RAM RAM 0x53c00x53d3 20 LCDRAM 16 RAM 1 RAM Seiko Epson Corporation S1C17601 Technical Manual
37 3, 3.5 0x4000 1K 0x5000 4K I/O x4000~ 0x40001I/O 1 PSC, 8 UART UART, 8 8 T8F, T16, 16 ITC, 16 SPI SPI, 16 I 2 CI2C, 16 I 2 C I2C, x5000~ 0x50002I/O 1 CT, 8 SWT, 8 WDT, 8 OSC, 8 CLG, 8 LCD LCD, 8 8 OSC1 PWMT8OSC1, 8 SVD SVD, 8 VD1, 8 & MUX P, 8 PWMT16E, 16 MISC MISC, 16 A/DADC10, 16 R/FRFC, 16 LCD SEGRAM, 16 S1C17601 Technical Manual Seiko Epson Corporation 3-7
38 3, 3.6 I/O 0xfffc00 0xffffff 1KCPU I/O I/O I/O I/O S1C17 I/O 0xffff84 IDIR Processor ID Register ID 0xffff90 DBRAM Debug RAM Base Register RAM 0xffffa0 DCR Debug Control Register 0xffffb8 IBAR2 Instruction Break Address Register 2 #2 0xffffbc IBAR3 Instruction Break Address Register 3 #3 0xffffd0 IBAR4 Instruction Break Address Register 4 #4 IDIR DBG S1C17 S1C Seiko Epson Corporation S1C17601 Technical Manual
39 S1C17601 : 1.8V 3.6V Flash: 2.7V 3.6V VSS GND VDD S1C17601 TQFP13-64pin 2 VDD 1 VSSVFBGA8H-81 2 VDD 11 VSS + GND (AVDD) A/D AVDD AVDD VSS GND AVDD VDD AVDD = VDDE, VSS = GND : AVDD VDD A/D S1C17601 Technical Manual Seiko Epson Corporation 4-1
40 4 4.2 S1C IC VD1 LCD LCD VC1 VC3 VDD VD1 VD1MD HVLD VD1 OSC1, OSC2 OSC3, OSC4 VDD VC1 VC2 VC3 CA CB LCD VC1~VC3 LHVLD LCD COM0~COM7 SEG0~SEG15 VSS VCSEL : VD1 VC1 VC3 VD1 VD1 1.8V Flash 2.5V LCD LCD LCD 1/3 VC1 VC2 VC3 S1C17601 LCD LCD / LCD VDD VCSEL LVDD VCSEL VDD VCSEL V V 1 : VDD 2.5V VCSEL 1 VC1 VC3 4-2 Seiko Epson Corporation S1C17601 Technical Manual
41 4 4.3 S1C VDD = V VD1 = 1.8V 2. Flash / Flash/ VDD = V VD1 = 2.5V VD1 VD1MD D0/VD1_CTL VD1MD 0 VD1 = 1.8V Flash / VD1MD 1 * VD1MD: Flash Erase/Program Mode Bit in the VD1 Control (VD1_CTL) Register (D0/0x5120) : 5ms max. Flash LCD LCDVC1 VC3 DSPC[1:0] D[1:0]/LCD_DCTL 0x0 Off LCD * DSPC[1:0]: LCD Display Control Bits in the LCD Display Control (LCD_DCTL) Register (D[1:0]/0x50a0) LCD LCD Off DSPC[1:0] VDD LCD VD1MD VCSEL DSPC[1:0] V 0 0 0x V 0 1 0x V 0 0 0x0 Flash / V () V 1 1 0x V 1 0 0x0 DSPC[1:0] x50a0: LCD Display Control Register (LCD_DCTL) S1C17601 Technical Manual Seiko Epson Corporation 4-3
42 4 4.4 LCD LCD HVLD D5/VD1_CTL 1 VD1 10μsec HALT/SLEEP : * HVLD: VD1 Heavy Load Protection Mode Bit in the VD1 Control (VD1_CTL) Register (D5/0x5120) LCD LHVLD D4/LCD_VREG 1 VC1 VC3 * LHVLD: LCD Heavy Load Protection Mode Bit in the LCD Voltage Regulator Control (LCD_VREG) Register (D4/0x50a3) : 4-4 Seiko Epson Corporation S1C17601 Technical Manual
43 x5120 VD1_CTL VD1 Control Register VD1 0x50a3 LCD_VREG LCD Voltage Regulator Control Register LCD 8 : Reserved 0 1 S1C17601 Technical Manual Seiko Epson Corporation 4-5
44 4 0x5120: VD1 Control Register (VD1_CTL) Register name Address Bit Name Function Setting Init. R/W Remarks VD1 Control Register (VD1_CTL) D[7:6] D5 D[4:1] D0 0x5120 (8 bits) Reserved D7 6 reserved 0 when being read. D5 HVLD VD1 heavy load protection mode 1 On 0 Off 0 R/W D4 reserved 0 R/W D3 1 reserved 0 when being read. D0 VD1MD Flash erase/program mode 1 Flash (2.5 V) 0 Norm.(1.8 V) 0 R/W HVLD: VD1 Heavy Load Protection Mode Bit 1 R/W : On 0 R/W : Off HVLD 1 VD1 Reserved VD1MD: Flash Erase/Program Mode Bit VD1 1 R/W : VD1 = 2.5V Flash / 0 R/W : VD1 = 1.8V VD1MD 0 VD1 = 1.8V Flash / VD1MD 1 : 5ms max. Flash 4-6 Seiko Epson Corporation S1C17601 Technical Manual
45 4 0x50a3: LCD Voltage Regulator Control Register (LCD_VREG) Register name Address Bit Name Function Setting Init. R/W Remarks LCD Voltage Regulator Control Register (LCD_VREG) 0x50a3 (8 bits) D7 5 reserved 0 when being read. D4 LHVLD LCD heavy load protection mode 1 On 0 Off 0 R/W D3 1 reserved 0 when being read. D0 VCSEL Power source select for LCD voltage regulator 1 VC = 2V 0 VC = 1V 0 R/W D[7:5] D4 D[3:1] D0 Reserved LHVLD: LCD Heavy Load Protection Mode Bit LCD 1 R/W : On 0 R/W : Off LCD LHVLD 1 VC1 VC3 Reserved VCSEL: Power Source Select for LCD Voltage Regulator VDD 1 R/W : VDD V 0 R/W : VDD V S1C17601 Technical Manual Seiko Epson Corporation 4-7
46 4 4.6 VD1 VC1 VC3 VDD 2.5V VCSEL 1 VC1 VC3 Flash / 5ms max. Flash 4-8 Seiko Epson Corporation S1C17601 Technical Manual
47 S1C #RESET 2 P0P00 P VDD S Q #RESET R P00 P01 P02 P03 P0KRST WDTMD CPU CPU #RESET #RESET Low S1C17601 #RESET Low 28.4 #RESET Low HighCPU #RESET S1C17601 Technical Manual Seiko Epson Corporation 5-1
48 P0 P00 P03 Low P0KRST[1:0] D[1:0]/P0_KRST * P0KRST[1:0]: P0 Port Key-Entry Reset Configuration Bits in the P0 Port Key-Entry Reset Configuration (P0_KRST) Register (D[1:0]/0x5209) P0 P0KRST[1:0] 0x3 0x2 0x1 0x0 P00, P01, P02, P03 P00, P01, P02 P00, P01 P0KRST[1:0] 0x3P00 P03 4 Low : P0Low P S1C17601 CPU 4 CPU NMI WDTMD D1/WDT_ST 1WDTMD 0NMI * WDTMD: NMI/Reset Mode Select Bit in the Watchdog Timer Status (WDT_ST) Register (D1/0x5041) 17 WDT : Seiko Epson Corporation S1C17601 Technical Manual
49 5 5.2 #RESETCPU CPU IOSC CR * fiosc: IOSC : SLEEP IOSC #RESET S1C17601 Technical Manual Seiko Epson Corporation 5-3
50 5 5.3 CPU R0 R7: 0x0 PSR: 0x0 = 0 SP: 0x0 PC: RAM Appendix I/O 5-4 Seiko Epson Corporation S1C17601 Technical Manual
51 6 ITC 6 ITC 6.1 ITC ITC / S1C17 NMI S1C17601 Technical Manual Seiko Epson Corporation 6-1
52 6 ITC 6.2 S1C17 MISC_TTBRL MISC_TTBRH 0x5328 0x532a TTBR MISC_TTBRL/MISC_TTBRH 0x S1C No./ No. 0 (0x00) TTBR + 0x00 #RESETLow *2 1 (0x01) TTBR + 0x04 2 (0xfffc00) brk 3 2 (0x02) TTBR + 0x08 NMI *2 4 3 (0x03) TTBR + 0x0c C reserved C 4 (0x04) TTBR + 0x10 P0 P00~P07 *1 5 (0x05) TTBR + 0x14 P1 P10~P17 6 (0x06) TTBR + 0x18 100Hz 10Hz 1Hz 7 (0x07) TTBR + 0x1c 32Hz 8Hz 2Hz 1Hz 8 (0x08) TTBR + 0x20 8 OSC1 9 (0x09) TTBR + 0x24 SVD 10 (0x0a) TTBR + 0x28 LCD 11 (0x0b) TTBR + 0x2c PWM Ch.0 A B 12 (0x0c) TTBR + 0x (0x0d) TTBR + 0x34 16 Ch.0 14 (0x0e) TTBR + 0x38 16 Ch.1 15 (0x0f) TTBR + 0x3c 16 Ch.2 16 (0x10) TTBR + 0x40 UART 17 (0x11) TTBR + 0x44 I 2 C I 2 C I 2 C I 2 C 18 (0x12) TTBR + 0x48 SPI 19 (0x13) TTBR + 0x4c I 2 C 20 (0x14) TTBR + 0x50 PWM Ch.1 A B 21 (0x15) TTBR + 0x54 reserved 22 (0x16) TTBR + 0x58 A/D 23 (0x17) TTBR + 0x5c R/F A B 24 (0x18) TTBR + 0x60 reserved : : : : 31 (0x1f) TTBR + 0x7c reserved *1 *1 *2 NMI 4 20, S1C Seiko Epson Corporation S1C17601 Technical Manual
53 6 ITC ITC S1C17 0 1ITC 1 ITC1 reti ITC ITC S1C ITC S1C17 ILPSR S1C ITC0 0 S1C17 ITC P0 ILV0[2:0] D[2:0]/ITC_LV0 0x4306 P1 ILV1[2:0] D[10:8]/ITC_LV0 0x4306 ILV2[2:0] D[2:0]/ITC_LV1 0x4308 ILV3[2:0] D[10:8]/ITC_LV1 0x OSC1 ILV4[2:0] D[2:0]/ITC_LV2 0x430a SVD ILV5[2:0] D[10:8]/ITC_LV2 0x430a LCD ILV6[2:0] D[2:0]/ITC_LV3 0x430c PWM Ch.0 ILV7[2:0] D[10:8]/ITC_LV3 0x430c 8 ILV8[2:0] D[2:0]/ITC_LV4 0x430e 16 Ch.0 ILV9[2:0] D[10:8]/ITC_LV4 0x430e 16 Ch.1 ILV10[2:0] D[2:0]/ITC_LV5 0x Ch.2 ILV11[2:0] D[10:8]/ITC_LV5 0x4310 UART ILV12[2:0] D[2:0]/ITC_LV6 0x4312 I 2 C ILV13[2:0] D[10:8]/ITC_LV6 0x4312 SPI ILV14[2:0] D[2:0]/ITC_LV7 0x4314 I 2 C ILV15[2:0] D[10:8]/ITC_LV7 0x4314 PWM Ch.1 ILV16[2:0] D[2:0]/ITC_LV8 0x4316 reserved ILV17[2:0] D[10:8]/ITC_LV8 0x4316 A/D ILV18[2:0] D[2:0]/ITC_LV9 0x4318 R/F ILV19[2:0] D[10:8]/ITC_LV9 0x4318 S1C17601 Technical Manual Seiko Epson Corporation 6-3
54 6 ITC ITC ITC S1C S1C17 ITC S1C17 S1C17 ITC S1C17 S1C17 PSR S1C17IE 1 PSR IL NMI 1 S1C17 S1C17 S1C17 1 PSRPC 2 PSR IE0 3 PSR IL NMI 4PC 2 IE1 3 IL reti PSR 6-4 Seiko Epson Corporation S1C17601 Technical Manual
55 6 ITC 6.4 NMI S1C17601 NMI NMI S1C17 NMI 17 WDT S1C17601 Technical Manual Seiko Epson Corporation 6-5
56 6 ITC 6.5 S1C17 int imm5 intl imm5,imm3 imm intl imm3 PSR IL Seiko Epson Corporation S1C17601 Technical Manual
57 6 ITC 6.6 HALT, SLEEP HALT SLEEP CPU ITC CPU NMI ITC CPU HALT SLEP CPU halt slp ITC HALT SLEP Appendix C C.1 S1C17601 Technical Manual Seiko Epson Corporation 6-7
58 6 ITC ITC 0x4306 ITC_LV0 Interrupt Level Setup Register 0 P0 P1 0x4308 ITC_LV1 Interrupt Level Setup Register 1 SWT CT 0x430a ITC_LV2 Interrupt Level Setup Register 2 T8OSC1 SVD 0x430c ITC_LV3 Interrupt Level Setup Register 3 LCD T16E Ch.0 0x430e ITC_LV4 Interrupt Level Setup Register 4 T8F T16 Ch.0 0x4310 ITC_LV5 Interrupt Level Setup Register 5 T16 Ch.1 Ch.2 0x4312 ITC_LV6 Interrupt Level Setup Register 6 UART I 2 C 0x4314 ITC_LV7 Interrupt Level Setup Register 7 SPI I 2 C 0x4316 ITC_LV8 Interrupt Level Setup Register 8 T16E Ch.1 0x4318 ITC_LV9 Interrupt Level Setup Register 9 A/D R/F ITC 16 : Reserved Seiko Epson Corporation S1C17601 Technical Manual
59 6 ITC 0x4306: Interrupt Level Setup Register 0 (ITC_LV0) Register name Address Bit Name Function Setting Init. R/W Remarks Interrupt Level 0x4306 Setup Register 0 (16 bits) (ITC_LV0) D[15:11] Reserved D15 11 reserved 0 when being read. D10 8 ILV1[2:0] P1 interrupt level 0 to 7 0x0 R/W D7 3 reserved 0 when being read. D2 0 ILV0[2:0] P0 interrupt level 0 to 7 0x0 R/W D[10:8] D[7:3] D[2:0] ILV1[2:0]: P1 Port Interrupt Level Bits P10 7 : 0 S1C17PSR IL ITC ITC ITC_LVx 0x4306 0x4318 S1C17 S1C17 ITC S1C17 S1C17 ITC Reserved ILV0[2:0]: P0 Port Interrupt Level Bits P00 7 : 0 ILV1[2:0] D[10:8] S1C17601 Technical Manual Seiko Epson Corporation 6-9
60 6 ITC 0x4308: Interrupt Level Setup Register 1 (ITC_LV1) Register name Address Bit Name Function Setting Init. R/W Remarks Interrupt Level 0x4308 Setup Register 1 (16 bits) (ITC_LV1) D[15:11] Reserved D15 11 reserved 0 when being read. D10 8 ILV3[2:0] CT interrupt level 0 to 7 0x0 R/W D7 3 reserved 0 when being read. D2 0 ILV2[2:0] SWT interrupt level 0 to 7 0x0 R/W D[10:8] D[7:3] D[2:0] ILV3[2:0]: Clock Timer Interrupt Level Bits 0 7 : 0 ITC_LV0 0x4306 ILV1[2:0] D[10:8] Reserved ILV2[2:0]: Stopwatch Timer Interrupt Level Bits 0 7 : 0 ITC_LV0 0x4306 ILV1[2:0] D[10:8] 6-10 Seiko Epson Corporation S1C17601 Technical Manual
61 6 ITC 0x430a: Interrupt Level Setup Register 2 (ITC_LV2) Register name Address Bit Name Function Setting Init. R/W Remarks Interrupt Level 0x430a Setup Register 2 (16 bits) (ITC_LV2) D[15:11] Reserved D15 11 reserved 0 when being read. D10 8 ILV5[2:0] SVD interrupt level 0 to 7 0x0 R/W D7 3 reserved 0 when being read. D2 0 ILV4[2:0] T8OSC1 interrupt level 0 to 7 0x0 R/W D[10:8] D[7:3] D[2:0] ILV5[2:0]: SVD Interrupt Level Bits SVD 0 7 : 0 ITC_LV0 0x4306 ILV1[2:0] D[10:8] Reserved ILV4[2:0]: 8-bit OSC1 Timer Interrupt Level Bits 8 OSC10 7 : 0 ITC_LV0 0x4306 ILV1[2:0] D[10:8] S1C17601 Technical Manual Seiko Epson Corporation 6-11
62 6 ITC 0x430c: Interrupt Level Setup Register 3 (ITC_LV3) Register name Address Bit Name Function Setting Init. R/W Remarks Interrupt Level 0x430c Setup Register 3 (16 bits) (ITC_LV3) D[15:11] Reserved D15 11 reserved 0 when being read. D10 8 ILV7[2:0] T16E Ch.0 interrupt level 0 to 7 0x0 R/W D7 3 reserved 0 when being read. D2 0 ILV6[2:0] LCD interrupt level 0 to 7 0x0 R/W D[10:8] D[7:3] D[2:0] ILV7[2:0]: PWM & Capture Timer Ch.0 Interrupt Level Bits PWM Ch : 0 ITC_LV0 0x4306 ILV1[2:0] D[10:8] Reserved ILV6[2:0]: LCD Interrupt Level Bits LCD 0 7 : 0 ITC_LV0 0x4306 ILV1[2:0] D[10:8] 6-12 Seiko Epson Corporation S1C17601 Technical Manual
63 6 ITC 0x430e: Interrupt Level Setup Register 4 (ITC_LV4) Register name Address Bit Name Function Setting Init. R/W Remarks Interrupt Level 0x430e Setup Register 4 (16 bits) (ITC_LV4) D[15:11] Reserved D15 11 reserved 0 when being read. D10 8 ILV9[2:0] T16 Ch.0 interrupt level 0 to 7 0x0 R/W D7 3 reserved 0 when being read. D2 0 ILV8[2:0] T8F interrupt level 0 to 7 0x0 R/W D[10:8] D[7:3] D[2:0] ILV9[2:0]: 16-bit Timer Ch.0 Interrupt Level Bits 16 Ch : 0 ITC_LV0 0x4306 ILV1[2:0] D[10:8] Reserved ILV8[2:0]: 8-bit Timer Interrupt Level Bits : 0 ITC_LV0 0x4306 ILV1[2:0] D[10:8] S1C17601 Technical Manual Seiko Epson Corporation 6-13
64 6 ITC 0x4310: Interrupt Level Setup Register 5 (ITC_LV5) Register name Address Bit Name Function Setting Init. R/W Remarks Interrupt Level 0x4310 Setup Register 5 (16 bits) (ITC_LV5) D[15:11] Reserved D15 11 reserved 0 when being read. D10 8 ILV11[2:0] T16 Ch.2 interrupt level 0 to 7 0x0 R/W D7 3 reserved 0 when being read. D2 0 ILV10[2:0] T16 Ch.1 interrupt level 0 to 7 0x0 R/W D[10:8] D[7:3] D[2:0] ILV11[2:0]: 16-bit Timer Ch.2 Interrupt Level Bits 16 Ch : 0 ITC_LV0 0x4306 ILV1[2:0] D[10:8] Reserved ILV10[2:0]: 16-bit Timer Ch.1 Interrupt Level Bits 16 Ch : 0 ITC_LV0 0x4306 ILV1[2:0] D[10:8] 6-14 Seiko Epson Corporation S1C17601 Technical Manual
65 6 ITC 0x4312: Interrupt Level Setup Register 6 (ITC_LV6) Register name Address Bit Name Function Setting Init. R/W Remarks Interrupt Level 0x4312 Setup Register 6 (16 bits) (ITC_LV6) D[15:11] Reserved D15 11 reserved 0 when being read. D10 8 ILV13[2:0] I 2 C (slave) interrupt level 0 to 7 0x0 R/W D7 3 reserved 0 when being read. D2 0 ILV12[2:0] UART interrupt level 0 to 7 0x0 R/W D[10:8] D[7:3] D[2:0] ILV13[2:0]: I 2 C (slave) Interrupt Level Bits I 2 C slave 0 7 : 0 ITC_LV0 0x4306 ILV1[2:0] D[10:8] Reserved ILV12[2:0]: UART Interrupt Level Bits UART Ch : 0 ITC_LV0 0x4306 ILV1[2:0] D[10:8] S1C17601 Technical Manual Seiko Epson Corporation 6-15
66 6 ITC 0x4314: Interrupt Level Setup Register 7 (ITC_LV7) Register name Address Bit Name Function Setting Init. R/W Remarks Interrupt Level 0x4314 Setup Register 7 (16 bits) (ITC_LV7) D[15:11] Reserved D15 11 reserved 0 when being read. D10 8 ILV15[2:0] I 2 C (master) interrupt level 0 to 7 0x0 R/W D7 3 reserved 0 when being read. D2 0 ILV14[2:0] SPI interrupt level 0 to 7 0x0 R/W D[10:8] D[7:3] D[2:0] ILV15[2:0]: I 2 C (master) Interrupt Level Bits I 2 C 0 7 : 0 ITC_LV0 0x4306 ILV1[2:0] D[10:8] Reserved ILV14[2:0]: SPI Interrupt Level Bits SPI 0 7 : 0 ITC_LV0 0x4306 ILV1[2:0] D[10:8] 6-16 Seiko Epson Corporation S1C17601 Technical Manual
67 6 ITC 0x4316: Interrupt Level Setup Register 8 (ITC_LV8) Register name Address Bit Name Function Setting Init. R/W Remarks Interrupt Level 0x4316 Setup Register 8 (16 bits) (ITC_LV8) D15 3 reserved 0 when being read. D2 0 ILV16[2:0] T16E Ch.1 interrupt level 0 to 7 0x0 R/W D[15:3] D[2:0] Reserved ILV16[2:0]: PWM & Capture Timer Ch.1 Interrupt Level Bits PWM Ch : 0 ITC_LV0 0x4306 ILV1[2:0] D[10:8] S1C17601 Technical Manual Seiko Epson Corporation 6-17
68 6 ITC 0x4318: Interrupt Level Setup Register 9 (ITC_LV9) Register name Address Bit Name Function Setting Init. R/W Remarks Interrupt Level 0x4318 Setup Register 9 (16 bits) (ITC_LV9) D[15:11] Reserved D15 11 reserved 0 when being read. D10 8 ILV19[2:0] R/F converter interrupt level 0 to 7 0x0 R/W D7 3 reserved 0 when being read. D2 0 ILV18[2:0] A/D converter interrupt level 0 to 7 0x0 R/W D[10:8] D[7:3] D[2:0] ILV19[2:0]: R/F Converter Interrupt Level Bits R/F 0 7 : 0 ITC_LV0 0x4306 ILV1[2:0] D[10:8] Reserved ILV18[2:0]: A/D Convertere Interrupt Level Bits A/D0 7 : 0 ITC_LV0 0x4306 ILV1[2:0] D[10:8] 6-18 Seiko Epson Corporation S1C17601 Technical Manual
69 6 ITC 6.8 PSR reti S1C17601 Technical Manual Seiko Epson Corporation 6-19
70 7 OSC 7 OSC 7.1 OSC S1C IOSC OSC3 OSC1 IOSC OSC3 S1C17 OSC1 IOSC On/Off IOSC/OSC3 OSC OSC OSC3 OSC4 FOUTH OSC1 OSC2 SLEEP, On/Off IOSC OSC3 SLEEP, On/Off FOUTH On/Off SLEEP, On/Off OSC1 wakeup wakeup (1/1~1/4) OSC HSCLK IOSC HSCLK OSC3 OSC1 (1/1~1/8) On/Off HALT HALT CLG PSC CCLK BCLK PCLK S1C17, RAM, Flash, LCD T16, T8F, UART, SPI, I2C( ), T16E, P, MISC, VD1, SVD, ADC, I2C() FOUT1 RESET NMI FOUT1 On/Off On/Off S1C17 S1C17 OSC1 On/Off (1/128) (1/1~1/32) (1/1~1/16K) T8F, T16, T16E, P, UART, SPI, I2C( ), ADC CLK_256Hz CT, SWT, WDT T8OSC1 On/Off On/Off HSCLK (1/512) OSC1 SVD On/Off HSCLK (1/32~1/512) LCLK LCD OSC1 On/Off HSCLK (1/1~1/8) RFC OSC1 On/Off OSC Appendix C S1C17601 Technical Manual Seiko Epson Corporation 7-1
71 7 OSC 7.2 IOSC IOSC S1C IOSC fiosc IOSC On/Off IOSC IOSCEN D2/OSC_CTL 0 1 IOSC SLEEP * IOSCEN: IOSC Enable Bit in the Oscillation Control (OSC_CTL) Register (D2/0x5061) IOSCEN 1 IOSC On IOSC S1C17 IOSC IOSC IOSCSLEEP IOSC On IOSCIOSC fiosc3/fosc3/fosc IOSC IOSCWT[1:0] D[7:6]/OSC_CTL 4 * IOSCWT[1:0]: IOSC Wait Cycle Select Bits in the Oscillation Control (OSC_CTL) Register (D[7:6]/0x5061) IOSC IOSCWT[1:0] 0x3 8 0x2 16 0x1 32 0x0 64 : 0x0 64 IOSC CPU 28 CPU IOSC max. IOSC 64 VDD IOSCWT[1:0] 0x3 IOSC IOSC max. IOSC 7-2 Seiko Epson Corporation S1C17601 Technical Manual
72 7 OSC 7.3 OSC3 OSC3IOSC OSC3 CG3 Rf3 OSC3 X'tal3 or Ceramic RD3 OSC3EN SLEEP fosc3 OSC3WT[1:0] VSS CD3 OSC OSC3 OSC3 OSC4 X'tal3 Ceramic Rf OSC3 OSC4 VSS2 CG3 CD3 OSC3 On/Off OSC3 OSC3EN D0/OSC_CTL 0 1 OSC3 SLEEP * OSC3EN: OSC3 Enable Bit in the Oscillation Control (OSC_CTL) Register (D0/0x5061) OSC3EN 0 OSC3 IOSC OSC3 On/Off 7.5 OSC3 OSC3SLEEP OSC3 On OSC3OSC3 OSC3 OSC3WT[1:0] D[5:4]/OSC_CTL 4 * OSC3WT[1:0]: OSC3 Wait Cycle Select Bits in the Oscillation Control (OSC_CTL) Register (D[5:4]/0x5061) OSC3 OSC3WT[1:0] 0x x x x : 0x OSC3 OSC3 On OSC3OSC3 OSC3 28 OSC3 OSC3 max. OSC3 : OSC3 OSC3 OSC3 VSS 28 S1C17601 Technical Manual Seiko Epson Corporation 7-3
73 7 OSC OSC3 OSC3 OSC4 : OSC3 OSC4 OSC3EN D0/OSC_CTL Seiko Epson Corporation S1C17601 Technical Manual
74 7 OSC 7.4 OSC1 OSC kHz OSC1 8 OSC1 IOSC OSC OSC1 CG1 X'tal1 OSC1 Rf1 RD1 CD1 OSC1EN SLEEP fosc1 VSS OSC2 VSS OSC1 OSC1 OSC2 X'tal1 Typ kHz OSC1 VSS CG1 0 25pF OSC1 On/Off OSC1 OSC1EN D1/OSC_CTL 0 1 OSC1 SLEEP * OSC1EN: OSC1 Enable Bit in the Oscillation Control (OSC_CTL) Register (D1/0x5061) OSC1EN 0 OSC1 OSC1 SLEEP OSC1 OnOSC1 OSC1 OSC OSC OSC1 max. OSC1 OSC1 OSC1 OSC2 : OSC1 OSC2 OSC1EN D1/OSC_CTL 0 S1C17601 Technical Manual Seiko Epson Corporation 7-5
75 7 OSC 7.5 S1C17601 HSCLK OSC1-HSCLK HSCLKSEL CLKSRC IOSC HSCLK OSC3 OSC HSCLK S1C17601 HSCLK IOSC OSC3 2 IOSC On IOSC HSCLK OSC3 HSCLK OSC3 On7.3 HSCLKSEL D1/OSC_ SRC 1 IOSC HSCLK IOSC On 7.2HSCLKSEL 0 * HSCLKSEL: High-speed Clock Select Bit in the Clock Source Select (OSC_SRC) Register (D1/0x5060) : HSCLK IOSC OSC3On On HSCLKSEL HSCLK HSCLKSEL OSC1 HSCLK S1C17601 OSC1 OSC1 HSCLK HSCLK OSC1OSC1 On7.4 CLKSRC D0/OSC_SRC 1 HSCLK HSCLK SRCSRC 0 OSC1 HSCLK HSCLK OSC1 HSCLK 1 OSC1 1 * CLKSRC: System Clock Source Select Bit in the Clock Source Select (OSC_SRC) Register (D0/0x5060) : OSC1_HSCLK OSC1 HSCLK CLKSRC CLKSRC OSC1-HSCLK Seiko Epson Corporation S1C17601 Technical Manual
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7 7 障害箇所の切り分け 万一 障害が発生した場合は ESMPRO/ServerManagerを使って障害の発生箇所を確認し 障害がハー ドウェアによるものかソフトウェアによるものかを判断します 障害発生個所や内容の確認ができたら 故障した部品の交換やシステム復旧などの処置を行います 障害がハードウェア要因によるものかソフトウェア要因によるものかを判断するには E S M P R O / ServerManagerが便利です
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( ) () ( ) 1 1 TX19A31_AG3 TX19A/H1 CPUTMP19A31CYFG AG3 AG3 2 2 3 TX19A31_AG3 CPU 32 RISC TMP19A31CYFG (U1) 80MHz ROM 32Mbit ROM 1 ROM (U8) 16Mbit Flash ROM 1 (U9) RAM 4Mbit SRAM 1 (U10) I/F RS232C 1chSIO
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13 Verilog HDL 16 CPU CPU IP 16 1023 2 reg[ msb: lsb] [ ]; reg [15:0] MEM [0:1023]; //16 1024 16 1 16 2 FF 1 address 8 64 `resetall `timescale 1ns/10ps module mem8(address, readdata,writedata, write, read);
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COPAL ELECTRONICS 32 (DP) DP INC 2 3 3 RH RL RWB 32 C S U/D INC U/D CS 2 2 DP7114 32 SOIC CMOS 2.5 V - 6.0 V / 10 kω 50 kω 100 kω TSSOP MSOP /BFR INC / U/D RH RoHS GND RWB RL CS VCC 2017 6 15 1 : R = 2
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1 CMOS 0.35um CMOS, 3V CMOS 2 RF CMOS RF CMOS RF CMOS RFCMOS (ADC Fabless 3 RF CMOS 1990 Abidi (UCLA): Fabless RF CMOS CMOS 90% 4 5 f T [GHz] 450 400 350 300 250 200 150 Technology loadmap L[nm] f T [GHz]
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FutureNet Microsoft Corporation Microsoft Windows Windows 95 Windows 98 Windows NT4.0 Windows 2000, Windows XP, Microsoft Internet Exproler (1) (2) (3) COM. (4) (5) ii ... 1 1.1... 1 1.2... 3 1.3... 6...
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