2 3 v v S i i L L S i i E i v L E i v 3. L urren (A) approx. 60% E = V = 0 Ω L = 00 mh urren (A) app
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1 3 ON ON L * 3. v() = i() (3.) 3.2 L 3. L = 0 S i() = i () = i L () v () L v L () = 0 L v () = i(), (3.4) v L () = L d i(). (3.5) d v () + v L () = E, (3.6) i () = i L () = i(). (3.7) L d i() + i() = E. (3.8) d L v() = L d i() (3.2) d v() = i() d (3.3) i() i() = E τ = L ( e /τ) (3.9) L v () = i() ( = E e /τ), (3.0) * 2 2 II II II v L () = L d d i() = Ee /τ. (3.) 3.2 τ ( e ) (= 0.63 = 63%)
2 2 3 v v S i i L L S i i E i v L E i v 3. L urren (A) approx. 60% E = V = 0 Ω L = 00 mh urren (A) approx. 60% down E = V = 0 Ω = 000 µf 0.02 τ = L / = 0 ms 0.02 τ = = 0 ms Time (s) Time (s) v () Volage (V) v () E = V = 0 Ω L = 00 mh Volage (V) approx. 60% of max. E = V = 0 Ω = 000 µf 0.2 v L () 0.2 v () Time (s) Time (s) L 3.4 L τ = L = 0 S i() v () v () = 0 v () = i(), (3.2) v () = i() d. (3.3) v () + v () = E, (3.4) i () = i () = i(). (3.5) i() d + i() = E. (3.6)
3 3.4. L 3 τ = i() = E e /τ (3.7) v () = i() = Ee /τ, (3.8) v () = i() d ( = E e /τ). (3.9) 3.4 τ v () ( e ) (= 0.63 = 63%) τ = 3.4 L L L L L L (open) (shor) ( ) (shor) (open) 3.4
4 High freq. D or Low freq. Large dv/d or Large di/d Small dv/d or Small di/d 3.5 L High freq. D or Low freq. ω L Z L Z L = jωl (3.20) ω Z L = jωl ω Z L (3.2) ω (open) ω Z L = jωl ω 0 Z L 0 (3.22) ω (shor) ω Z 3.6 ω Z = jω ω Z 0 (3.24) ω (shor) ω Z = jω ω 0 Z (3.25) ω (open) * Z = jω (3.23) *2
5 5 V D = 0.7 V D V T V T2 V L L 3.4 D 00 V 2 V (a) wihou a reserver capacior V D = 0.7 V V T V T2 V L 00 V 2 V (b) wih a reserver capacior L * 3 * (a) (b) (a) V T2 (b) V L w/o (c) V L w +7 V 0 V 7 V +6.3 V 0 V ripple 0 V 3.8 *3 choke a choke coil, a choking coil, a choke * L V L 8 00 V ( 2 V ) 3.8(b) 0.7 V 3.8(a) 0.7 V
6 6 3 V D = 0.7 V V D = 0.7 V L D V T V T2 2 V L L D V T V T2 2 V L L L * 5 3.8(b) 3.7(b) 3.8(c) *6 (ripple) V * 7 V = V m f L (3.26) f V m 3.8(b) V m = 6.3 V f = 60 Hz L = 0 kω = 4700 µf V = 5.8 mv *5 0.7 V *6 * V V V = V X X 2 2 (3.27) X 2 = ω 2 (3.28) V = 5.8 mv = 00 Ω 2 = 000 µf V =.5 mv V L V L 3.0 L = 0 H ωl L V = 4 µv
7 7 (a) A (a2) A (a3) pulsaed (a4) quasi-d v() = L d i() (3.29) d A 00 V A (N 2 /N ) x 00 V L V : V 2 = N : N 2 diode bridge di/d (b) A 00 V A (b2) (a) A-D converer wih a smoohing capacior A A (N 2 /N ) x 00 V (b3) pulsaed (b4) D choking coil V : V 2 = N : N 2 diode bridge 3. 4 *8 L 3.2 v in v ou *9 *8 4 *9 () (b) A-D converer wih smoohing capaciors and a choking coil 3. (a) (b) L B B 3.2 B V = +0 V V v in v in B v in 0 V v in B B 0 V h FE
8 8 3 V +0 V v in 00 uv 0 0 kω kω +.8V 3.6 kω E kω +6.04V +.V 0 V L 00 kω 3.2 B E 3 2 v ou B v in v in B v in B B v in B (+.8 V) v in 2 L 0 V L 2 L L 0 V E E E * 0 E E E B E B E * 3 E E E E E *0 E * E
9 9 High freq. noise Low freq. signal (differenial-mode noise) Low freq. signal High freq. noise (a) Normal-mode noise High freq. noise Low freq. signal L (common-mode noise) 3.5(a) Low freq. signal High freq. noise (b) educion of normal-mode noise L 3.3 (a) (b) 3.4 (Schaffner FN9222) [] L (normal-mode noise) 3.3(a) ( ) 3.3(b) L 3.3(b) L 3.5(b) 3.6
10 0 3 High freq. noise High freq. noise Low freq. signal Low freq. signal floaing Low freq. signal High freq. noise (a) ommon-mode noise Low freq. signal floaing High freq. noise ommon-mode choke floaing floaing (b) educion of common-mode noise 3.5 (a) (b) A B For common mode curren (noise) A Flux is added. B Work as an inducor for boh A and B, i.e. For differenial mode curren (signal) A Flux is canceled. B Does no work as an inducor L L Work for noise reducion. for boh A and B, i.e. Work as simple lines PU (cenral processing uni) (ulra large scale inegraed circuis; ULSI) PU PU GPU (graphics processing uni) "0" "" PU PU "0" "" 3.9 (meal oxide semiconducor field effec ransisor (MOS FET)) ON OFF MOS FET ( ) (Schaffner B series) [] 3.8 Inel ore i7 [2]
11 Gae widh, Z Polysilicon or meal Oxide n-ype semiconducor 60 nm gae n-source Gae n-drain Meal source conac S L p-subsrae (a) Gae, G n-ype polysilicon Deposied insulaor Meal source conac D.5 nm gae oxide nm MOS FET [3] SiO 2 n + d ox n + SiO 2 Source Drain Field oxide hannel region L p Silicon dioxide hannel lengh p-ype body, B (b) D G B S (c) 3.9 MOS FET (a) (b) (c) } MOS FET ( ) 3.20 MOS FET ( ) 60 nm MOS FET 3.2 [3] Feaure size (nm) (97) 8080 (974) 8086 (978) (982) (985) Penium (993) PowerP 603 (994) UlraSparc II (997) Penium 4 (2000) Xeon 5400 (2007) ore i7 (2009) ore M (204) Year lock frequency (MHz) PU 3.22 [4] * PU [2] *2
12 2 3 (a) v() level 0 level inpu T ime 23. µm (b) v() level 0 level oupu ( << T ) ime 3.22 IBM [4] (c) v() level 0 level oupu ( ~ T ) ime 3.25 "0"/"" dielecric meal (a) (b) 3.23 inpu inpu E 0 meal dielecric v v 2 level E delay oupu oupu v v 2 0 level 0 level 0 level "0" "" ON/OFF 3.24 = 0 0 E = 0 "0" "" 0 E E ( v 2 () = E e /τ). (3.30) τ = T τ = T 3.25(b) "0" "" T 3.25(c) PU PU
13 3 passivaion global u wire via low-k dielecric ech sop layer dielecric diffusion barrier u inermediae barrier/seed layer (Ta/TaN) local MOS W plug isolaion (STI, USG) p-si wafer buried oxide ρ S L = ρ L (3.3) S L ULSI S ULSI 3.26 [3] ρ * 3 * ρ = 2.8 µω cm Al Al Au (2.4 µω cm) u (.7 µω cm) Ag (.6 µω cm) u [5] [6] = ε rε 0 S d (3.32) ε r ε 0 d S ( )
14 4 3 S d ε r 4 SiO 2 (low-k ) 3.26 d * 4 * 5 "" ( ) τ = *4 d *5 τ = Delay ime (ps) u/low-k + Gae NMOS gae delay Al/SiO 2 + Gae u/low-k delay Al/SiO 2 delay Feaure size (µm) 3.27 [7] 2 3 SiO 2 SiO Al (ρ = 2 µω cm) SiO 2 (ε r = 4) u (ρ = 3 µω cm) Low-k (ε r = 2) [7] Al SiO µm u ε r = 2 Low-k 0.2 µm 0.2 µm PU PU PU PU PU
15 5 3.28(a) 3.28(b) v() V m Δ ~ T 2 ΔV T (a) (a) V = V m f (3.33) v() V m Δ ~ T/2 2 ΔV (b) V = V m 2f (3.34) T/2 T (b) f 3.29(a) [8] ( ) 2 2 ( ) V v() L (a) v() L V (b) 3.28 (a) (b) 3.29 (a) (b) = v = V m = 2 = ( v() = V m exp ). (3.35) 2 v() = V m ( + 2 ( ) 2 ) ( = V m ). (3.36) V = = 2 T V = V m (3.37) f = /T V = V m f. (3.38)
16 (b) T T/2 V = V m 2f. (3.39) 0: Z Z = 2 + X 2 (3.42) 0: 3.30(a) 0: [9] X = = 0. (3.43) 0 Z = 2 + (0.) 2 =.005 (3.44) X < 0 (3.40) Z = = = 99.5%. (3.45).005 X = ω (3.4) ω Z 0: 3.30(b) f = 20 Hz ω = 26 rad/s = 2 kω (a) v A > 40 µf (3.46) v D shor (b) v A 3.3(a) open (c) v D 0: * (a) (b) (c) X < 0 X = ω *6 (3.47) (3.48)
17 7 (a) v A v D r E /X Y = 0/ = = 99.5%. (3.52) 0.05/ (b) v A (c) v D r r E E open shor Y 0: 3.30(b) f = 20 Hz ω = 26 rad/s = kω 3.3 (a) (b) (c) ω r 3.3 E r 0: Y Y = 2 + X 2 (3.49) > 80 µf (3.53) r r * 7 v A v A * 8 v A 0: X = 0 (3.50) Y = = (3.5) *7 *8
18 8 3 q() [] i() L d i() + i() = E. (3.54) d = 0 i() = 0 L E ( 0) i E di = d. (3.55) L i E di = L d. (3.56) ln(i E) = + ln K. (3.57) L K i E = Ke L (3.58) = 0 i() = 0 E = K (3.59) i() i() = E ( e L ). (3.60) d d q() + q() = E. (3.62) dq = d. (3.63) q E dq = q E d. (3.64) ( ) ln q E = + ln K. (3.65) K q E = Ke (3.66) = 0 q() = 0 E = K (3.67) q() ) q() = E ( e. (3.68) i() = d d q() i() i() = E e. (3.69) [2] i() = d d q() i() i() + i() d = E. (3.6) = 0 q() = 0 E ( 0)
19 9 [] hp:// [2] hp:// PU [3] S. Thompson e al.: 30 nm logic echnology feauring 60 nm ransisors, low-k dielecrics, and u inerconnecs, Inel Technol. J. 6 (May 2002) pp [4] hp://www-03.ibm.com/ibm/hisory/ibm00/us/en/icons/copperchip/ hp://kasap3.usask.ca/ [5] D. Edelsein e al.: Full copper wiring in a sub-0.25 µm MOS ULSI echnology, IEDM Tech. Diges (997) pp [6] K. Ohashi e al.: On-chip opical inerconnec, Proc. IEEE 97, (2009). [7] : ULSI, 68, (999). [8] J. Millman and.. Halkias: Inegraed Elecronics: Analog and Digial ircuis and Sysems (McGraw- Hill Kogakusha, Tokyo, 972) pp [9] Alber Malvino and David Baes: Elecronic Principles 8h Ed. (McGraw-Hill Eduaion, New York, NY, 206) pp
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