MOSFET 6-2 CMOS 6-2 TTL Transistor Transistor Logic ECL Emitter Coupled Logic I2L Integrated

1 -- 7 6 2011 11 1 6-1 MOSFET 6-2 CMOS 6-2 TTL Transistor Transistor Logic ECL Emitter Coupled Logic I2L Integrated Injection Logic 6-3 CMOS CMOS NAND NOR CMOS 6-4 6-5 6-1 6-2 CMOS 6-3 6-4 6-5 c 2011 1/(33)

1 -- 7 -- 6 6--1 2008 10 6--1--1 6 1 6 1 V i V o I B I C V CC V BE V CE V CC = I C R C + V CE V i = I B R B + V BE I C I C = V CC V CE R C I C V CE 6 2 A - B I B A - C - B V i I B 1 A I B = 0 I C = 0 V CE = V CC 2 B c 2011 2/(33)

I C [ma] I B V CE [V] 6 2 I C = I CS AT = V CC V CES AT R C V CE = V CES AT V CES AT 0.1 0.2 V 0.6 0.7 V V CES AT V BE 3 A B A B A B I C = βi B β V CE = V CC R C I C (1) (2) 6--1--2 6 3(a) t = 0 I B 6 3(b) I C c 2011 3/(33)

6 3(c) I C I CS AT 10 90 rise time t r 10 delay time t d I CS AT V CES AT = 0.2 0.3 V I CS AT 0 (a) t 0 (b) t 90% 0 10% 6 3 I CSSAT t r t d t s t f t (c) 0 0 I C storage t time s I C I CS AT 90 10 fall time t f 6 4 c 2011 4/(33)

0 t 6 4 6--1--3 MOS 6 5 MOS I D : V DD V DS C V i V GS 6 5 MOS MOS NMOS PMOS CMOS MOS V DD V GS = 0 I D = 0 V GS = V DD MOS 6 6 A B I DS = 1 2 µc ox ( ) W (V DD V T H ) 2 L c 2011 5/(33)

µ C ox W L B I D = 0 C MOS R = V DD I DS = 1 2 µc ox( W L V DD ) (VDD V T H ) 2 I D [ma] V GS V DS [V] 6 6 MOS 6 7 C in = 3/2C ox C out = C ox Gate SW C in 3 C OX R 2 C OX C out Drain Source 6 7 MOS c 2011 6/(33)

6--1--4 MOS MOS τ = RC ox = 2L V DD µc ox W(V DD V T H ) C 2L 2 V DD oxwl = 2 µ(v DD V T H ) 2 L 2 W V DD c 2011 7/(33)

1 -- 7 -- 6 6--2 2008 10 DTL Diode Transistor Logic TTL Transistor Transistor Logic ECL Emitter Coupled Logic I2L Integrated Injection Logic TTL ECL I2L 6--2--1 TTL 1 NAND NAND 6 8 V A V B V O V A V B L 0.8 V R 1 Q 1 Q 1 V C1 Q 2 R 4 0 V BE4 = 0 Q 4 Q 3 V B3 V CC Q 3 V O = V CC V BE3 V D3 H V CC R 3 R 1 R 2 V B3 Q 3 V CE3 V A V B V BE1 V BC1 Q 1 V C1 V CE1 V BE2 R 4 Q 2 V CE2 V BE3 D 3 V E3 V D Q 4 V CE4 V O IN OUT VA VB V O L L H L H H D 1 D 2 V BE4 H L H H H L L 0.8 V L 0.4 V H 2.0 V H 2.4 V 6 8 2 NAND TTL V A V B Q 1 Q 2 Q 2 V A, V B > V BE1 + V BC1 + V BE2 + V BE4 2V BE c 2011 8/(33)

V BE1 = V BE2 = V BE4 = V BC1 = V BE R 4 Q 4 Q 3 V B3 V E3 V B3 = V BE4 +V CE2 V E3 = V CE4 + V D3 V BE4 = V D3 V CE2 = V CE4 Q 3 V BE3 V BE3 = V B3 V E3 = V BE4 + V CE2 V CE4 V D3 0 L D 3 Q 3 Q 3 Q 4 Q 2 Q 1 Q 4 R 4 Q 4 Q 3 Q 4 Q 3 Q 4 R 4 Q 3 D 3 Q 4 D 1 D 2 2 NOT NOT NAND 6 8 Q 1 NAND 3 NOR 6 9 NOR NOR Q 1 Q 3 Q 2 Q 4 2 Q 3 Q 4 NOR V CC R 1 R 2 R 3 R 5 V A Q 1 Q 3 Q 5 IN OUT VA VB VO V B Q 2 Q 4 D 3 V O L L H Q 6 L H L D 1 D 2 R 4 H L L H H L 6 9 2 NOR TTL V A V B L Q 1 Q 2 Q 3 Q 4 Q 5 V CC Q 6 0 Q 5 Q 6 V O H V A V B H Q 3 Q 4 R 4 Q 6 V O L 6--2--2 ECL TTL c 2011 9/(33)

ECL Emitter Coupled Logic CML Current Mode Logic 6 10 ECL OR/NOR V CC R 1 R 2 V O2 V O1 V A Q 1 V B Q 2 Q 3 V R R E I RE V EE 6 10 2 OR/NOR ECL V B < V R 6 10 6 11 Q 1 Q 2 V A < V R Q 1 Q 3 V O1 H V O2 L R E I RE I RE = V E V EE R E = V R V EE3 V EE R E R 2 Q 3 V O2 = V CC I RE R 2 Q 3 V BC3 = V R V O2 V A > V R Q 1 Q 3 R E I RE I RE = V E V EE R E = V A V BE1 V EE R E Q 1 V A Q 1 V O1 = V CC I RE R 1 Q 1 V O1 (V A V BE1 ) > V CES AT V CES AT Q 1 c 2011 10/(33)

V CC R 1 R 2 V O1 V O2 V A Q 1 Q 3 V R V BE1 V E V BE2 R E V EE 6 11 6 10 V A V B V R Q 1 Q 2 Q 3 V O1 H V O2 L V A V B V R Q 1 Q 2 Q 3 V O1 L V O2 H V O1 V A V B NOR V O1 = V A + V B V O2 V A V B OR V O2 = A + B 6 12 ECL Q 4 Q 5 V 1 V 2 V BE Q 3 R 5 R 6 D 1 D 2 Q 6 R 7 R E 6--2--3 I2L IIL I2L Integrated Injection Logic TTL ECL c 2011 11/(33)

V CC R 1 R 2 R 5 Q 4 V 1 V 2 Q 5 Q 6 V O1 V A Q 1 V B Q 2 Q 3 D1 V O2 D 2 R 3 R 7 R 6 R 4 R E V EE 6 12 2 OR/NOR ECL pn I2L 6 13 6 14 npn Q 1 Q 2 pnp Q 3 n Q 3 pnp pnp Q 3 Q 1 Q 2 npn n Q 1 Q 2 I2L Q 1 Q 2 Q 3 I2L L V CS 0.1 V H V BE 0.7 V A B L A B L Q 1 Q 2 H H Q 3 Q 1 Q 2 L Q 1 Q 2 NOR Q 1 Q 2 Q 3 Q 1 Q 2 Integrated Injection Logic c 2011 12/(33)

V CC V CC R R Q 5 Q 3 Q 1 Q 4 Q 2 6 13 I2L Q 1 Q 3 Q 2 6 14 I2L c 2011 13/(33)

1 -- 7 -- 6 6--3 CMOS 6--3--1 CMOS 2008 10 MOS CMOS Complementary MOS 1 CMOS CMOS 6 15 V DD Q p V I V O Q n 6 15 CMOS CMOS nmos pmos H L 0 V I V O V GS V I H V I = V DD Q n Q p V O L Q p Q n Q p V I L V I = 0 Q n Q p V O H Q n Q p 2 CMOS NAND 6 16 NAND A B H Q n1 Q n2 V O L Q p1 Q p2 A B L Q n1 Q n2 Q p1 Q p2 V O H c 2011 14/(33)

V DD Q p1 Q p2 V O Q n2 Q n1 6 16 NAND 3 CMOS NOR 6 17 NOR A B H Q n1 Q n2 V 0 L Q p1 Q p2 A B L Q n1 Q n2 Q p1 Q p2 V O H V DD Q p1 Q p2 V O Q n1 Q n2 6 17 NOR c 2011 15/(33)

6--3--2 CMOS MOS 6 18 CMOS SW MOS L SW H SW C G H H 6 19 V I SW V O C G 6 18 V DD Q p Q psw V I V O Q nsw C G Q n 6 19 nmos pmos Transfer Gate Analog Switch 6 20 c 2011 16/(33)

6 21 CMOS Q n1 Q p1 C G V I V O C G 6 20 V DD Q p1 Q p2 V I V O Q n2 C G Q n1 6 21 c 2011 17/(33)

6 22 6 1 V I V O C G 6 22 D 6 1 φ Q 0 0 1 0 1 0 1 1 1 0 Q n 1 6--3--3 6 23 D SW1 D 2 Q D SW1 C G SW2 Q 2 SW2 2 6 2 D 6 2 φ Q 0 1 0 1 1 1 0 6 24 c 2011 18/(33)

SW1 SW2 6 23 6 24 6--3--4 D D 6 25 D 2 φ L SW1 D 1 X D φ H SW1 SW2 1 SW3 2 D Q φ L H φ L SW4 2 D φ L H D Q n 1 1 D 6 3 D 6 26 c 2011 19/(33)

SW1 SW3 SW2 SW4 6 25 D D 6 3 φ Q 0 0 1 0 1 0 1 1 1 0 Q n 1 6 26 D c 2011 20/(33)

1 -- 7 -- 6 6--4 2009 12 2 2 6--4--1 6 27 1 V d = V p V n 0 A A 1 V out ±V DD V d V MAX 1 mv 2 V out = V DD α = R 1 /(R 1 + R 2 ) V p = αv DD V n < V p V MAX V n R 0 C 0 V out = V DD V p V n = V MAX 0 V n = αv DD V DD V out = V DD V p = αv DD, V n > V p + V MAX V n V out = V DD V n R 1 /(R 1 + R 2 )V DD T osc T osc = 2R 0 C 0 ln(1 + 2R 1 /R 2 ) 1/T osc R 1, R 2 R 0 C 0 α V n ±V DD 2 ±αv DD 6 28 6 27 V n R 0, C 0 R 1 T osc T osc = 4R 0 R 1 C 0 /R 2 1/T osc c 2011 21/(33)

6 27 c 2011 22/(33)

6 28 c 2011 23/(33)

6--4--2 NOT NOT 6 29 6 31 6 27 NOT 1 NOT 1 V n V T H V DD V DD NOT 1 V n V T H 6 27 V p V T H 6 29 NOT i i = 2 3 R i 1, C i 1 V n = V T H R 0 V z V n V T H V z V n V T H V V n = V T H + V V z V DD V n = V T H V V z +V DD R 0 C 0 V n V p V T H ± V 2 6 27 NOT 6 29 R i NOT C i T osc τ ui, τ di i = 1 2 3 T osc = Σ i τ ui + τ di NOT NOT 6 30 NOT 2 C 0 V out V n V n V n = V T H V out = V DD NOT 2 V DD +V DD V n V T H V T H + 2V DD V n V out = V DD V n V n = V T H V out = +V DD NOT 2 +V DD V DD V n V T H V T H 2V DD V out = +V DD T osc = 2R 0 C 0 ln[(3v DD V T H )/(V D D V T H )] 6 31 6 30 NOT V T H ±2V DD 6--4--3 1 NOT EG SG NOT EG SG NOT NOT c 2011 24/(33)

6 29 c 2011 25/(33)

6 30 CMOS NOT c 2011 26/(33)

6 31 TTL NAND 6 32 6 31 6 31 V B 1 6 32 6 33 6 32 V B V DD R 0A, R 0B 2 c 2011 27/(33)

6 33 6 34 MOSFET 6 34 1),,,,,, 2006. 2),,, 1989. 3),,,, 1980. c 2011 28/(33)

1 -- 7 -- 6 6--5 2008 9 khz MHz 1 2 3 6--5--1 6 35 DC/DC 6 35 DC/DC 6--5--2 6 35 DC/DC 6 4 c 2011 29/(33)

2 Buck Boost Buck-boost Zeta 6 4 6--5--3 D 1 D2 L V in S C O R O V out 6 36 DC/DC 6 36 6 37 6 38 6 39 c 2011 30/(33)

6 40 6 5 R 1 D L C O R O V out V in T r1 R 2 6 37 D V in C O R O V out S 6 38 V in L S D C O R O V out 6 39 c 2011 31/(33)

S1 S4 V in S2 C 1 C O R O V out S3 6 40 6 5 ( ) 1) 6--5--4 6 41 PWM: Pulse Width Modulation 6 41 c 2011 32/(33)

EMC: Electromagnetic Compatibility 1) 1),, pp.1-549,, 12-01. c 2011 33/(33)