FPGA 概概 Tutorial TU0116 (v2.0) May 17, 2008 Innovation Station FPGA Altium Designer FPGA NanoBoard FPGA - FPGA Innovation Station Altium Designer NanoBoard FPGA Innovation Station. NanoBoard FPGA NanoBoard LED FPGA FPGA Altium Designer FPGA FPGA - FPGA HDL 1 Altium Designer Altium Designer \Examples\Tutorials\Getting Started with FPGA Design 1 - TU0116 (v2.0) May 17, 2008 1
NanoBoard NanoBoard LED NanoBoard NanoBoard DIP NanoBoard DIP NanoBoard 'DAUGHTER BD TEST/RESET' LED Desktop NanoBoard, TR0143 Technical Reference Manual for Altium's Desktop NanoBoard NB2DSK01 NanoBoard www.altium.com/nanoboard/resources FPGA NanoBoard FPGA FPGA Altium Designer NanoBoard FPGA Actel Designer Libero IDE www.actel.com Altera Quartus II www.altera.com Quartus II Lattice isplever www.latticesemi.com isplever Xilinx ISE www.xilinx.com Xilinx ISE WebPACK (www.altium.com/community/vendorresources) Altium Designer Tools Devices View» Devices View Vendor Tool Support : FPGA FPGA 2 TU0116 (v2.0) May 17, 2008
Altium Designer FPGA Altium Designer FPGA FPGA *.PrjFpg ASCII FPGA 1. FPGA File» New» Project» FPGA Project 2. Projects FPGA_Project1.PrjFpg Save Project Simple_Counter.PrjFpg Basic FPGA Design Tutorial : - _ FPGA HDL VHDL Verilog OpenBus - FPGA - Altium Designer FPGA PCB FPGA 1. Projects FPGA Add New to Project» Schematic 2. File» Save Simple_Counter.SchDoc 3. Projects Save Project 2 FPGA TU0116 (v2.0) May 17, 2008 3
NanoBoard NB2DSK01 1 FPGA Generic FPGA Generic.IntLib Altium Designer \Library\Fpga 表 1. ツツツツツツツツツツツの回回回に必概なデデツツデツデデデツツ FJKC J-K 2 INV 6 J8B_8S Bus Joiner 8 8 1 OR2N2S 2 OR Low A Low B 1 SR8CLED 8 / - 1 2 NanoBoard FPGA I/O FPGA NB2DSK01 Port-Plugin FPGA NB2DSK01 Port- Plugin.IntLib Altium Designer \Library\Fpga 表 2. ツツツツツツツツツツツの回回回に必概なデデツデツデデデツツ CLOCK_REFERENCE NanoBoard 20MHz 4 TU0116 (v2.0) May 17, 2008
DIPSWITCH LED TEST_BUTTON Desktop NanoBoard DIP 3 Desktop NanoBoard LED LED Desktop NanoBoard 'DAUGHTER BD TEST/RESET' D GND '0' 3 FPGA Generic FPGA NB2DSK01 Port-Plugin Libraries OK Place & Tools» Annotate Schematics Quietly 3 Simple_Counter.SchDoc 1. 4 Place» Wire Place» Bus Wiring TU0116 (v2.0) May 17, 2008 5
4-2. Wiring GND TAB Power Port Style Bar 2 CLR 3. GND Bar CLR 4. Wiring GND Style Bar D[7..0] Spacebar 5 CLR GND 6 GND 5. SLI SRI Wiring 2 7 7 6. No ERC U4 Wiring No ERC O3 O7 8 8 ERC 6 TU0116 (v2.0) May 17, 2008
7. 9 Place» Net Label Wiring 9 9-8. File» Save All FPGA TU0116 (v2.0) May 17, 2008 7
FPGA Altium Designer Options for FPGA Project Project» Project Options Error Reporting Connection Matrix : 1. Project» Compile FPGA Project Simple_Counter.PrjFpg 2. Messages 10 Options for FPGA Project Error Reporting Connection Matrix System Messages Compile Errors 3. Simple_Counter.SchDoc 11 SQ0 SQ7 SQ1 SQ6 SQ[7..0] 11 TR0142 Project Compiler Error Reference 4. 8 TU0116 (v2.0) May 17, 2008
FPGA FPGA ( ) Desktop NanoBoard NB2DSK01 3 FPGA NanoBoard NB2DSK01 NB2DSK01 NB2DSK01 NanoBoard FPGA FPGA FPGA Altium Designer NB2DSK01 3 1 : 2 NanoBoard NB2DSK01 AR0124 Design Portability, Configurations and Constraints NanoBoard NB2DSK01 AP0154 Understanding the Desktop NanoBoard NB2DSK01 Constraint System FPGA 1. - FPGA 3 NB2DSK01 - - NanoBoard USB ( ) PC 2. Devices View» Devices View Live Connected 3. 2 1 NanoBoard NanoBoard Configure Fpga Project» 12 Devices Simple_Counter.PrjFpg 12 2 NanoBoard NanoBoard Controllers Instrument Rack Board View NanoBoard Configuration Auto Configure FPGA Project Simple_Counter.PrjFpg TU0116 (v2.0) May 17, 2008 9
13 NanoBoard NB2DSK01 NB2DSK01 13 NanoBoard Configuration Simple_Counter NanoBoard motherboard code_revision_daughter board code_revision NanoBoard NB2DSK01 8 Spartan-3 DB30 6 NB2DSK01_08_DB30_06 Altium Designer \Library\Fpga\NB2 Constraint Files Spartan-3 DB30 6 DB30.06.Constraint '_BoardMapping' NB2DSK01_08_DB30_06_BoardMapping.Constraint Simple_Counter.PrjFpg 10 TU0116 (v2.0) May 17, 2008
4. Configuration Manager 14 14 Simple_Counter OK Settings Projects Constraint Files 5. FPGA 15 FPGA FPGA FPGA Devices 1. Altium Designer Devices View» Devices View 2. Live Connected FPGA 'Process Flow' 15 16 FPGA Process Flow Process Flow FPGA Project / Configuration TU0116 (v2.0) May 17, 2008 11
Project / Configuration Simple_Counter / ConfigurationName Simple_Counter / NB2DSK01_08_DB30_06 15 Process Flow 4 Process Flow Progran FPGA 3. Compile Design Compiler Messages 4. Symthesize VHDL EDIF FPGA Generated [ConfigurationName] EDIF Simple_Counter.edf VHDL Simple_Counter.vhd Simple_Counter_Synth.log 17 Messages 5. Build Altium Designer 18 Build 5 - Process Flow EDIF NGD Native Generic Database - FPGA FPGA - FPGA - - BIT Messages Output System Results Summary 12 TU0116 (v2.0) May 17, 2008
19 6. Program FPGA FPGA PC NanoBoard JTAG Altium Designer Devices Reset Programmed 'Program' LED 20 Devices AP0103 Processing the Captured FPGA Design 7. NanoBoard DIP - Switch 8: ON LED - Switch 7: ON LED - Switch 6: On 7 8 OFF 8. NanoBoard 'DAUGHTER BD TEST/RESET' LED 9. NanoBoard LED NanoBoard 20MH Mhz LED FPGA TU0116 (v2.0) May 17, 2008 13
FPGA *PrjFpg Filename OpenBus VHDL Verilog VHDL 21 21 NanoBoard Simple_Counter VHDL FPGA 1. Simple_Counter.SchDoc 2. Place» Sheet Symbol 3. Sheet Symbol - Designator : U_Clock_Divider - : Clock_Divider.SchDoc. 22 4. Place» Add Sheet Entry - Name: CLK_REF, I/O Type: Input - Name: CLK_OUT, I/O Type: Output 5. CLK_REF 23 14 TU0116 (v2.0) May 17, 2008
23 Simple_Counter Clock_Divider.SchDoc : 6-9 Project Simple_Counter.PrjFpg Add Existing to Project. Choose Documents to Add to Project Clock_Divider.SchDoc Altium Designer \Examples\Tutorials\Getting Started with FPGA Design 10 6. Sheet Symbol Actions» Create Sheet From Symbol Clock_Divider.SchDoc 2 CLK_REF CLK_OUT 7. Libraries 6 CDIV10DC50-50% 10 1 FPGA FPGA Generic.IntLib 2 24 24 Clock_Divider.SchDoc 8. Tools» Annotate Schematics Quietly 9. File» Save All Clock_Divider.SchDoc 10. 11. Projects Clock_Divider.SchDoc Simple_Counter 25 12. Devices Live Connection 13. FPGA Process Flow Ignore FPGA source Process Flow Ignore FPGA source Process Flow TU0116 (v2.0) May 17, 2008 15
26 Ignore FPGA source Process Flow 14. FPGA Process Flow Program FPGA VHDL VHDL DIP 7 8 NanoBoard LED DIP HDL 27 VHDL HDL VHDL Verilog VHDL VHDL VHDL VHDLEntity VHDL Entity Verilog Verilog Verilog VerilogModule Verilog Module Mhz VHDL VHDL : 1-3 VHDL Project Simple_Counter.PrjFpg Add Existing to Project. Choose Documents to Add to Project Clock_Divider.SchDoc Altium Designer \Examples\Tutorials\Getting Started with FPGA Design 4 1. Projects Simple_Counter.PrjFpg Add New to Project» VHDL Document VHDL VHDL1.vhd Clock_Divider.vhd 2. VHDL library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity Clock_Divider is port ( CLK_REF : in std_logic; CLK_OUT : out std_logic ); 16 TU0116 (v2.0) May 17, 2008
end entity; architecture RTL of Clock_Divider is begin process(clk_ref) variable i : integer range 0 to 999999; begin if rising_edge(clk_ref) then if i = 0 then CLK_OUT <= '1'; i := 999999; else CLK_OUT <= '0'; i := i - 1; end if; end if; end process; end architecture; 3. VHDL 4. Clock_Divider.SchDoc FPGA Projects Remove from Project 5. Simple_Counter Simple_Counter.SchDoc Delete 6. Design» Create Sheet Symbol From Sheet Or HDL Choose Document to Place Clock_Divider.vhd OK 7. 28 Designator Filename U_clock_divider Clock_Divider.vhd VHDLENTITY value = clock_divider VHDL 28 Simple_Counter Clock_Divider.vhd TU0116 (v2.0) May 17, 2008 17
8. 9. 10. Projects VHDL Clock_Divider.vhd Simple_Counter 29 VHDL VHDL 11. Devices FPGA Process Flow Program FPGA 12. DIP 7 8 NanoBoard LED DIP 18 TU0116 (v2.0) May 17, 2008
- FPGA Hard Devices FPGA JTAG Viewer Live Update JTAG Viewer JTAG FPGA JTAG 1. Devices FPGA Hard Devices FPGA Instrument Rack Hard Devices 30 30 FPGA Instrument 2. JTAG Viewer Panel JTAG Device Viewer Live Update Hide Unassigned I/O Pin 31 3. FPGA LED LED 4. NanoBoard DIP TU0116 (v2.0) May 17, 2008 19
FPGA Devices \Library\Fpga\FPGA Instruments.IntLib FRQCNT2 - I/O DIGITAL_IO - NanoBoard DIP 3 CR0101 FRQCNT2 Frequency Counter CR0179 DIGITAL_IO Configurable Digital IO Module VHDL 1. Simple_Counter Simple_Counter.SchDoc 2. Libraries FRQCNT2 FPGA Instruments FPGA Instruments.IntLib 3. Tools» Annotate Schematics Quietly CLK_OUT TIMEBASE NanoBoard CLK_REF 4. 32 32 / / 1. Libraries DIGITAL_IO 2. Tools» Annotate Schematics Quietly 3. Configure U13 (DIGITAL_IO) Digital I/O Configuration 33 8-bit AIN[7..0] 8-bit AOUT[7..0] 20 TU0116 (v2.0) May 17, 2008
33 / 4. AOUT[7..0] Remove 5. Count_Output[7..0] Style LEDs Color Green NanoBoard LED 6. DIP 3 3 - Signal 1 Name: Shift_Left, Style: LEDs, Color: Green. - Signal 2 Name: Shift_Right, Style: LEDs, Color: Green. - Signal 3 Name: STOP, Style: LEDs, Color: Red. Input Signal 34 34 I/O 7. 35 S04 SO3 SO2 & DIP Off ON TU0116 (v2.0) May 17, 2008 21
35 I/O JTAG Altium Designer FPGA JTAG NanoBoard JTAG Nexus JTAG NEXUS_TMS NEXUS_TCK NEXUS_TDI NEXUS_TDO NanoBoard NanoTalk Spartan-3 FPGA 4 NEXUS_JTAG_CONNECTOR 36 FPGA NB2DSK01 Port-Plugin \Library\Fpga\FPGA NB2DSK01 Port-Plugin.IntLib JTAG Nexus 2 NEXUS_JTAG_PORT 37 NEXUS_JTAG_CONNECTOR FPGA Generic \Library\Fpga\FPGA Generic.IntLib NEXUS_JTAG_PORT NEXUS_JTAG_DEVICE=True JTAG JTAG AR0130 PC to NanoBoard Communications 1. NEXUS_JATAG_CONNECTOR NEXUS_JTAG_PORT Simple_Counter 2. VCC NEXUS_JTAG_PORT TRST 36 Nexus JTAG 37 Nexus JTAG 2 39 38 JTAG JTAG 22 TU0116 (v2.0) May 17, 2008
39 2 3. 4. Messages SQ Digital I/O JTAG FPGA Altium Designer IEEE 1149.1 JTAG FPGA Nexus 5001 I/O Nexus - Soft Device - FPGA Devices Nexus FPGA 1. Devices FPGA 2. Soft Devices 2 40 40 Soft Devices TU0116 (v2.0) May 17, 2008 23
3. NanoBoard DIP 7 8 4. 2 Instrument Rack Soft Devices panel 41 41 I/O 50Hz NanoBoard 20MHz MH 20Hz LED I/O LED NanoBoard 2 5. Counter Options Counter Module Options Counter Time Base 50.000MHz 20.000MHz TIMEBASE 20Hz 6. I/O Options Digital I/O Module Options Update Display From Core Every 250ms 100ms LED 42 TIMEBASE 43 7. I/O 24 TU0116 (v2.0) May 17, 2008
FPGA Innovation Station FPGA Altium Designer NanoBoard 32 FPGA Innovation Station GU0123 An Introduction to Embedded Intelligence TU0122 TU0123 Creating a Core Component TU0126 Checking Signal Integrity on an FPGA Design TU0128 Implementing a 32-bit Processor-based Design in an FPGA TU0129 Converting an Existing FPGA Design to the OpenBus System TU0130 Getting Started with the C-to-Hardware Compiler TU0131 Capturing Video the Easy Way TU0133 Designing Custom FPGA Logic using C TU0135 FPGA 日日バデババツ番番変変変変 16-Jan-2004 1.0 23-Sep-2004 1.1 Clock divider components updated 18-Jan-2005 1.2 Components in Johnson_Counter.SchDoc updated 13-Apr-2005 1.3 Updated for Altium Designer 22-Aug-2005 1.4 Verilog references included 28-Nov-2005 1.5 Updated for Altium Designer 6 12-Apr-2007 1.6 Updated for Altium Designer 6.7 17-May-2008 2.0 Updated for Altium Designer Summer 08. Project and schematic documents renamed to Simple_Counter.PrjFpg and Simple_Counter.SchDoc respectively. Tutorial content enhanced throughout. Section on virtual instrumentation added. ソソツツソソ ハデハツソソ 文文 おおお関関関関 Copyright 2008 Altium Limited. All Rights Reserved. 以以の注注文ききききに提提さささ文文きとの情情は 様々な形におさ国変 海海の知知知知知の保保 - 著著知の保保を含むむとさに限限ささなさ - む目知でで この注注文きの閲閲閲には 非非非知なラツラツツむ日付さささおさ このおこな文文きとの情情を との使使ににささ規限しさささ使使使使使使文 ( エツハエデデラツラツツソツツデエツツ ) に記記の目知のののに使使でさこきむできすで さいなさ場場におささき あなのにラツラツツささの文文いら あささはとの他の手手を利使しさ ツバデツエツバリソ 逆デツコツコ 複複 配配 派派派の著作を行ここきは 明明に規限ささの同注文におさ使使を得なさ限さできすりり いいさ制限制制む遵遵ささなさ場場 罰罰や実実を含む民民罰き実民罰の対対きなさこきむあさすで しいしなむら バババソババの目知に限さ 提提さささ文文のすのは情情を一一だだ記記に残し オツバオコデオデむ不不の場場のの との複複にソバラツし 利使でさこきは使許ささすで Altium Altium Designer Board Insight CA Mtastic CircuitStudio Design Explorer DXP Innovation Station LiveDesign NanoBoard NanoTalk OpenBus Nexar nvisage P CAD Protel SimCode Situs TASKING Topological Autorouting おおおとさおさに対対でさロロは Altium Limited すのはとの子子子の商商すのは登記商商でで 本文に記記さささささとさ以海の登記商商や商商はとさおさの所所閲の知知であさ 商商知を主主でさきのではあさすりり TU0116 (v2.0) May 17, 2008 25