UML 1 1 2 UML HDL The Verfication and Evalution to the Hard-ware Design Method using the UML Diagrams Daiki Kanou, 1 Ryota Yamazaki 1 and Naohiko Shimizu 2 In this paper, we will practice verification using our design method. This method generates logic synthesizable HDL from UML diagrams. We illustrate Hard-ware structure using UML Class, Activity, and State-machine diagrams. In verification, we practice same design using this design method and hand design method. And we evaluate verification result. 1. LSI 1 Tokai University 2 /IP ARCH, Inc. Tokai University / IP ARCH, Inc. C SystemC (RTL) (HDL) 1) LSI System System Unified Modeling Language(UML) 2) UML 3)4) UML 5) UML UML2 6) UML2 UML ACT2 COMP 7) ACT2 COMP UML2 ACT2 UML STA2 8) STA2 COMP STA2 UML 2 UML 3 4 5 2. UML 2.1 UML 1 UML UML XML Metadata Interchange(XMI) 9) UML XMI UML UML 1 UML 1 c 2011 Information Processing Society of Japan
Structure Modeling of Hardware Structure XMI (Class) UML2 Fig. 1 Requirements Analysis System Analysis The UML modeling with the manual entry Action UML Modeling Tool Behavior Modeling of Hardware XMI (Activity) ACT2 COMP State XMI (State Machine) STA2 1 The flow of the our design method. UML2 XMI 1 UML ACT2 XMI STA2 XMI UML COMP Fig. 2 TOP_mod + T_in : input[1] + T_out : output[1] - Proc0() SUB_mod + S_in : input[1] + S_out : output[1] - S_wire : wire [1] + S_fanc() ( a )UML Class diagram [1] +sub_mod0 Synthesis of byuml2 declare TOP_mod{ input T_in[1]; output T_out[1]; declare SUB_mod{ input S_in[1]; output S_out[1]; module TOP_mod{ SUB_mod sub_mod0; proc_name Proc0; proc Proc0{ module SUB_mod{ wire S_wire[1]; function S_fanc{ ( b ) 2 The flow to generate from the class diagram. 2.2 2. 2(a) UML. UML UML2 2(b) 6). TOP mod 1bit T in T out Proc0 sub mod0. Proc0 - proc. SUB mod 1bit S in S out S wire S func S func + func. 2.3 3. 3(a) UML. UML ACT2 3(b) 7). seq seq clock 2 c 2011 Information Processing Society of Japan
Fig. 4 Fig. 3 S_wire := ^S_in S_out = S_wire ( a )UML activity diagram [EVENT2] [EVENT3] Synthesis of by ACT2 seq{ { S_wire := ^S_in; S_out = S_wire; ( b ) 3 The generate from the activity diagram. State1 do/activity1 State2 do/activity2 [EVENT1] Synthesis of by STA2 ( a )UML State machine diagram state_name State1,State2; state State1{ // Activity1 if(event1)goto State2; state State2{ // Activity2 if(event2)goto State1; if(event3)goto finish; ( b ) 4 The generate from the state machine diagram. par clock 2.4 4. 4(a) UML. UML STA2 4(b) 8) proc state declare TOP_mod{ input T_in[1]; output T_out[1]; declare SUB_mod{ input S_in[1]; output S_out[1]; module TOP_mod{ SUB_mod sub_mod0; proc_name Proc0; proc Proc0{ module SUB_mod{ wire S_wire[1]; function S_func{ by class diagram Fig. 5 Put behavior by COMP state_name State1,State2; state State1{ // Activity1 if(event1)goto State2; state State2{ // Activity2 if(event2)goto State1; if(event3)goto finish; by state machine diagram Put behavior by COMP (Action1) (Action2) seq{ { S_wire := ^S_in; S_out = S_wire; by activity diagram 5 The generate logic synthesizable from the each. EVENT if goto. 2.5 UML 5 COMP 1 COMP 1 3 c 2011 Information Processing Society of Japan
HDL Design Requirements Analysis Debug Completion (on the FPGA) System Analysis UML Design Debug Completion (on the FPGA) 6 Fig. 6 The flow of verification. 3. 3.1 FPGA 40pin connector Serial port interface Synchronous timing signals and RGB data Serial port interface LCD touch panel AD converter 7 LTM Fig. 7 The overview of the LTM. Analog coordinates signals 6 4 2 1 6 8 4 2 2 HDL ( ) UML ( UML ) FPGA 3.2 LTM LTM LTM terasic LCD LTM RGB 8bit HD VD2 LTM_main + ADC_PENIRQ_n : input[1] + SCEN : output[1] + ADC_DCLK : output[1] + NCLK : output[1] + GREST : output[1 + HD : output[1] + VD : output[1] + DEN : output[1] + R : output[8] + G : output[8] + B : output[8] + func() MicroWire [1] +MW_CTRL + SCEN : output[1] + ADC_DCLK : output[1] - r_scen : reg[1] - r_clk_cnt : reg[7] - r_dclk_on : reg[1] + wire_sig_ctrl() + set_signal() + out_signal() + ADC_DCLK_CTRL.CLKMHz5_enable() ADC_DCLK_ctrl + CLKMHz5_ctrl : output[1] - r_clk_cnt : reg[4] - r_adc_dclk : reg[1] # CLKMHz5_enable() + CLKMHz5_ctrl() [1] +IO_CTRL [1] +ADC_DCLK_CTRL Fig. 8 IO_ctrl + ADC_PENIRQ_n : input[1] + R : output[8] + G : output[8] + B : output[8] - r_red : reg[8] - r_green : reg[8] - r_blue : reg[8] - r_rgb_ctrl[2] + display_ctrl(adc_penirq_n) + set_signal() + out_signal() + PAD_CTRL.display_touch() LCD_sync + NCLK : output[1] + HD : output[1] + VD : output[1] + DEN : output[1] - r_nclk : reg[1] - r_hd : reg[1] - r_vd : reg[1] - r_hden : reg[1] - r_vden : reg[1] - r_den : reg[1] - r_clk_cnt : reg[11] - r_lin_cnt[10] [1] + PAD_CTRL + sync_sig_ctrl() + set_signal() + out_signal() + CLK_CTRL.CLKMHz25_enable() PAD_ctrl + i_signal : input[1] - r_clk_cnt : reg[28] - r_sig_buf : reg[1] # display_touch() + state_touch( i_signal ) [1] +LCD_SYNC 8 LTM The class diagram of the LTM controller. [1] + CLK_CTRL CLK_ctrl + NCLK : output[1] - r_nclk : reg[1] - r_nclk_buf : reg[1] # CLKMHz25_enable() + CLKMHz25_ctrl() LTM 7 LTM LCD AD 40 LCD FPGA RGB AD 40 FPGA LTM 3.3 2 LTM 4 c 2011 Information Processing Society of Japan
(Class) auto generate auto generate logic synthesis (Activity) COMP description nsl2vl Verilog HDL description ALTERA tool FPGA (State-machine) Fig. 9 9 FPGA (UML ) The flow of implementation on the FPGA(UML design team). 3.3.1 UML UML UML 8 UML 8 UML LTM LTM main IO ctrl PAD ctrl LCD sync CLK ctrl MicroWave ADC DCLK ctrl 6 IO ctrl PAD ctrl LCD LCD sync CLK ctrl LCD MicroWire ADC DCLK ctrl 9 UML LTM FPGA LTM UML UML nsl2vl verilog HDL verilog HDL ALTERA FPGA 10 11 FPGA LTM 3.3.2 12 LTM Main CHANGE Hz LCDtiming LCD DISPLAY CHANGE Hz LTM LCDtiming LCD 10 LTM(UML ) Fig. 10 The operating LTM(UML design team). CHANGE_Hz NCLK ADC_ PENIRQ_n LCDtiming HD VD DEN Main LCD_DISPLAY DEN ADC_ PENIRQ_n R G B 8 8 8 SCEN NCLK HD VD DEN 12 LTM ( ) Fig. 12 The block diagram of LTM controller(hand design team). R G B 11 LTM(UML ) Fig. 11 The LTM after touch detection (UML design team). (Hand Design) nsl2vl Verilog HDL description ALTERA tool FPGA auto generate logic synthesis 13 FPGA ( ) Fig. 13 The flow of implementation on the FPGA(Hand design team). 5 c 2011 Information Processing Society of Japan
UML 4 3 30 4 1 UML HDL UML UML UML UML 14 LTM( ) Fig. 14 The operating LTM(hand design team). 15 LTM( ) Fig. 15 The LTM of touch detection (hand design team). LCD DISPLAY LCD 13 LTM FPGA nsl2vl verilog HDL Verilog HDL ALTERA FPGA 14 15 FPGA LTM 4. 4.1 UML LTM 1 10 5 LTM UML 3 9 UML UML UML UML UML 1 11 UML LTM UML 22 27 30 LTM 2 AL- 1 Table 1 The verification data. The item The UML design team The hand design team unit The requirements Analysis 10 hour The system Analysis 5 hour The design time 4 3.5 hour The debug time 3 9 hour The number of error 1 11 piece The total time 22 27.5 hour 6 c 2011 Information Processing Society of Japan
TERA CycloneII EP2C70F896C6 UML UML LTM 269.76MHz LTM 339.79MHz UML 4.2 LTM UML UML 1 16 16 UML UML UML UML Table 2 2 LTM The logic synthesis result of The LTM. The item The UML design team The hand design team unit The logic cell 86 90 piece The power consumption 261.45 252.84 [mw] The critical path 3.707 2.943 [ns] The frequency 269.76 339.79 [MHz] 30 25 20 15 10 5 0 Time(hour) 10 15 18:30 27:30 19 22:30 RAT SAT DsT DbT Fig. 16 : The UML Model diagram Design : The Hand Design RAT: Requirements Analysis Time SAT: System Analysis Time DsT: Design Time DbT: Debug Time Manufacturing Process 16 The graph of design time of the each method. UML UML UML UML UML UML 5. UML HDL LCD LTM 22 27 30 7 c 2011 Information Processing Society of Japan
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