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1 STRJ WS: March5, 29, 特別講演設計技術から見た半導体集積回路の省電力技術東京大学大規模集積システム設計教育研究センター (VDEC) 1 生産技術研究所 2 高宮真

2 Outline 2 低電力設計技術の動向 (1) 低電圧 (2) 細粒度制御 (3)3 次元ロジック回路の電源電圧の下限 (V DDmin ) 細粒度基板バイアス制御による低電力化 3 次元 SSD の NAND フラッシュ向け昇圧回路による低電力化 (SSD: Solid State Drive)

3 電源電圧 (V DD ) の低減の必要性 3 電源電圧 (V) 研究のターゲット High-performance logic Low-power logic Design rule ITRS 年 P switching ƒv DD 2 P leakage I leakage V DD DRAM half pitch (nm) 9nm 65nm 45nm と V DD =1V が続いたが今後は電力と信頼性の観点から V DD の低減が必須

4 4 エネルギー効率最適は低 V DD で実現 Normalized delay & power Delay Power PD product V DD [V] Normalized PD product 9nm CMOS SPICE Power, Delay 積 (PD 積 = エネルギー ) は V DD =.2-.3V で最小速度が問われないアプリでは低 V DD が energy efficient

5 5 Energy Efficient な超低 V DD ロジック超低 V DD ロジックに関する初めての企業 (Intel) からの報告 V DD =23mV まで動作はするが 32mV がエネルギー効率最高 H. Kaul, M. Anders, S. Mathew, S. Hsu, A. Agarwal, R. Krishnamurthy, and S. Borkar, "A 32mV 56µW 411GOPS/Watt ultralow voltage motion estimation accelerator in 65nm CMOS," IEEE ISSCC, pp , Feb. 28.

6 6 時空間の細粒度電圧制御がトレンド Time step of power control ns μs Static 近年の低電力 VLSI 回路技術の方向性 Single Domain Common f CLK, V DD, V TH Domain1 f CLK1, V DD1, V TH1 Conventional LSI 1 4 Future LSI 2 3 n f CLK3, V DD3, V TH3 f CLKn, V DDn, V THn Number of power control domain on a chip

7 7 細粒度制御には 3 次元技術との連携が必須 Interposer L & C cell array Power supply & other wires Inductors Capacitors Embedded Pads & bumps Package Sensor, MEMS, High voltage generation, Analog, RF etc. (3D stacked) Stacked memories Parallel processors with own DC-DC converters Base chip

8 8 細粒度と 3 次元に対する我々の取り組み電源電圧の下限 (V DDmin ) の追求チップ内トランジスタばらつき測定 [1] ロジック回路のV [2-3] DDmin 今回発表空間的細粒度制御今回発表製造後の細粒度基板バイアス制御による低電力化 [4] メニーコア向けテスト手法 [5] 3 次元積層を用いたオンチップDC-DCコンバータ [6-7] 時間的細粒度制御電源電圧基板バイアスを高速に変化させる加速回路 [8-11] 電源ノイズキャンセル回路 [12] 今回発表 3 次元集積技術 3 次元 SSDのNANDフラッシュ向け昇圧回路による低電力化 [13]

9 Outline 9 低電力設計技術の動向 (1) 低電圧 (2) 細粒度制御 (3)3 次元ロジック回路の電源電圧の下限 (V DDmin ) 細粒度基板バイアス制御による低電力化 3 次元 SSD の NAND フラッシュ向け昇圧回路による低電力化 (SSD: Solid State Drive)

10 1 Minimum Operating Voltage (V DDmin ) 2 Simulated V out Voltage (mv) V out V DD V DDmin Time (μs) V DDmin is defined as the supply voltage (V DD ) when the RO s stop oscillation. RO s are useful V DDmin detectors.

挟ピッチかつ広範囲のTrアレー (2) 非選択 Trのリークカット規格化 V TH 1.6 1.4 1.2 1..8.6.4.2. 1 1 Power (a.u.

11 チップ内トランジスタばらつき 11 Data clk DQ DQ DQ DQ DQ V sel V unsel V D Measured transistor VS V bs V bs V sel V D (1.V) V s (V) GND V unsel 4mm (4 transistors) 9nm CMOS 1 Transistor Array 4mm トランジスタばらつき測定回路キー技術 (1) 挟ピッチかつ広範囲のTrアレー (2) 非選択 Trのリークカット規格化 V TH Power (a.u.)1 4 トランジスタトランジスタ位置 (µm) 1E 空間周波数 (1/µm) 頻度フーリエ変換チップ内 V TH ばらつきはランダムチップ内 V TH ばらつきは 4mm の範囲内でランダム細粒度の基板バイアス制御では補償不可

12 12 Analysis of Origin of V DDmin V DD V 1 V 2 V 3 V 1 V Each transistor has random V TH. V INV of inverter, V 1 ~V 11 (mv) V 2 V 4 V 1 V 3 L V 5 V 6 V 9 V 7 V 8 V 1 V Inverter number H H L H V INV V 1 ~V 11 V DD =85mV Fail V OUT_LOW_7 > V INV_8 Monte Carlo SPICE

13 13 RO Circuits to Enable V DDmin Measurement V DD2 V DD2 V DD 1V Low swing 1V swing V SS2 V SS2 (manually tuned) Ring Oscillator V SS V Output Buffer The low swing output of RO is amplified to 1-V swing by the output buffer.

14 14 V DD Dependence of Oscillation Frequency variation 15 Frequency Variations (= σ / average) (%) 1 5 実測 9nm CMOS 11-stage ring oscillators 13 dies V DD (V) t pd Δ pd = Δ dvth t pd dt DD TH ( V V ) DD CV V TH Δtpd α ΔV t V V pd DD TH TH Δf Δt α f t V V pd Δ α pd DD TH V TH Relative frequency variations increases with reduced V DD.

15 ゲート遅延の V DD 依存 15 Oscillation frequency (Hz) 1G 1G 11-stage 1M 1M 1M 11-stage 1k 13 dies 1k V DD (V) V DDmin 実測 9nm CMOS インバータ RO 11-stage 11-stage 11-stage Layout 1mm 4μm Micrograph 低 V DD 回路の問題 : 低速 PVT ばらつきに敏感対策 : 並列動作 adaptive 制御

16 16 Measured Die-to-Die Distribution of V DDmin stage (1) Inverter RO s k-stage (4) Number of dies stage (2) 1k-stage (3) Number of dies k-stage (5) M-stage (6) V DDmin (mv) V DDmin (mv)

17 論理ゲートの V DDmin を RO で調査 mm 平均 V DDmin (mv) k 1k 1k 1M リングオシレータ段数大規模になるほどより高いV DDmin が必要に大規模ロジックになるほど低 V DD 化が困難 1.3mm 1M stage inverter RO 実測 9nm CMOS インバータ RO 複数チップ測定

18 18 Analysis of Die-to-Die V DDmin Variations V DDmin (mv) Inverter RO s 15 dies 1 1 1k 1k 1k 1M Number of stages The die-to-die V DDmin variations are not systematic but random.

19 19 Summary of Measured V DDmin Average V DDmin (mv) NAND RO x4 inverter RO 2NAND RO Inverter RO (3 different lots) (1) Large # of stages (2) Large # of stacked Tr s (3) Narrow gate width increase V DDmin k 1k 1k 1M Number of stages

20 2 Comparison of Measured and Calculated V DDmin Average V DDmin (mv) Measurement MATLAB x4 inverter RO Inverter RO s Inverter RO Name Sim75 Sim1 Sim125 Sim k 1k 1k 1M Number of stages σv TH (mv) nmos pmos Sim15 Sim125 Sim1 Sim75 Remarks x.75 x1 x1.25 x1.5

21 21 Reason Why Average V DDmin Increases with # of RO Stages Probability distribution function The largest value distributions f max (x,n) of n samples which have Gaussian distribution f(x) x 2σ f ( x) n= x σ x x + σ n=1 1 x + 2σ x x max x + 2 log x + 3σ nσ ( x ) f, max 1 1 n x + 4σ x + 5σ x + 6σ x at n=1 max 6 x + 7σ

22 22 Comparison of Monte Carlo and Model Average V DDmin (mv) Measurement Matlab (Monte Carlo simulation) Model calculation x4 inverter RO Inverter RO x max x + 2 log 1 nσ Sim15 Sim125 Sim1 Sim k 1k 1k 1M n: Number of stages The equation intuitively explains the reason why the average V DDmin increases with the number of RO stages.

23 23 Adaptive Body Bias Control to Reduce V DDmin Simulated V DDmin =89 mv (Initial) Body bias control V DDmin =87 mv The body bias of pmos is adaptively controlled to minimize V DDmin and the body bias of nmos is fixed.

24 24 Fine-Grain Adaptive Body Bias Control to Reduce V DDmin Simulated Vb1 Vb2 Vb3 Vb4 Vb5 Vb V DDmin =85 mv Vb1 Vb3 Vb5 Vb7 Vb9 Vb11 Vb2 Vb4 Vb6 Vb8 Vb V DDmin =43 mv When inverter-by-inverter body bias is applied, V DDmin is drastically reduced to 43mV. But it is impractical.

25 25 V DDmin Dependence on Body Bias of Both nmos and pmos Measured Initial V DDmin (mv) nmos Body Bias (V) pmos Body Bias (V) Common body bias control allows to reduce V DDmin by only 4mV.

26 Outline 26 低電力設計技術の動向 (1) 低電圧 (2) 細粒度制御 (3)3 次元ロジック回路の電源電圧の下限 (V DDmin ) 細粒度基板バイアス制御による低電力化 3 次元 SSD の NAND フラッシュ向け昇圧回路による低電力化 (SSD: Solid State Drive)

27 27 細粒度基板バイアス制御による低電力化 V N1 V P1 V N2 V P2 V N3 V P3 V N4 V P4 電力 % -5% -1% -15% As-fabricated 実測 N8P8 Simulated Annealing >19% power reduction at 2 iterations V N5 V P5 V N6 V P6-2% 機能プロセス V N7 V P7 V N8 V P8-25% 64bit DES CODEC 1V, 9nm CMOS 1 つの機能ブロックを 8 領域に等分割 Iteration count [times] 基板バイアス 16 変数の最適化基板バイアスのグローバル最適化により電力を 19% 以上削減 post-fabrication tuning により設計ばらつきを補正

28 Outline 28 低電力設計技術の動向 (1) 低電圧 (2) 細粒度制御 (3)3 次元ロジック回路の電源電圧の下限 (V DDmin ) 細粒度基板バイアス制御による低電力化 3 次元 SSD の NAND フラッシュ向け昇圧回路による低電力化 (SSD: Solid State Drive)

29 Importance of 2V generator in NAND 29 Write time is dominant over read time. Write 8 to 16 chips simultaneously. 2V or higher program voltage for write Energy during write should be reduced. Read time ~5µs Write time ~8µs Program voltage:2v Floating gate V V Injection V Write operation of NAND flash High-speed low-power 2V generator is required.

30 3 Conventional SSD with charge pump Each NAND flash has charge pump for 2V. 5 to 1% area of NAND flash chip! NAND controller Interposer NAND flash Charge pump DRAM

31 Issues on charge pump 31 Serial MOS diodes lose energy. Large number of stages for low V DD V DD V OUT =2V Clk Clk Large capacitance area Energy loss Large capacitance for large current V OUT V DD Bucket brigade

32 32 Voltage scalability of charge pump Energy during write (a.u.) Others Memory core Charge pump 3.3V NAND* (Core 2.5V) *K. Takeuchi, et al., ISSCC 26 C BL V 2 Energy increases! C BL : Bit-line capacitance Memory core Charge pump 1.8V NAND (simulated) Energy by charge pump increases!

33 33 Proposed 3D-SSD with boost converter Realizing low power and low cost Boost converter (shared) NAND controller Adaptive controller Low-cost High-voltage MOS Spiral inductor Smaller die size Interposer Charge pump NAND flash Charge pump DRAM

34 34 Advantages of Boost converters Frequency, duty cycle Conversion ratio (V OUT /V DD ) Inductance Output current T ON T OFF V DD V OUT Frequency = 1 / (T ON + T OFF ) Duty cycle = T ON / (T ON + T OFF ) Clk High conversion ratio, large output current High efficiency Small chip area Off-chip inductor

35 35 Boost converter & NAND Co-operation High voltage MOS (.35mm.5mm) Inductor (5mm x 5mm) 16Gb NAND flash Adaptive controller (.67mm.28mm)

36 36 Comparison of energy during write Energy during write (a.u.) Others Memory core Charge pump Conventional 3.3V NAND* (Core 2.5V) *K. Takeuchi, et al., ISSCC 26. Memory core Charge pump Conventional 1.8V NAND (Simulated) Total -68% Memory core This work 1.8V NAND Boost converter with adaptive control

37 Summary of key features 37 This work (Measured) Charge Pump (Simulated) Transient energy ( 15V) 3nJ (12%) 253nJ (1%) Rising time ( 15V).92µs (27%) 3.45µs (1%) Chip area (HV-MOS).175mm 2 (15%) 1.19mm 2 (1%) Technology 2V CMOS (High voltage MOS) process Chip area (Adaptive controller).188mm Technology 1.8V.18µm (Adaptive controller) standard CMOS Supply voltage 1.8V 1.8V

38 まとめ 38 低電力設計技術の 3 つのキーワード (1) 低電圧 (2) 細粒度制御 (3)3 次元チップ内製造ばらつきはランダム (9nm CMOS, 4mm) 細粒度制御では対処不能一方設計ばらつきは細粒度制御で対処可能リングオシレータの段数を 11 段から 1M 段にすると V DDmin は 9mV から 343mV に増加大規模ロジックの低電圧化は困難革新的な回路技術が必要 3 次元による低電力化の例 SSD

39 参考文献 (1) 39 [1] D. Levacq, T. Minakawa, M. Takamiya, and T. Sakurai, "A Wide Range Spatial Frequency Analysis of Intra-Die Variations with 4-mm 4 x 1 Transistor Arrays in 9nm CMOS," IEEE Custom Integrated Circuits Conference (CICC), San Jose, USA, pp , Sep. 27. [2] T. Niiyama, P. Zhe, K. Ishida, M. Murakata, M. Takamiya, and T. Sakurai, "Dependence of Minimum Operating Voltage (V DDmin ) on Block Size of 9-nm CMOS Ring Oscillators and Its Implications in Low Power DFM," IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, USA, pp , March 28. [3] T. Niiyama, P. Zhe, K. Ishida, M. Murakata, M. Takamiya, and T. Sakurai, "Increasing Minimum Operating Voltage (V DDmin ) with Number of CMOS Logic Gates and Experimental Verification with up to 1Mega-Stage Ring Oscillators," International Symposium on Low Power Electronics and Design (ISLPED), Bangalore, India, pp , Aug. 28. [4] Y. Nakamura, D. Levacq, L. Xiao, T. Minakawa, T. Niiyama, M. Takamiya, and T. Sakurai, "1/5 Power Reduction by Global Optimization Based on Fine-Grained Body Biasing," IEEE Custom Integrated Circuits Conference (CICC), San Jose, USA, pp , Sep. 28. [5] T. Niiyama, K. Ishida, M. Takamiya, and T. Sakurai, "Expected Vectorless Teacher-Student Swap (TSS) Test Method with Dual Power Supply Voltages for.3v Homogeneous Multi-core LSI s," IEEE Custom Integrated Circuits Conference (CICC), San Jose, USA, pp , Sep. 28. [6] K.Onizuka, H. Kawaguchi, M. Takamiya and T. Sakurai, "Stacked-chip Implementation of Onchip Buck Converter for Power-Aware Distributed Power Supply Systems," IEEE Asian Solid- State Circuits Conference (A-SSCC), Hangzhou, China, pp , Nov. 26. [7] K. Onizuka, K. Inagaki, H. Kawaguchi, M. Takamiya, and T. Sakurai, "Stacked-Chip Implementation of On-Chip Buck Converter for Distributed Power Supply System in SiPs," IEEE Journal of Solid-State Circuits, Vol. 42, No. 11, pp , Nov. 27.

40 参考文献 (2) 4 [8] K.Onizuka and T. Sakurai, "V DD -Hopping Accelerator for On-Chip Power Supplies Achieving Nano-Second Order Transient Time," IEEE Asian Solid-State Circuits Conference (A-SSCC), Hsinchu, Taiwan, pp , Nov. 25. [9] K. Onizuka, H. Kawaguchi, M. Takamiya, and T. Sakurai, "V DD -Hopping Accelerators for On- Chip Power Supply Circuit to Achieve Nanosecond-Order Transient Time," IEEE Journal of Solid-State Circuits, Vol. 41, No. 11, pp , Nov. 26. [1] D. Levacq, M. Takamiya and T. Sakurai, "Backgate Bias Accelerator for 1ns-order Sleep-to- Active Modes Transition Time," IEEE Asian Solid-State Circuits Conference (A-SSCC), Jeju, Korea, pp , Nov. 27. [11] D. Levacq, M. Takamiya, and T. Sakurai, "Backgate Bias Accelerator for sub-1 ns Sleepto-Active Modes Transition Time," IEEE Journal of Solid-State Circuits, Vol. 43, No. 11, pp , Nov. 28. [12] Y. Nakamura, M. Takamiya, and T. Sakurai, "An On-Chip Noise Canceller with High Voltage Supply Lines for Nanosecond-Range Power Supply Noise," IEEE Symposium on VLSI Circuits, Kyoto, pp , June 27. [13] K. Ishida, T. Yasufuku, S. Miyamoto, H. Nakai, M. Takamiya, T. Sakurai, and K. Takeuchi, "A 1.8V 3nJ Adaptive Program-Voltage (2V) Generator for 3D-Integrated NAND Flash SSD," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, USA, pp , Feb. 29.

RW1097-0A-001_V0.1_170106

RW1097-0A-001_V0.1_170106 INTRODUCTION RW1097 is a dot matrix LCD driver & controller LSI which is fabricated by low power CMOS technology. It can display 1line/2line/3line/4line/5line/6lines x 12 (16 x 16 dot format) with the