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1 STRJ ITRS 2003 LSI MIRAI
2 100nmCMOS - Si SOI CMOS SOI MOSFET CMOS
3 100nmCMOS
4 trade-off Sub 100 nm CMOS trade-off x j (ext. conc.) Nsub Vdd Vth design EOT S or Si Nsub EOT
5 something S/D EOT SiGe high k Si SiGe SOI (2 Fin etc.
6 MOSFET Si SiGe Ge PD-SOI SOI FD-SOI (, FinFET, GAA etc.)
7 List of (Column IV) High Mobility Channels applicable to MOSFETs n-mosfet (high electron mobility) strained Si on relaxed Si 1-x Ge x virtual sub. pure Ge channel? (Ge problem in MOS interface high k / Ge MIS?) p-mosfet (high hole mobility) strained Si on relaxed Si 1-x Ge x virtual sub. strained Si 1-x Ge x on Si sub. (Si 1-x Ge x buried channel problems in C g, SCE etc.) pure Ge channel? strained-si channel for CMOS application (surface channel SiGe pmos and pure Ge CMOS under new gate insulator technology)
8 ITRS Technology Booster Factors ASIC HP (High Performance) (ITRS 2003 Edition) (nm) MOSFET (nm) Mobility Improve F. 1x 1.3x 2.0x 2.0x 2.0x 2.0x Velocity Improve F. 1x 1x 1x 1.1x 1.1x 1.3x Eeff reduction F. 1x 1x 1x 0.6x 0.5x 0.5x Device Structure Bulk Bulk Bulk SOI DG DG I dsat 0 V dsat = L 1 µ 2 = 1 E eff C d + V ox _ el c gt W L E c V gt V 2ν µ eff dsat µ eff K mu µ eff 0 ν sat = K ν sat = Vs sat0 = mobility imp. F. velocity imp. F.
9 v s : v s = µ s E s N s source I sat = qn s source v s µ s % Mobility Shift Velocity vs. mobility shift for 45-nm NFET under applied uniaxial strain, δv/δµ= (at L g of sub 100 nm) I sat µ +4 Vgs = 1V Vgmi +2 0 % Velocity Shift Lochefeld et al., EDL(2001) Vidi
10 Si Yamada et al, TED(1994)1513 Rim et al., TED(2000)1406 ν sat ν sat τ w
11 - Si SOI CMOS
12 SiGe MOSFET SOI G SiO 2 S n + poly-si n + Si n + Si 1-x Ge x SiGe Si Ge: 0 % x % Mizuno et al., IEDM(1999)934 Si Mizuno et al., EDL-21(2000)230 Takagi, IJHSES-10(2000)155 J. Welser et al., IEDM(1992) 1000 Takagi, IEICE, E85-C(2002)1064 D G SiO 2 S gate D p + n + Si n p + Si 1-x Ge x SiO 2
13 <100> spin -orbit Influence of Strain on Conduction and Valence Band Structures <001> E C <001> <010> degenerate E V strained Si SiGe 4 fold 6 fold degenerate heavy hole light hole without strain 2fold 2 fold <100> out-ofplane spin -orbit <001> <010> light k in-plane heavy tensile strain mobility enhancement reduction in (averaged) conductivity mass suppression of inter-valley scattering
14 Methods for Preparing Strained-Si Layers Bulk relaxed SiGe buffer technology - SiGe graded buffer technique - other techniques (low temperature buffer, SiGe buffer including damaged layer etc.) Relaxed SiGe-On-Insulator (SGOI) technology - Wafer bonding - Thermal melting of SiGe/SOI - SIMOX for SiGe/Si substrates - Ge condensation due to oxidation Single-layer strained-soi technology - Wafer bonding Other technologies - Use stressors (STI, capping layer(s), SiGe S/D, silicides, poly-si gate etc.)
15 Si CMOS % Ion-Ioff improvement 100nm MOS Si trade-off 18% τ pd RO τ pd 6.5ps (T. Sanuki et al., IEDM2003, p. 65) (Wang et al., IEDM2003, p. 61)
16 SOI SOI substrates SiGe/Si substrates BOX SOI sub. BOX Si Si sub. Si 1-x Ge x (x>0.1) Si Si sub. Oxide (SiO 2 ) Higher Ge content Si 1-x Ge x (x>0.3) slip conventional SOI sub. SiGe epitaxy (Ge condensation) oxidation Ge SiGe epitaxy on Si sub SIMOX process Strained-Si epitaxy Si 1-x Ge x (x<0.15) Si sub. Si 1-x Ge x (x<0.1) Si sub. thin and strained SiGe O + implantation + high T anneal BOX strained Si layer
17 200 mm strained SOI wafer 1 T SGOI / T Si =90nm / 25nm Strain (%) x eff Ge condensation for SiGe/SOI + regrowth of strained Si T Strained Si /T SGOI = 25nm/90nm effective Ge content: 21% Position (mm) Variation in strain Uniform in wafer scale Void free
18 Si MOSFET SiGe S/D pmos Intel, IEDM02, 03) Si STI capping layer, silicide SOI MOSFET (IEDM01) (02) IBM, Intel, TSMC, Princeton, 03) AMD, IBM (IEDM03)
19 Application of Strained-Si FET into 90 nm TN (Intel) (S. Thompson et al., IEDM2002, p. 61, T. Ghani et al., IEDM2003, p. 978) high hole mobility enhancement of 50 % even in high E eff at 17% of Ge content 20 % Ion improvement for both nmos and pmos pmos compressive strain due to SiGe S/D nmos tensile strain due to SiN films nmos pmos mobility vs E eff pmos
20 Strained-Si Directly-On-Insulator MOSFET ( K. Rim et al., IEDM (2003) p. 49) Fabrication of bonded single strained-soi sub. by smart cut Demonstration of n- and p-mosfets with L g of 60 nm
21 MOSFET SOI
22 MOSFET Wong et al, IEDM 1997 Lee et al, IEDM 1999 Hergernrother et al, IEDM 1999 Hisamoto et al, IEDM 1998, Huang et al, IEDM 1999
23 SOI SOI FD SOI (single gate) T SOI ~ L g /4 - L g /3 FinFET (double gate) T SOI (Fin T SOI ~ L g /2 - L g /1.5 SOI D. Hisamoto, T SOI =0.7L min (= L min /1.5 ) IEDM short course (2003)8
24 SOI 10nmMOSFET B. Doris et al., IEDM2002, p. 267 L g = 6 nm, 12 nm L g = 14 nm
25 Electron Mobility [cm 2 /Vsec] SOI MOSFET (K. Uchida, H. Watanabe, A. Kinoshita, J. Koga, T. Numata and S. Takagi, IEDM(2002) 47) 4.08nm 3.37nm 2.99nm ~60nm T = 300K T SOI = 2.48nm Universal Mobility Enhancement Effective Field [MV/cm] Hole Mobility [cm 2 /Vsec] ~60nm 7.03nm 5.49nm T = 300K Universal 3.57nm 3.08nm 2.88nm T SOI = 2.72nm Effective Field [MV/cm] SOI
26 Electrical Properties of sub-1 nm Extremely-thin SOI (K. Uchida, J. Koga, and S. Takagi, IEDM (2003) p. 805) 1.0 nm 0.7 nm
27 SOI ~ K. Uchida et al., IEDM (2002)47 (a) (b) GOX SOI BOX Interface roughness Thickness fluctuation E C [ev] 0.15 Potential fluctuation V 0.1 (c) T SOI [nm] potential barrier due to quantum confinement effect Potential barrier due to larger quantum confinement effect E = T Electrons 1 6 δt SOI -limited 0.05 mobility µ r µ r TSOI Thermal Energy V 0 SOI E F = E C E n = 2 n h V * 3 SOI 4m TSOI h * 2 8m tsoi electrons Si/SiGe; A. Gold, Phys. Rev. B35 (1987)723 GaAs/AlAs; H. Sakaki et al., APL (1987)1934 2
28 Mobility [cm 2 /Vsec] 1000 SOI 6 T SOI T=25K E eff =0.1MV/cm δt SOI [atomic layer] δt SOI should be smaller than this line 4 5 T SOI [nm] SOI 4nm MOSFET T SOI [nm] SOI T 6 SOI 3 SOI 6 7
29 MOSFET
30 MOSFET Ballistic S D S D CMOS Ballistic Ballistic Efficiency for L g of nm (Natori, SSDM2002, p.17) for L g of 50 nm (Antoniadis, VLSI Symp.2002, p.2) v inj N source s I sat = qn s source v inj Ballistic
31 Carrier Injection Velocity [ cm/s ] Ballistic MOSFET 5x10 7 4x10 7 3x10 7 2x10 7 v Ballistic (100) 2 1/2 N s K. Natori, JAP76 (1994) 4879 inj k B T 12 v 2 th mx π V th 1/ 2 1.5x10 7 E 0 E V (ii) 0 F D 2 DOS 2D 4 4 4Ns vinj = vf = 3π 3π m 10 7 xd2 D M v D D = mxm 2 y Ns [ cm -2 ] E F (i) πh M v
32 I-V curves under full ballistic transport Drain Saturation Current [ µa/µm ] (S. Takagi, VLSI Symp. (2003) 115) Ion (45 nm TN) (2002) (100) Si Strained Si (Ge=20%) (111) Ge (100) SOI (3nm) (111) GOI (3nm) I off = 3µA/µm const. T OX = 0.5 nm V g [ V ] Even under ballistic transport, SOI, strained Si, Ge, and GOI can provide higher current drive, because of higher injection velocity Ultra-thin GOI MOSFET is one of the most promising device structures beyond 45 nm TN
33 CMOS
34 Planar technology Non-planar technology Future New Channel Structure Families New channel materials SOI-based devices 3D structure (DG) devices ( S. Takagi et al., IEDM (2003) 57 ) PDSOI bulk Strained- Si, SiGe, SiGeC MOS FDSOI UTB SOI back gate controlled FDSOI Gate All Around MOS FinFET vertical FET strained-soi, SGOI PD Ge channel MOSFET strained-soi, SGOI FD GOI Ge-On- Insulator) MOS Strained SOI /GOI CMOS 3D strained-soi, SGOI, GOI MOS Technology Node
35 Strained-Si on nothing (SSON) Structure Strained-Si on nothing (SSON) structure applicable to DG strained-si MOSFET Confirm strain of % in SSON region by nano-ed (electron diffraction) method relaxed SiGe Si sub. Gate electrode SSON channel BOX Strained-Si-on-nothing region K. Usuda et al., SOI conference 2003, p. 138 Si 0.72 Ge 0.28 layer Strained-Si layer BOX
36 Hole Mobility in SiGe-On-Insulator p-mosfet Strained-SiGe channel p-mosfet 2.3 time higher µ eff Surface channel structure (SiO 2 /SiGe interface) higher N ss Fully-depleted operation (T SiGe 20 nm) poly-si gate source SiGe SiO 2 Si gate oxide drain T. Tezuka, N. Sugiyama, T. Mizuno and S. Takagi, IEDM (2001) p. 946 Effective mobility (cm 2 /Vs) L/W=100/118 µm V d =-10 mv Effective field (V/cm) Improvement and understanding of SiO 2 /SiGe interface properties are important pmosfet x=0.42 x=0.35 x=0.28 universal Si control
37 High k / Ge MISFETs C.-O. Chui et al., IEDM (2002) 437 A. Ritenour et al., IEDM (2003) 433 high k / Ge MIS high k / Ge MISFET
38 Dual channel CMOS using pure Ge pmos Strained Si Strained SiGe or Ge Relaxed SiGe (50% Ge) Dual Channel C.W. Leitz et al., MRS Proc. 686(2002)113 M.J. Lee et al., IEDM (2003) 429 Very high hole mobility can be obtained for strained-sige p- MOSFETs with high Ge contents
39 GOI (Ge-On-Insulator) Structure fabricated by Ge Condensation Technique SiGe Ge condensation Ge SiO 2 SiO 2 SOI BOX Si sub. SiGe BOX Si sub. Ge BOX Si sub. Cross-sectional TEM SiO 2 100nm Surface Oxide Ge BOX Residual Si conc. < 0.01 % S. Nakaharai et al., Appl. Phys. Lett., vol. 83 (2003) 3516 Cross-sectional TEM 10 nm 100nm 7 nm 7nm Surface Oxide Ge Ge BOX BOX
40 70nm CMOS Si MOS near term SOI CMOS Si SOI SOI Si GOI MOSFET NEDO
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