Linda

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1 1 METROLOGY ITRS IC IC 1/10 FIN IC

2 2 3 SOI ITRS nm FINFET High-k Low-k FEP SOI 22nm Cu ( ) CIM computer integrated manufacturing APC advanced process control CoO(Cost Of Ownership)

3 CD Critical Dimension / ( Reference Materials Reference Materials ) ( ) FEP RMS Reference Measurement Systems / / IC IC / P/T Measurement Precision to Tolerance Ratio 1 P/T SPC Statistical Process Control / S/N (Sensor Based Metrology) Infrastructure needs / 1 For example, refer to SEMI E Guide For Measurement System Capability Analysis.

4 4 MEMS Micro-Electro-Mechanical Systems 32nm Table

5 5 Table nm / / / robust sensors starting materials SOI CD SOI Cu (Low-k) / Metrology Difficult Challenges / / RTA SOI SOI (Low-k) 3 CD High-k / Low-k / Si SOI <32nm 3 / / / 32nm CMOS SEM 3 3 Cu * SPC(Statistical Process Control) - Beyond

6 6 Table 117a Metrology Technology Requirements Near-term Year of Production Driver DRAM ½ Pitch (nm) (contacted) MPU/ASIC Metal 1 (M1) ½ Pitch (nm)(contacted) MPU Physical Gate Length (nm) Microscopy Inline, nondestructive microscopy process resolution (nm) for P/T=0.1 Microscopy capable of measurement of patterned wafers having maximum aspect ratio/diameter (nm) (DRAM contacts) [A] Materials and Contamination Characterization MPU Gate >20 >20 >20 >20 D1/ Real particle detection limit (nm) [B] MPU Minimum particle size for compositional analysis (dense lines on patterned wafers) (nm) Specification limit of total surface contamination for critical GOI surface materials (atoms/cm 2 ) [C] Surface detection limits for individual elements for critical GOI elements (atoms/cm 2 ) with signal-to-noise ratio of 3:1 for each element D1/2 5.00E E E E E E E E E E E E E E E E E E+08 MPU Gate MPU Gate Table117b Metrology Technology Requirements Long-term Years Year of Production Driver DRAM ½ Pitch (nm) (contacted) MPU/ASIC Metal 1 (M1) ½ Pitch (nm)(contacted) MPU Physical Gate Length (nm) Microscopy Inline, nondestructive microscopy process resolution (nm) for P/T=0.1 Microscopy capable of measurement of patterned wafers having maximum aspect ratio/diameter (nm) (DRAM contacts) [A] Materials and Contamination Characterization MPU Gate >20 >20 >20 >20 >20 >20 >20 D1/ Real particle detection limit (nm) [B] MPU Minimum particle size for compositional analysis (dense lines on patterned wafers) (nm) Specification limit of total surface contamination for critical GOI surface materials (atoms/cm 2 ) [C] Surface detection limits for individual elements for critical GOI elements (atoms/cm 2 ) with signal-to-noise ratio of 3:1 for each element D1/2 5.00E E E E E E E E E E E E E E+08 MPU Gate MPU Gate Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known Table117a b [A] [B] [C] FEP F

7 7 32nm 1 LSI LWR D.Herr ) Low-k Cu 2 3 (Microscopy) 2 IC Integrated Circuit 1 / CD IC 3 Telepresence IC

8 8 SEM Scanning Electron Microscopy CD at-line at-line offline 45nm CD ( ) 250 ev SEM SEM / DOF SEM SEM SEM SEM CD 90nm / 3 FIB Focused Ion Beam TEM(Transmission Electron Microscope ) STEM(Scanning Transmission Electron Microscope ) FIB He CD

9 9 SPM Scanning Probe Microscopy CD SEM Critical Dimension Measurement Scanning Electron Microscope SPM 3 nm (Far-field Optical Microscopy) ) Near-field Microscopy SEM SPM SPM SPM SPM SEM SPM SPM SEM SEM SEM SEM Lithography Metrology 4 MEF CD CD IC precision, accuracy, CD CD CD

10 10 CD CD CD 1 % 3σ 10 nm 3σ 15 % 200 nm P/T precision to tolerance = 0.1 K1 CD CD CD OPC( ) RET( ) CD absolute accuracy repeatability precision CD 2 LER CD CD CD-SEM / 193 nm EUVL CD-SEM 2 CD CD-SEM measurement variation precision CD-SEM SEM CD CD-SEM CD-SEM

11 11 2 CD APC CD SEM AFM CD CD CD precision CD CD-AFM CD CD-AFM 90 nm 3 / FIB(SEM+FIB) LER LWR LER LWR 2001 LWR LER LWR 2001 ITRS LER CD CD-SEM LER LER LER LWR LER/LWR 2 LER/LWR / CD 3σ LER/LWR R&D 3σ LER/LWR L y 3σ L y 2 2 L y

12 12 LER/LWR LER/LWR L 2 µm LER 10 nm y LER/LWR 10 nm y 2 µm LER/LWR LER/LWR 1/fm f m , y 10 nm 2 µm LWR 5% 4nm y 32nm node 2nm y 22nm node LWR y LER/LWR 2 µm 3σ LWR LWR CD LWR LWR/LER LWRmeas 2 = LWRactual 2 + σ ε2 LWR meas LWR actual σ ε reproducibility σ ε 2.5 nm accuracy LER/LWR LER/LWR LER/LWR LWR LER/LWR LER/LWR LER/LWR precision accuracy LER/LWR LER/LWR CD reproducibility precision SEMI precision reproducibility reproducibility repeatability reproducibility

13 13 ITRS CD precision CD golden TMU precision P TMU P TMU TMU CD CD SEM CD-AFM CD precision CD CD-SEM 2 CD-AFM FIB LER LWR LER precision CD CD / SEM SEM SEM CD

14 14 Low-k SOI SOI Kramers-Kronig n k 193nm EUV Si Si SPM SEM CMP chemical mechanical polishing Low-k Low-k DRAM NVM 20 % 25 % SEM Table 118a, b Table 119a, b, c, d EUV

15 15 Table 118a Lithography Wafer Metrology Technology Requirements Near-term Years Year of Production DRAM ½ Pitch (nm) (contacted) MPU/ASIC Metal 1 (M1) ½ Pitch (nm)(contacted) Flash ½ Pitch (nm) (Un-contacted Poly) MPU Physical Gate Length (nm) Printed gate CD control (nm) Uniformity (variance) is 12% of CD Allowed lithography variance = 3/4 total variance of physical gate length * Wafer dense line CD control (nm) * Uniformity is 13.5% of CD Allowed lithography variance = 3/4 total variance Wafer minimum contact hole (nm, post etch) from lithography tables Wafer contact CD control (nm)* Uniformity is 15% of CD = minimum contact hole size Allowed lithography variance = 2/3 total variance Line width roughness (nm, 3 σ) < 8% of CD *** Wafer CD metrology tool precision (nm) * 3σ at P/T = 0.2 for isolated printed and physical lines [A] Wafer CD metrology tool precision (nm) * (P/T=.2 for dense lines**) Wafer CD metrology tool precision (nm) * (P/T=.2 for contacts**)**** Wafer CD metrology tool precision (nm) * (P/T=.2) for LWR*** Maximum CD measurement bias (%) Aspect Ratio Capability for Trench Structure CD Metrology 15:1 15:1 15:1 15:1 15:1 15:1 15:1 15:1 20:1 Wafer overlay control (nm) Wafer overlay output metrology precision (nm, 3 σ)* P/T= * precision nm 3σ precision CD ** *** LER 2 3 LWR LWR= 2 (LER) **** CD FIB Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known

16 16 Table 118b Lithography Wafer Metrology Technology Requirements Long-term Years Year of Production DRAM ½ Pitch (nm) (contacted) MPU/ASIC Metal 1 (M1) ½ Pitch (nm)(contacted) Flash ½ Pitch (nm) (Un-contacted Poly) MPU Physical Gate Length (nm) Printed gate CD control (nm) Uniformity (variance) is 12% of CD Allowed lithography variance = 3/4 total variance of physical gate length * Wafer dense line CD control (nm) * Uniformity is 13.5% of CD Allowed lithography variance = 3/4 total variance Wafer minimum contact hole (nm, post etch) from lithography tables Wafer contact CD control (nm)* Uniformity is 15% of CD = minimum contact hole size Allowed lithography variance = 2/3 total variance Line width roughness (nm, 3 σ) <8% of CD *** Wafer CD metrology tool precision (nm) * 3σ at P/T = 0.2 for isolated printed and physical lines [A] Wafer CD metrology tool precision (nm) * (P/T=.2 for dense lines**) Wafer CD metrology tool precision (nm) * (P/T=.2 for contacts**)**** Wafer CD metrology tool precision (nm) * (P/T=.2) for LWR*** Maximum CD measurement bias (%) Aspect Ratio Capability for Trench Structure CD Metrology 20:1 20:1 20:1 20:1 20:1 20:1 20:1 Wafer overlay control (nm) Wafer overlay output metrology precision (nm, 3 σ)* P/T= * precision nm 3σ precision CD ** *** LER 2 3 LWR LWR= 2 (LER) **** CD FIB Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known

17 17 Table 119a Lithography Metrology (Mask) Technology Requirements: Optical Near-term Years Year of Production DRAM ½ Pitch (nm) (contacted) MPU/ASIC Metal 1 (M1) ½ Pitch (nm)(contacted) MPU gate in resist (nm) MPU Physical Gate Length (nm) Flash ½ Pitch (nm) (Un-contacted Poly) DRAM/Flash CD control (3sigma) (nm) CD uniformity (nm, 3 sigma) isolated lines (MPU gates), binary or attenuated phase shift mask [H] Wafer overlay control (nm) DRAM Contact after etch (nm) Wafer contact CD control (nm)* Uniformity is 13.5% of CD = minimum contact hole size Allowed lithography variance = 3/4 total variance Mask nominal image size (nm) [B] Mask minimum primary feature size [D] Optical Section Minimum OPC size (opaque at 4, nm) [D] Image placement (nm, multi-point) [F] CD uniformity allocation to mask (assumption) Mask error factor (MEF) from lithography tables isolated lines, binary MEEF dense lines, binary or attenuated phase shift mask [G] MEF contacts [G] CD Uniformity (3 Sigma at 4, nm) Refer to Lithography Chapter Table for Optical Mask Requirements Mask CD uniformity (nm, 3 sigma) isolated lines (MPU gates), binary or attenuated phase shift mask [H] Mask CD uniformity (nm, 3 sigma) dense lines (DRAM half pitch), binary or attenuated phase shift mask [J] Mask contact CD control (nm)* Uniformity is 12% of CD = minimum contact hole size Allowed lithography variance = 3/4 total variance Mask image placement metrology (precision, P/T=0.1) Mask CD precision (nm, 3 sigma) isolated lines (MPU gates), binary or attenuated phase shift mask [H] (P/T=0.2 for isolated lines, binary**) Mask CD precision (nm, 3 sigma) dense lines (DRAM half pitch), binary or attenuated phase shift mask [J] Mask contact CD precision(nm)* Uniformity is 12% of CD = minimum contact hole size Allowed lithography variance = 3/4 total variance Specific Requirements Alternated PSM phase mean deviation Phase metrology precision, P/T= Attenuated PSM phase mean deviation from 180º (± degree) [S] Phase uniformity metrology precision, P/T=

18 18 Table 119b Lithography Metrology (Mask) Technology Requirements: Optical Long-term Years Optical Masks not part of potential solutions beyond 22 nm, grey-colored cells indicate the transition Year of Production DRAM ½ Pitch (nm) (contacted) MPU/ASIC Metal 1 (M1) ½ Pitch (nm)(contacted) MPU gate in resist (nm) MPU Physical Gate Length (nm) Flash ½ Pitch (nm) (Un-contacted Poly) DRAM/Flash CD control (3sigma) (nm) CD uniformity (nm, 3 sigma) isolated lines (MPU gates), binary or attenuated phase shift mask [H] Wafer overlay control (nm) DRAM Contact after etch (nm) Wafer contact CD control (nm)* Uniformity is 13.5% of CD = minimum contact hole size Allowed lithography variance = 3/4 total variance Mask nominal image size (nm) [B] Mask minimum primary feature size [D] Minimum OPC size (opaque at 4, nm) [D] Optical Section Image placement (nm, multi-point) [F] CD uniformity allocation to mask (assumption) Mask error factor (MEF) from lithography tables isolated lines, binary MEEF dense lines, binary or attenuated phase shift mask [G] MEF contacts [G] CD Uniformity (3 Sigma at 4, nm) Refer to Lithography Chapter Table for Optical Mask Requirements Mask CD uniformity (nm, 3 sigma) isolated lines (MPU gates), binary or attenuated phase shift mask [H]

19 19 Table 119b Lithography Metrology (Mask) Technology Requirements: Optical Long-term Years (continued) Optical Masks not part of potential solutions beyond 22 nm, grey-colored cells indicate the transition 1. Year of Production DRAM ½ Pitch (nm) (contacted) MPU/ASIC Metal 1 (M1) ½ Pitch (nm)(contacted) MPU gate in resist (nm) Mask CD uniformity (nm, 3 sigma) dense lines (DRAM half pitch), binary or attenuated phase shift mask [J] Mask contact CD control (nm)* Uniformity is 12% of CD = minimum contact hole size Allowed lithography variance = 3/4 total variance Mask image placement metrology (precision, P/T=0.1) Mask CD precision (nm, 3 sigma) isolated lines (MPU gates), binary or attenuated phase shift mask [H] (P/T=0.2 for isolated lines, binary**) Mask CD precision (nm, 3 sigma) dense lines (DRAM half pitch), binary or attenuated phase shift mask [J] Mask contact CD precision(nm)* Uniformity is 12% of CD = minimum contact hole size Allowed lithography variance = 3/4 total variance Specific Requirements Alternated PSM phase mean deviation Phase metrology precision, P/T=0.2 Attenuated PSM phase mean deviation from 180º (± degree) [S] Phase uniformity metrology precision, P/T= Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known

20 20 Table 119c Lithography Metrology (Mask) Technology Requirements: EUV Near-term Years Year of Production DRAM ½ Pitch (nm) (contacted) MPU/ASIC Metal 1 (M1) ½ Pitch (nm)(contacted) MPU Physical Gate Length (nm) Flash ½ Pitch (nm) (Un-contacted Poly) Image placement error (nm, multipoint) CD Uniformity (3 sigma at 4, nm) Isolated lines (MPU gates) Uniformity is 10% of CD Mask error factor varies with year Dense lines (DRAM half-pitch) Uniformity is 15% of CD Mask error factor varies with year DRAM contact after Etch Contact/Vias Uniformity is 10% of CD mask error factor varies with year Mask CD metrology tool precision* (P/T=0.2 for isolated lines)** Mask CD metrology tool precision* (P/T=0.2 for dense lines)** Mask CD metrology tool precision* (P/T=0.2 for contact/vias)** Specific Requirements Mean peak reflectivity 65% 66% 66% 66% 67% 67% Peak reflectivity uniformity (3 sigma %) 0.69% 0.58% 0.47% 0.42% 0.37% 0.33% Absorber sidewall angle tolerance (degrees) Absorber LER (3 sigma, nm) Mask substrate flatness (peak-to-valley, nm) Metrology mean peak reflectivity precision (P/T=0.2, %) Peak reflectivity uniformity metrology precision (3 sigma, P/T = 0.2) Absorber sidewall angle metrology precision (degrees 3 sigma, P/T = 0.2) Absorber LER metrology precision (3 sigma, P/T=0.2) Mask substrate flatness metrology precision (nm 3 sigma, P/T=0.2) 1.30% 1.30% 1.30% 1.30% 1.30% 1.30% 0.14% 0.12% 0.09% 0.08% 0.07% 0.07% nm EUV * precision nm 3 ** Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known

21 21 Table 119 d Lithography Metrology (Mask) Technology Requirements: EUV Long-term Years Year of Production DRAM ½ Pitch (nm) (contacted) MPU/ASIC Metal 1 (M1) ½ Pitch (nm)(contacted) MPU Physical Gate Length (nm) Flash ½ Pitch (nm) (Un-contacted Poly) Image placement error (nm, multipoint) CD Uniformity (3 sigma at 4, nm) Isolated lines (MPU gates) Uniformity is 10% of CD Mask error factor varies with year Dense lines (DRAM half-pitch) Uniformity is 15% of CD Mask error factor varies with year DRAM contact after Etch Contact/Vias Uniformity is 10% of CD mask error factor varies with year Mask CD metrology tool precision* (P/T=0.2 for isolated lines)** Mask CD metrology tool precision* (P/T=0.2 for dense lines)** Mask CD metrology tool precision* (P/T=0.2 for contact/vias)** Specific Requirements Mean peak reflectivity 67% 67% 67% 67% 67% 67% 67% Peak reflectivity uniformity (3 sigma %) 0.29% 0.26% 0.23% 0.21% 0.19% 0.17% 0.15% Absorber sidewall angle tolerance (degrees) Absorber LER (3 sigma, nm) Mask substrate flatness (peak-to-valley, nm) Metrology mean peak reflectivity precision (P/T=0.2, %) Peak reflectivity uniformity metrology precision (3 sigma, P/T = 0.2) Absorber sidewall angle metrology precision (degrees 3 sigma, P/T = 0.2) 1.30% 1.30% 1.30% 1.30% 1.30% 1.30% 1.30% 0.06% 0.05% 0.05% 0.04% 0.04% 0.03% 0.03% Absorber LER metrology precision (3 sigma, P/T=0.2) Mask substrate flatness metrology precision (nm 3 sigma, P/T=0.2) * precision nm 3 ** Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known

22 22 Table 119 a b [A] CD (process range) precision CD 1 25nm CD [B] 4 [C] CD / OPC [D] OPC [E] CD process range CD 3 CD 1/10 4/5 CD 15% 4/5 / CD 15% 2/3 40 MEF CD MEF [F] 65nm [G] 1 [H] 70nm 100nm 2 65nm nm 50nm 3 [I] / 70nm 100nm 3 65nm nm 50nm 4

23 DRAM 1/2 Pitch 65nm 45nm 32nm 22nm 16nm CD-Wafer and Mask Metrology 65 CD-SEM, scatterometry Off-line CD-SPM (e.g. AFM) Off-line destructive dual column FIB DRAM Half-pitch 45 CD-SEM, scatterometry Off-line CD-SPM (e.g. AFM) Off-line destructive dual column FIB Narrow options Technology Options (DRAM Half-Pitch, nm) CD-SEM with improvements (e.g., aberration corrected items) Scatterometry with improvements Off-line CD-SPM (e.g. AFM) Off-line destructive dual column FIB Narrow options CD-SEM with improvements (e.g., aberration corrected lens) Scatterometry with improvements Off-line CD-SPM (e.g., AFM) Off-line destructive dual column FIB Narrow options 16 CD technology capable of measuring nano-materials Narrow options Overlay Metrology DRAM Half-pitch 65 Optical (microscopic) SEM 45 Optical (microscopic) SEM Scatterometry Narrow options Technology Options (DRAM Half-Pitch, nm) 32 Advanced optical (microscopic) SEM Innovative scatterometry Narrow options 22 Innovative Scatterometry & other Narrow options 16 Overlay technology capable of measuring nano-materials Narrow options Research Required Development Underway Qualification/Pre-Production Continuous Improvement This legend indicates the time during which research, development, and qualification/pre-production should be taking place for the solution. Figure 106 Lithography Metrology Potential Solutions FEP Front End Processes Metrology CMOS CMOS 15 IC FEP FINFET SOI CMOS High-k (wrap around)

24 24 FEP FEP Table120 Figure107 Table 120a Front End Processes Metrology Technology Requirements Near-term Years Year of Production DRAM ½ Pitch (nm) (contacted) MPU/ASIC Metal 1 (M1) ½ Pitch (nm)(contacted) MPU Physical Gate Length (nm) Metrology for metal gate thickness and composition* Bulk control limits for trace metals for bulk silicon and SOI top silicon layer. 0.5x x x x x x x x x10 10 (Fe concentration in atoms/cm 3 ) Bulk detection limits for trace metals for bulk silicon and SOI top silicon layer. 0.5x x x x x x x x x10 9 (Fe concentration in atoms/cm 3 ) High-performance EOT (Extended planar bulk) High-performance EOT (FDSOI) High-performance EOT (DG) Low power EOT (bulk) Low power EOT (DG) Low power EOT (FD) ± 3σ dielectric process range (EOT) (nm) ± 4% ± 4% ± 4% ± 4% ± 4% ± 4% ± 4% ± 4% ± 4% EOT measurement precision 3σ (nm) [B] Cylinder Cylinder Pedestal Pedestal Pedestal DRAM stacked capacitor structure including Pedestal Pedestal Pedestal Pedestal /Pedestal /Pedestal MIM/ MIM/ MIM/ electrodes MIM MIM MIM MIM MIM MIM others others others DRAM stacked capacitor electrodes (near term) MIM MIM MIM MIM MIM MIM MIM MIM MIM DRAM stacked capacitor dielectric material ALO/TAO /others ALO/TAO /others ALO/TAO/ others ALO/TAO/ others ALO/TAO/ others ALO/TAO/ DRAM stacked capacitor dielectric constant EOT (nm) for stacked capacitor DRAM stacked capacitor dielectric physical thickness (nm) ± 3 σ process range ± 4% ± 4% ± 4% ± 4% ± 4% ± 4% ± 4% ± 4% ± 4% DRAM capacitor dielectric physical thickness measurement precision (nm 3s) [C] Uniform channel concentration (cm 3 ), for V t =0.4 [W] E E E18 others new material new material new material NA NA NA NA NA NA Dopant atom P, As, B P, As, B P, As, B P, As, B P, As, B P, As, B P, As, B P, As, B P, As, B

25 25 Table 120a Front End Processes Metrology Technology Requirements Near-term Years (continued) Year of Production DRAM ½ Pitch (nm) (contacted) MPU/ASIC Metal 1 (M1) ½ Pitch (nm)(contacted) MPU Physical Gate Length (nm) Metrology for junction depth [based on drain extension] of (nm) Note change to different structure for 2008 Extension lateral abruptness (nm/decade) [M] TBD TBD TBD TBD TBD TBD Lateral/depth spatial resolution for 2D/3D dopant profile (nm) TBD TBD TBD TBD TBD TBD At-line dopant concentration precision (across concentration range) [D] 4% 4% 4% 4% 4% 2% 2% 2% 2% Metal gate work function for bulk MPU/ASIC Ec,v fm (ev) [***] <0.2 <0.2 <0.2 <0.2 <0.2 <0.2 <0.2 Metal gate work function for FDSOI MPU/ASIC fm Ei (ev) NMOS/PMOS [***] ± 0.1 ± 0.1 ± 0.1 ± 0.1 ± 0.1 ± 0.1 Metal gate work function for multi-gate MPU/ASIC [***] midgap midgap midgap Metal gate work function for bulk low operating power Ec,v fm (ev) [***] <0.2 <0.2 <0.2 <0.2 <0.2 <0.2 <0.2 <0.2 Metal gate workfunction for FDSOI LOP [***] midgap midgap midgap Metal gate work function for multi-gate LOP [***] midgap midgap midgap Metal gate work function for bulk LSTP Ec,v fm (ev) [***] <0.2 <0.2 <0.2 <0.2 <0.2 <0.2 Metal gate work function for FDSOI and multi-gate LSTP fm - Ei (ev) NMOS/PMOS [***] Metrology for metal gate thickness and composition* Starting silicon layer thickness (SOI) (fully depleted) (tolerance ± 5%, 3s) (nm) [M] SOI Si thickness precision (3s in nm) Grey cells indicate transition years of technologies. * Cell colors indicate this is an overarching metrology for metal gate thickness and composition that are critical challenges during the long-term years. Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known

26 26 Table 120b Front End Processes Metrology Technology Requirements Long-term Years Year of Production DRAM ½ Pitch (nm) (contacted) MPU/ASIC Metal 1 (M1) ½ Pitch (nm)(contacted) MPU Physical Gate Length (nm) Metrology for metal gate thickness and composition* Bulk control limits for trace metals for bulk silicon and SOI top silicon layer. (Fe concentration in atoms/cm 3 ) Bulk detection limits for trace metals for bulk silicon and SOI top silicon layer. (Fe concentration in atoms/cm 3 ) High-pPerformance EOT (Extended planar bulk) High-performance EOT (FDSOI) x x x x x x x x x x x x x x10 9 High-performance EOT (DG) Low power EOT (bulk) Low power EOT (DG) Low power EOT (FD) ± 3σ dielectric process range (EOT) (nm) ± 4% ± 4% ± 4% ± 4% ± 4% ± 4% ± 4% EOT measurement precision 3σ (nm) [B] DRAM stacked capacitor structure including electrodes DRAM stacked capacitor electrodes (near term) Pedestal MIM Pedestal MIM DRAM stacked capacitor dielectric material new material new material Pedestal MIM Pedestal MIM DRAM stacked capacitor dielectric constant Pedestal MIM EOT (nm) for stacked capacitor DRAM stacked capacitor dielectric physical thickness (nm) Pedestal MIM Pedestal MIM ± 3σ process range ± 4% ± 4% ± 4% ± 4% ± 4% DRAM capacitor dielectric physical thickness measurement precision (nm 3s) [C] Uniform channel concentration (cm 3 ), for V t =0.4 [W] NA NA NA NA NA Dopant atom P, As, B P, As, B P, As, B P, As, B P, As, B Metrology for junction depth [based on drain extension] of (nm) Note change to different structure for Extension lateral abruptness (nm/decade) [M] TBD TBD TBD TBD TBD Lateral/depth spatial resolution for 2D/3D dopant profile (nm) TBD TBD TBD TBD TBD

27 27 Table 120b Front End Processes Metrology Technology Requirements Long-term Years (continued) Year of Production DRAM ½ Pitch (nm) (contacted) MPU/ASIC Metal 1 (M1) ½ Pitch (nm)(contacted) MPU Physical Gate Length (nm) At-line dopant concentration precision (across concentration range) [D] 2% 2% 2% 2% 2% Metal gate work function for bulk MPU/ASIC Ec,v fm (ev) [***] Metal gate work function for FDSOI MPU/ASIC fm Ei (ev) NMOS/PMOS [***] Metal gate work function for multi-gate MPU/ASIC [***] ± 0.1 ± 0.1 midgap midgap midgap midgap midgap midgap midgap Metal gate work function for bulk low operating power Ec,v fm (ev) [***] Metal gate work function for FDSOI LOP [***] midgap midgap midgap midgap midgap midgap midgap Metal gate work function for multi-gate LOP [***] midgap midgap midgap midgap midgap midgap midgap Metal gate work function for bulk LSTP Ec,v - fm (ev) [***] Metal gate work function for FDSOI and multi-gate LSTP fm - Ei (ev) NMOS/PMOS [***] Starting silicon layer thickness (SOI) (fully depleted) (tolerance ± 5%, 3s) (nm) [M] ± 0.1 ± 0.1 ± 0.1 ± 0.1 ± 0.1 ± 0.1 ± SOI Si thickness precision (3s in nm) Grey cells indicate transition years of technologies. * Cell colors indicate this is an overarching metrology for metal gate thickness and composition that are critical challenges during the long-term years. Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known Table 120a 120b [A] SOI [B] P/T=0.1=6x / SiO 2 SiON SiN/ SiO nm SiO 2 Ta2O5 70nm 100nm High-k/ ox EOT 6.4nm Ta 2 O 5 =~2.5 EOT=1nm SiO 2 k=3.9 EOT [C] MIS tdiel tdiel=(teq.ox-1nm)diel High-k/3.9 MIM tdiel tdiel= teq.ox High-k/3.9 teq.ox SiO 2 High-k [D] FEP

28 28 FEP Table120 Figure107 Starting Materials SOI Si p+ SOI Si SOI Si Ni Cu SOI Si cm- 3 Fe SOI <20nm HF <100nm 2-20 <50nm 90nm 90nm 90nm 90 nm FEP Starting Materials SOI Silicon-On-Insulator SOI IC SOI SOI SOI SOI FEP Starting Materials 2001 SOI Si Si (Materials Characterization) Surface Preparation in-situ " " " / " High-k / Thermal/Thin Films SiON High-k High-k FEP 2005 High-k / High-k " / " High-k STEM X SiGe Ge " / "

29 29 NMOS Si 3 N 4 PMOS SiGe STI PMOS STI Si 3 N 4 NMOS FINFETS wrap around FERAM nm nm 4 Thermally Modulated Optical Reflectance B P As B P As X In-line Electron Microprobe System SIMS Secondary Ion Mass Spectroscopy 2 3 TCAD technology computer-aided design Carrier Illumination

30 DRAM 1/2 Pitch 65nm 45nm 32nm 22nm 16nm 65 Dielectric Ellipsometry X-ray reflectivity Non-contact electrical Technology Options (DRAM Half-Pitch, nm) 45 32/22 Dielectric Ellipsometry X-ray reflectivity Non-contact electrical (Corona discharge methods) XPS (x-ray photoelectron spectroscopy Metal gate X-ray reflectivity and ellipsometry Narrow options Dielectric (requires considerable improvement) Ellipsometry possible sidewall measurement X-ray reflectivity Non-contact electrical (Corona discharge methods) XPS (x-ray photoelectron spectroscopy) Metal gate possible sidewall measurement X-ray reflectivity and ellipsometry Narrow options 16 Dielectric Modified methods for sidewall measurements Metal gate Modified methods for sidewall measurement s Narrow options Research Required Development Underway Qualification/Pre-Production Continuous Improvement This legend indicates the time during which research, development, and qualification/pre-production should be taking place for the solution. Figure 107 FEP Metrology Potential Solutions Interconnect Metrology IC /SiO 2 Cu/Low-k / / /SiO 2 Cu-Low- Cu-Low- Cu

31 31 Cu-Low-k Cu Cu-Low-k Cu Cu Cu Cu /CMP/ Cu Cu Cu 90nm Cu 90nm Cu 2 Cu Cu Cu Cu Cu in-situ Potential Solution CVS

32 32 Cu 5nm ITRS % 6nm (6 ) 0.12nm SPC Cu X X X Cu CMP Cu Cu Cu Cu Cu/ ( ) CMP Cu CMP in-situ Low-k ( ) X Cu Cu CMP Cu Low-k CD

33 33 CD / 3 CD CD Table121 Figure108 Cu Low-k Table121

34 34 Table 121a Interconnect Metrology Technology Requirements Near-term Years Year of Production DRAM ½ Pitch (nm) (contacted) MPU/ASIC Metal 1 (M1) ½ Pitch (nm)(contacted) MPU Physical Gate Length (nm) Metrology for maintaining planarity requirements: lithography field (mm mm) for minimum interconnect CD (nm) [A] Measurement of deposited barrier layer at thickness (nm) Process range (± 3σ ) 10% 10% 10% 10% 10% 10% 10% 10% 10% Precision σs (nm) for P/T=0.1 [B] Metrology capability to measure Cu thinning at minimum pitch due to erosion (nm), 10% height, 50% areal density, 500 µm square array Detection of post deposition and anneal process voids at or exceeding listed size (nm) when these voids constitute 1% or more of total metal level conductor volume of copper lines and vias Detection of killer pore in ILD at (nm) size Measure interlevel metal insulator bulk/effective dielectric constant (κ) and anisotropy on patterned structures [C] Table 121b Interconnect Metrology Technology Requirements Long-term Years Year of Production DRAM ½ Pitch (nm) (contacted) MPU/ASIC Metal 1 (M1) ½ Pitch (nm)(contacted) MPU Physical Gate Length (nm) Metrology for maintaining planarity requirements: lithography field (mm mm) for minimum interconnect CD (nm) [A] Measurement of deposited barrier layer at thickness (nm) Process range (± 3σ) 10% 10% 10% 10% 10% 10% 10% Precision σs (nm) for P/T=0.1 [B] Metrology capability to measure Cu thinning at minimum pitch due to erosion (nm), 10% height, 50% areal density, 500 µm square array Detection of post deposition and anneal process voids at or exceeding listed size (nm) when these voids constitute 1% or more of total metal level conductor volume of copper lines and vias Detection of killer pore in ILD at (nm) size Measure interlevel metal insulator bulk/effective dielectric constant (κ) and anisotropy on patterned structures [C] Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known

35 35 Low-k Low-k SiO 2 Cu Low-k SiO 2 2 Low-k 2 Low-k Low-k CMP CMP in-situ Low-k X SAXS SAXS Low-k Low-k 40GHz 20GHz 40GH 100GH Low-k 1 GHz 10 GHz CMP Low-k Low-k CD / CD-SEM CD

36 36 M1 CD Low-k R-C DRAM 1/2 Pitch 65nm 45nm 32nm 22nm 16nm 65 Low k stack Optical and x-ray reflectivity Metal barrier / seed copper X-ray reflectivity, x-ray fluorescence, acoustic, and 4pt probe Technology Options (DRAM Half-Pitch, nm) Low k stack Optical and x-ray reflectivity Metal barrier / seed copper X-ray reflectivity, x-ray fluorescence, acoustic, and 4pt probe Low k stack Porous low k control Metal barrier / seed copper 3D Interconnect Metrology Narrow options Narrow options 22 Metrology development to meet needs of unknown Interconnect technology Narrow options 16 Metrology development to meet needs of unknown Interconnect technology Narrow options Research Required Development Underway Qualification/Pre-Production Continuous Improvement This legend indicates the time during which research, development, and qualification/pre-production should be taking place for the solution. Figure 108 Interconnect Metrology Potential Solutions X TEM STEM TEM STEM ADF-STEM; Annular Dark Field STEM

37 37 TEM STEM ADF-STEM X SIMS TOF; Time Of Flight SIMS X XRR X XRR X-Ray Reflectivity TEM/STEM SIMS FE-AES; Field Emission Auger Electron Spectroscopy 20nm Low-k 300mm TEM STEM High-k Low-k STEM ADF EELS; Electron energy Loss Spectroscopy 0.2nm ELS High-k ADF EELS STEM TEM STEM STEM EDS; energy-dispersive spectroscopy X EDS EDS SEM 50nm High-k Cu

38 /cm 3 Cu 10 8 /cm 3 ICP-MS SOI Silicon On Insulator 2003 Si Si SOI Si Si SiGe SOI SiGe 1 SiGe Ge 2 Si 3 Si/SiGe Si 4 Si 5 Si cm -2 6 SiGe/Si 7 TEM TEM TEM AFM Si EPD EPD EPD EPD X Ge SIMS SiGe Si / SIMS SOI Si Si Si Si-Si Si-Si Si Si Si 325nm Si SiGe Si-Si SiGe Si-Si SiGe Si

39 µm 5 10 Si Si Si Si Si 1 Si Si Si SiGe Ge Ge Si Si/SiGe X Si X nm Si Si TEM X X X High k Si Si Si SiGe SR X Microscopy

40 DRAM 1/2 Pitch 65nm 45nm 32nm 22nm 16nm PRODUCT WAFER ANALYSIS / REVIEW Improved imaging for SEM, auger, and dule, column FIB defect review ATOMIC LEVEL CHARACTERIZATION AND INTERFACE ANALYSIS Advanced TEM / STEM imaging / ELS Field emission atomic mapping Gi-XRR for interface analysis Innovative methods Dopant profiling Scanned probe methods Field emission atomic mapping Innovative methods Centralized facilities for TXRF / ion beam methods Research Required Development Underway Qualification/Pre-Production Continuous Improvement This legend indicates the time during which research, development, and qualification/pre-production should be taking place for the solution. Figure 109 Materials and Contamination Potential Solutions (RMS; Reference Measurement System) RMS RMS FAB RMS RMS FAB RMS FAB ( golden ) FAB FAB in-house

41 41 / / / / / / certified reference material, CRM / consensus reference material NIST / NTRM / standard reference material, SRM 2 ISO VIM RM CRM RM " " CRM " " NIST NIST RM ISO RM CRM NIST SRM ISO CRM NIST / SRM NIST NIST / NIST NTRM / NIST NIST NTRM 3 ASTM / NMI NIST NMI 4 (Mutual Recognition) (Key Comparison) NMI NTRM SRM NIST 3 NTRM NIST 4 BIPM

42 42 / / / / / / / / / / / 1/4 / 1/4 / " / " / APC APC advanced process control in-situ APC R2R run-to-run FDC fault detection and classification APC 1 APC 2 APC APC CMP 3 APC APC APC 2 1 R2R wafer-to-wafer batch-to-batch in-situ 2 FDC FDC in-situ

43 43 R2R FDC 2 APC R2R FDC R2R In-situ R2R R2R FDC EEC Equipment Engineering Capability APC APC APC R2R FDC in-situ R2R FDC R2R FDC R2R FDC 1 2 APC APC 3 R2R FDC FDC R2R 4 FDC R2R 1 3 APC APC APC R2R CD CMP CD CD 100

44 in-situ in-situ APC in-situ APC R2R APC in-situ R2R In-situ in-situ In-situ in-situ In-situ ALD Atomic Layer Deposition ALD Low-k in-situ in-situ High-k CMP Low-k APC APC

45 45 3 TEM ELS STEM TEM STEM TEM STEM 0.1nm STEM 3 TEM High-k ELS ELS ELS LEAP Local Electrode Atom Probe LEAP 2 LEAP 3 60% CMOS CMOS Opportunities SPM Scanning Probe Microscopy nm

46 46 2 SPM 8 SSPM Scanning Surface Potential Microscopy 10nm High-k SPM Multiple Modulation Challenges General Accessibility High-k CMOS 6

47 47 SPM SSPM SPM 30 / Critical Point Jellison (Joint Density of State) Jellison E 0 3.4eV E eV( 292nm) nm, CMOS

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