2.5. Verilog 19 Z= X + Y - Z A+B LD ADD SUB ST (X<<1)+(Y<<1) X 1 2 LD SL ST 2 10

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1 2.5. Verilog 19 Z= X + Y - Z A+B LD ADD SUB ST (X<<1)+(Y<<1) X 1 2 LD SL ST LD SL ADD ST Y LD 0,1,2 A,B,C (A-B) OR (B+C) Verilog Verilog Verilog

2 20 2 module ( input 1, input 2, output 1, output 2 ); C (;) a, b s 1bit /* 1 bit adder */ module adder ( input a, b, output s ); assign s = a + b ; // add a b endmodule C (/* */ //) Verilog VHDL + CAD(Computer Aided Design) s=a+b; assign assign s s endmodule ; adder.v C.c Verilog-HDL.v 1 Verilog test.v Verilog Verilog

3 2.5. Verilog 21 CAD /* test bench */ timescale 1ns/1ps module test; parameter STEP = 10; reg ina, inb; wire outs; adder adder_1(.a(ina),.b(inb),.s(outs)); initial begin $dumpfile("adder.vcd"); $dumpvars(0,adder_1); ina <= 1 b0; inb <= 1 b0; $display("a:%b b:%b s:%b", ina, inb, outs); ina <= 1 b0; inb <= 1 b1; $display("a:%b b:%b s:%b", ina, inb, outs); ina <= 1 b1; inb <= 1 b0; $display("a:%b b:%b s:%b", ina, inb, outs); ina <= 1 b1; inb <= 1 b1; $display("a:%b b:%b s:%b", ina, inb, outs); ina <= 1 b0; inb <= 1 b0; $finish; end

4 22 2 endmodule timescale 1ns/1ps 1ns( =10 9 ) 1ps( =10 12 ) parameter STEP = 10; 10nsec 1 (reg) (wire) reg ina, inb; wire outs; adder adder.v ( adder 1). () adder a ina b inb s outs adder adder_1(.a(ina),.b(inb),.s(outs)); initial initial begin end $dumpfile("adder.vcd"); $dumpvars(0,adder_1); V erilog ( ) dumpfile dumpvars (adder.vcd)

5 2.5. Verilog 23 ina <= 1 b0; inb <= 1 b0; $display("a:%b b:%b s:%b", ina, inb, outs); ina <= 1 b0; inb <= 1 b1; $display("a:%b b:%b s:%b", ina, inb, outs); ina <= 1 b1; inb <= 1 b0; $display("a:%b b:%b s:%b", ina, inb, outs); ina <= 1 b1; inb <= 1 b1; $display("a:%b b:%b s:%b", ina, inb, outs); ina <= 1 b0; inb <= 1 b0; $finish; ina, inb <= 0,1 10nsec ina <= 1 b0; inb <= 1 b0; $display("a:%b b:%b s:%b", ina, inb, outs); ina, inb 0 10nsec ina, inb, outs Verilog < > < >< > b 2 h 16 o : 8

6 b0 1bit 0 1 b1 1bit 1 $display("a:%b b:%b s:%b", ina, inb, outs); display ina,inb,outs display C printf 2 %b 10nsec finish ikarus verilog iverilog test.v adder.v vvp a.out a b a.out iverilog test.v adder.v -o adder vvp adder a:0 b:0 s:0 a:0 b:1 s:1 a:1 b:0 s:1 a:1 b:1 s:0 gtkwave adder.vcd

7 2.5. Verilog : gtkwave SST test adder 1 Signals Append Waves gtkwave Waves Zoom - gtkwave GUI File Quit Yes 1 adder AND OR ( ) ALU ALU 1 (Bus) Verilog MSB:LSB LSB ALU module alu ( input [15:0] a, b,

8 26 2 input [2:0] com, output [15:0] y ); ALU Verilog assign =? 1 2; 1 2 case assign = 1? 1 : 2? 2 : 3? 3 : 4; ALU com 000 A 001 B 010 A AND B AND 011 A OR B OR 100 A 1 SL 101 A 1 SR 110 A+B ADD 111 A-B SUB Verilog assign y = com==3 b000? a: com==3 b001? b: com==3 b010? a & b: com==3 b011? a b: com==3 b100? a<<1: com==3 b101? a>>1: com==3 b110? a + b: a - b ; Verilog 2.1 AND, OR, AND, OR 16 16

9 2.5. Verilog : Verilog NOT & AND & NAND OR NOR ˆ Ex-OR ˆ Ex-NOR << >> ==! = === (x,z )! == (x,z ) < <= > >= + / %! && C 1 == b define ALU 3 b000 15:0 (

10 : ˆ!& + - ( ) / % + - <<>><<<>>> <<=>>= ==! ====! == & & ˆ && ) Verilog C define C define ( ) define DATA_W 16 // bit width define SEL_W 3 //control width define ALU_THA SEL_W b000 define ALU_THB SEL_W b001 define ALU_AND SEL_W b010 module alu ( input [ DATA_W-1:0] a, b, input [ SEL_W-1:0] s, output [ DATA_W-1:0] y ); assign y = s== ALU_THA? a: s== ALU_THB? b: s== ALU_AND? a & b: a + b ; endmodule 2 define parameter

11 2.5. Verilog 29 web ALU test.v ALU /* test bench */ timescale 1ns/1ps define DATA_W 16 // bit width define SEL_W 3 //control width define ALU_THA SEL_W b000 define ALU_THB SEL_W b001 define ALU_AND SEL_W b010 define ALU_ADD SEL_W b110 module test; parameter STEP = 10; reg [ DATA_W-1:0] ina, inb; reg [ SEL_W-1:0] sel; wire [ DATA_W-1:0] outs; alu alu_1(.a(ina),.b(inb),.s(sel),.y(outs)); initial begin $dumpfile("alu.vcd"); $dumpvars(0,alu_1); ina <= DATA_W h1111; inb <= DATA_W h2222; sel <= ALU_THA; $display("a:%h b:%h s:%h y:%h", ina, inb, sel, outs); sel <= ALU_THB; $display("a:%h b:%h s:%h y:%h", ina, inb, sel, outs); sel <= ALU_AND; $display("a:%h b:%h s:%h y:%h", ina, inb, sel, outs); sel <= ALU_ADD;

12 30 2 $display("a:%h b:%h s:%h y:%h", ina, inb, sel, outs); $finish; end endmodule 16bit a,b com 16 C 0x h a <= 16 h1111; b <= 16 h2222; com <= 3 b000 display 16 %x %h iverilog test.v alu.v vvp a.out a b a:1111 b:2222 com:0 y:1111 a:1111 b:2222 com:1 y:2222 a:1111 b:2222 com:6 y:3333 AND,OR, ALU Verilog reg [15:0] acum;

13 2.5. Verilog alu y Verilog wire wire [15:0] alu_y; alu y ALU ALU reg [ DATA_W-1:0] accum; wire [ DATA_W-1:0] alu_y; ALU define 1 def.h include def.h C include ( ) def.h define DATA_W 16 define SEL_W 3 define ADDR_W 8 define DEPTH 256 define ALU_THA SEL_W b000 define ALU_THB SEL_W b001 define ALU_AND SEL_W b010 define ALU_ADD SEL_W b110 define ALU_SUB SEL_W b111 define ENABLE 1 b1 define DISABLE 1 b0 define ENABLE_N 1 b0 define DISABLE_N 1 b1 include "def.h" module datapath( input clk, input rst_n, input [ DATA_W-1:0] datain, input [ SEL_W-1:0] com,

14 32 2 output [ DATA_W-1:0] accout); reg [ DATA_W-1:0] accum; wire [ DATA_W-1:0] alu_y; assign accout = accum; alu alu_1(.a(accum),.b(datain),.s(com),.y(alu_y)); clk or negedge rst_n) begin if(!rst_n) accum <= DATA_W b0; else accum <= alu_y; end endmodule assign assign accout = accum; accum dataout accum dataout ALU alu alu_1(.a(accum),.b(datain),.com(com),.y(alu_y)); alu alu 1 ( ) Verilog.( ) ALU a accum b datain com com y alu y com module alu module datapath clk) accum <= alu_y; accum ALU alu y Verilog

15 2.5. Verilog 33 3GHz CPU CPU 2 clk) (posedge clk)= L H ( positive edge) clk negedge negative edge accum <= alu_y; <= begin end reg reg [15:0] dmem [0:15]; : dmem reg [15:0] dmem [0:1023]; 1024=1K daddr dmem [daddr]; 2

16 34 2 always we(write enable) we=1 clk) if(we) dmem[daddr] <= ddataout; if C Verilog always if /* test bench */ timescale 1ns/1ps include "def.h" module test; parameter STEP = 10; reg clk, rst_n; reg [ DATA_W-1:0] datain; reg [ SEL_W-1:0] com; reg [ ADDR_W-1:0] addr; reg we; wire [ DATA_W-1:0] accout; wire [ DATA_W-1:0] dmem2; reg [ DATA_W-1:0] dmem [ DEPTH-1:0]; clk) begin if(we) dmem[addr] <= accout; end always #(STEP/2) begin clk <= ~clk; end datapath datapath_1(.clk(clk),.rst_n(rst_n),.com(com),.datain(dmem[addr]),.accout(accout)); initial begin $dumpfile("datapath.vcd"); $dumpvars(0,test); $readmemh("dmem.dat", dmem);

17 2.5. Verilog 35 clk <= DISABLE; rst_n <= ENABLE_N; {we,com,addr} <= { DISABLE, ALU_THB, ADDR_W h00}; // LD 0 #(STEP*1/4) rst_n <= DISABLE_N; $display("we:%b com:%h addr:%h accout:%h", we, com, addr, accout); $display("dmem[0]:%h dmem[1]:%h dmem[2]:%h", dmem[0], dmem[1], dmem[2]); #(STEP*1/2) {we,com,addr} <= { DISABLE, ALU_ADD, ADDR_W h01}; // ADD 1 #(STEP*1/2) $display("we:%b com:%h addr:%h accout:%h", we, com, addr, accout); $display("dmem[0]:%h dmem[1]:%h dmem[2]:%h", dmem[0], dmem[1], dmem[2]); #(STEP*1/2) {we,com,addr} <= { DISABLE, ALU_ADD, ADDR_W h02}; // ADD 2 #(STEP*1/2) $display("we:%b com:%h addr:%h accout:%h", we, com, addr, accout); $display("dmem[0]:%h dmem[1]:%h dmem[2]:%h", dmem[0], dmem[1], dmem[2]); #(STEP*1/2) {we,com,addr} <= { ENABLE, ALU_THA, ADDR_W h02}; // ST 2 #(STEP*1/2) $display("we:%b com:%h addr:%h accout:%h", we, com, addr, accout); $display("dmem[0]:%h dmem[1]:%h dmem[2]:%h", dmem[0], dmem[1], dmem[2]); #(STEP*1/2) {we,com,addr} <= { DISABLE, ALU_THA, ADDR_W h02}; // NOP #(STEP*1/2) $display("we:%b com:%h addr:%h accout:%h", we, com, addr, accout); $display("dmem[0]:%h dmem[1]:%h dmem[2]:%h", dmem[0], dmem[1], dmem[2]); $finish; end endmodule clk L,H,L,H always #(STEP/2) begin clk <= ~clk; end

18 36 2 STEP STEP clk reg initial $readmemh("dmem.dat", dmem); dmem dmem.dat 16 (readmemh ) dmem.dat readmemb dmem.dat {we,com,addr} <= { DISABLE, ALU_THB, ADDR_W h00}; Verilog we,com.addr we=0, com=001, addr=0000 LD 0, ADD 1, ADD 2, ST =9 dmem[2] display 0-2 STEP*1/4 iverilog test.v datapath.v alu.v vvp a.out

19 2.5. Verilog 37 A 0 B 1 A << 1 OR B << 1 2 A 0 B 1 C 2 (A+B) OR (A-B) 3 ST accum

ディジタル回路　第1回ガイダンス、CMOSの基本回路

ディジタル回路　第1回ガイダンス、CMOSの基本回路 POCO の 1 サイクルマイクロアーキテクチャ POCO は作りながら学ぶコンピュータアーキテクチャ ( 倍風館 ) で使っている教育用の 16 ビット RISC である www.am.ics.keio.ac.jp/parthenon/pocobook/ も参照のこと POCO の構成 1 + + ext func[2:0] 2:0 THB ADD 00 01 10 comsel com S A