1 osana@eee.u-ryukyu.ac.jp

: FPGA : HDL, Xilinx Vivado + Digilent Nexys4 (Artix-7 100T)

LSI / PC clock accurate /

Artix-7 XC7A100T Kintex-7 XC7K325T

: CAD Hands-on: HDL (Verilog) CAD (Vivado HLx)

: 28y4 : b6uy

LSI: / OP

LSI ( ) 1.5 2 : (Moore s law) :

EUV ( )

LSI 100 75 Yield Ramp-up Mask Cost Design Cost 13 12 Million USD 50 12 9 75 25 0 10 3 9 40 1 0.1 6 21 0.1 5 10 14 5 180 130 90 65 45 32 Process (nm) IC design costs at different process nodes Ilkka Tuomi, The Future of Semiconductor Intellectual Property Architectural Blocks in Europe, JRC European Commission, 2009

FPGA FPGA OK

Worldwide Wafer Capacity (8 eq, Million) 140 105 70 35 125mm 150mm 200mm 300mm 450mm 0 1975 1985 1995 2005 2015 2025 450 mm Era: A New Opportunity for the Semiconductor Industry (4/25/2013) Future Fab Intl. Issue 45

: CPU/GPU 90 67.5 29.66 27.57 20.97 13.72 Nintendo 3DS Nintendo DS Nintendo Wii U Nintendo Wii Xbox360 Sony Playstation Vita Sony PSP Sony Playstation 3 XBox360: IBM PowerPC (90, 65nm) Playstation 3: Cell BE (90, 65, 45nm) ARM / MIPS SoC LSI Million Units 45 22.5 0 24.19 10.91 14.05 10.2 21.3 10.16 9.86 13 17.68 13.53 9.61 14.18 8.86 11.83 14.07 7.71 15.09 14.91 3.05 2.37 5.36 11.33 3.77 4.5 12.98 14.74 0.82 3.09 2.06 6.11 3.12 3.08 8.94 '08 '09 '10 '11 '12 '13 Annual Game Console Sales http://www.statista.com/statistics/276768/global-unit-sales-of-video-game-consoles/

PC 400 Notebook & Netbook Desktop 300 PC CPU LSI Million Units 200 168.7 201.2 209.1 202 199 199 201 204 Intel fab 14nm (Broadwell / Skylake) 100 136.2 145.9 154.8 148.4 145.4 142.5 139 135.5 0 '09 '10 '11 '12 '13 '14 '15 '16 Annual PC Shipments Source: IDC Press Release & Trefis Estimate (2013)

MPU (CPU) Sales Intel Samsung / Apple Freescale MediaTek Spreadtrum Qualcomm AMD TI Nvidia Broadcom 60000! Million USD 45000 30000 345 265 356 375 398 295 591 764 325 415 485 280 510 1,070 565 1,247 1,210 2,831 3,605 4,552 4,249 4,850 2,614 4,152 5,322 6,884 15000 37,435 36,892 36,325 0 '11 '12 '13 Leading MPU Suppliers Source: IC Insights

One-time programmable in-system program

IC 74 IC TC74HC00/04

Glue Logic LSI IC

Programmable? RAM ROM UVEPROM EEPROM ( ) ( )!

Floating gate MOS-FET MOS-FET Source Drain EEPROM MOS-FET Source Drain EEPROM

PROM AND Programmable ROM (AND ) Input OR Output OR * AND/OR PLD

PAL, PLA: Programmable Array Logic PROM AND + OR PAL: AND + OR PLA: AND + OR 22V10 12 10

GAL: Generic Array Logic PAL, PLA FF CLK Q Q GAL CLK Q Q (GAL22V10 )

CMOS LSI: ( ) http://en.wikipedia.org/wiki/cmos

SRAM: EEPROM: MOS-FET Antifuse:

A B C Y A B C Y (LUT: look-up table) A B C LUT Y 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 A 0 0 B 1 0 Y 1 0 1 0 1 0 C 0

CPLD FPGA Coarse-grain

CPLD: Complex PLD Product term PLD block PAL, GAL PAL, GAL EPROM PLD Block Switch Matrix

Gate array ULA: uncommitted logic array LSI

FPGA: Field Programmable Gate Array LUT 4-LUT Island-style

PLD FPGA

NEC DRP (Renesas STP Engine) Mem Mem Mem Mem Mem PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE Mem Control in Mem Mem PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE State Transition Controller PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE Mem Mem 8bit x 2 data in 8bit DMU 8bit ALU 8bit data out Mem PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE Mem Mem Mem Mem Mem Control out

Sea-of-gate CPLD

LSI PROM, PLD, FPGA

Web http://mux.eee.u-ryukyu.ac.jp/lecture.html.ja

FPGA Digilent Nexys 4 FPGA board (!) CAD: Vivado HLx Design Suite 2017.2 (Webpack edition)

CAD: Vivado HLx Design Suite (1) RHEL, SUSE, Cent OS 6.8, Ubuntu 16.04 or Windows 7, 8.1, 10.1 64bit required http://japan.xilinx.com/support/download/

CAD: Vivado HLx Design Suite (2) WebPACK Design Edition System Edition IP SDK I/O IP System Generator for DSP

CAD: Vivado HLx Design Suite (3) Webpack: ( ) Design Edition: ($2,995-,1 year subscription) System Edition: ($4,795-, 1 year subscription) System Edition ( WebPack )

CAD: Vivado HLx Design Suite (4) Webpack OK

Vivado Xilinx University Program Nexys4 ( ) XUP