VHDL VHDL VHDL i

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1

2 VHDL VHDL VHDL i

3 ii

4 1 VHDL IC VHDL IC 4 5 1

5 2 2-1 sequential circuit 2.1 [1] t t t 2

6 state transition diagram state transition table a s1 s b a 2.2 3

7 2-2 flip-flop FF a 2 NOT N1 N2 N1 Q1 H N2 Q1 H Q2 L N1 L Q1 H Q1 Q1 H Q2 L Q1 L Q1 L Q2 H 2.3 a b R S Q [5] 4

8 2.3 2 SR SR set reset flip-flop SR-FF S R 2.4 S 1 Q 1 R 0 Q 1 Q 1 FF Q 0 S R 1 S R 0 Q 1 Q 2.4 FF SR SR-FF 2.5 a Q 2.5 b 2.5 c 5

9 Q Q FF 2.5 d 2.5 SR 6

10 D D delayed flip-flop D-FF D CL CL D CL CL a D-FF b c d CL FF 2.6 c SR-FF R Q D 7

11 2.6 D SR JK T SR S/R 0 Q S/R 1 0 / 1 S/R Q 1 / SR-FF [2] 8

12 Q Q t+1 Q Q t Q Q S S R SR 2.8 [2] 2.8 9

13 JK SR J/K J/K 0 SR J/K 1 Q SR D 2.9 JK-FF [2] Q Q J 2.9 JK T JK J K T T 0 Q T 1 Q toggle 2.10 T [2] 10

14 Q Q T T Q 2.10 T latch register read write 2.11 D 11

15 1 1 D-FF 2.12 D-FF 4 [1] Counter count 1 count up 1 count down

16 ripple carry [2] [2] 13

17 2-5 decode 2 decoder [2] encode encoder [2] D1 D 2 1 D 0 D 3 0 Q 11 D3 14

18 priority D0 D3 D 1 D 2 1 Q 10 D

19 / ON 1 6 [6] 16

20 LED LED 6 LED 1 6 LED 3.1 LED LED LED 3.2 LED LED LED LED [6] 3.2 LED 17

21 LED 1 6 LED 7 LED LED 1 6 LED LED 7 LED a g 7 LED LED b LED [6] 18

22 3.4 LED H 4 OR b f 1 OR a g 4 OR d 3 OR OR NAND OR NAND 3.5 OR NAND 19

23 3.5 OR NAND OR NAND OR NAND NAND 74HC20 3 NAND 74HC10 NAND LED LED 6 LED OFF NAND 0 3V 47k 1 NAND [6] 20

24 3.6 OR NAND [6] 21

25 3.7 [6] H 22

26 LED

27 [6] CR CR CR CR 3.10 CR 4 74HC14 2 1M,100k F 45Hz 3.10 CR TTL D 74HC

28 D n= [6] [6] 25

29 LED LED LED 7 2 LED LED LED LED a g X Y Z LED X 0 Y 0 Z 0 1 X 1 Y 0 Z [6]

30 3.13 X Y Z 3 a b c d e f g 7 X Y Z bit 7bit 3-13 a b c d e f g LED 1 LED 0 LED LED LED 1 LED 3.12 [6] 3.12 LED [6] 27

31 X Y Z [6] 28

32 Z OR a g a g b f c e a g b AND OR IC NAND NOR NAND 74HC c D [6] 29

33 3.16 LED LED IC 74HC04 IC H ON L 5V LED IC 470 LED 6mA [6] ON OFF CR 3.17 ON 4.7 F 0 5V 100k L H NAND OFF 4.7 F 100k 5V 30

34 ON OFF LED ON LED OFF L NAND [6] 3.17 CR ON OFF 31

35

36 3.19 CR

37 ON,OFF LED LED 34

38 4 4-1 VHDL HDL HDL ASIC HDL ASIC FPGA PLD HDL VHDL VHSIC HDL Verilog-HDL UDL I Unified Design Language for Integrated Circuit SFL Structured Function description Language 4.1 VHDL [7] 4.1 HDL 35

39 VHDL VHDL HSIC Very High Speed Integrated Circuit 1981 IC ASIC 3 4 ASIC HDL ASIC 1983 VHDL 1985 VHDL ASIC VHDL 1986 IEEE VASG VHDL Analysis & Standardization Group LRM Language Reference Manual 12 IEEE Std IEEE VHDL HDL 1989 VHDL VHDL EDA [7] 36

40 4-2 VHDL VHDL 3 RTL Behaviar ASIC FPGA ASIC

41 RTL library ieee; use ieee.std_logic_1164.all; entity DFFR is port( CLK,RESET1,D : in std_logic; Q,QN :out std_logic ); end DFFR; architecture RTL of DFFR is signal Q_IN:std_logic; begin QN <= not Q_IN; Q <= Q_IN; process(clk,reset1)begin if(reset1='1')then Q_IN <= '0'; elsif(clk'event and CLK = '1')then Q_IN <= D; end if; end process; end RTL; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; 38

42 entity COUNTER is port( CLK,RESET : in std_logic; COUNT : out std_logic_vector(2 downto 0) ); end COUNTER; architecture RTL of COUNTER is component DFFR port(clk,reset1,d : in std_logic; Q,QN : out std_logic); end component; signal COUNT_IN_BAR : std_logic_vector(3 downto 0); signal COUNT_IN : std_logic_vector(2 downto 0); signal RESET_IN : std_logic; begin COUNT <= COUNT_IN; COUNT_IN_BAR(0) <= CLK; GEN1:for I in 0 to 2 generate U:DFFR port map( CLK => COUNT_IN_BAR(I), RESET1 => RESET_IN, D => COUNT_IN_BAR(I+1), Q => COUNT_IN(I), QN => COUNT_IN_BAR(I+1) ); end generate; 39

43 RESET_IN <= RESET or (COUNT_IN(1) and COUNT_IN(2)); end RTL; 4.2 library ieee; use ieee.std_logic_1164.all; use work.std.textio.all; use work.dffr; entity TESTBNCH is end TESTBNCH; architecture stimulus of TESTBNCH is component COUNTER is port ( ); CLK : in std_logic; RESET : in std_logic; COUNT : out std_logic_vector(2 downto 0) end component; signal CLK : std_logic; signal RESET : std_logic; signal COUNT : std_logic_vector(2 downto 0); begin DUT : COUNTER port map ( ); CLK, RESET, COUNT 40

44 CLOCK1:process begin CLK <= '1'; wait for 10 ns; CLK <= '0'; wait for 10 ns; end process CLOCK1; STIMULUS1 : process begin RESET <= '0'; wait for 5 ns; RESET <= '1'; wait for 10 ns; RESET <= '0'; wait for 180 ns; RESET <= '1'; wait for 20 ns; RESET <= '0'; wait; end process STIMULUS1; end stimulus; CLK COUNT

45 LED LED COUNT A B C 3 7 START EN START EN 1,0 START EN 1, library ieee; use ieee.std_logic_1164.all; entity DECODER3TO7 is port ( A,B,C : in std_logic; START,EN : in std_logic; Y : out std_logic_vector(6 downto 0) ); end DECODER3TO7; architecture RTL of DECODER3TO7 is 42

46 signal INDATA : std_logic_vector(2 downto 0); begin INDATA <= C & B & A; process(indata,start,en)begin if(start = '1' and EN = '0')then --EN = STOP case INDATA is when "000" => Y <= " "; --1 when "001" => Y <= " "; --2 when "010" => Y <= " "; --3 when "011" => Y <= " "; --4 when "100" => Y <= " "; --5 when "101" => Y <= " "; --6 when others => Y <= "XXXXXXX"; --X end case; else null; --Y <= " "; end if; end process; end RTL; 43

47 library ieee; use ieee.std_logic_1164.all; use std.textio.all; use work.decoder3to7; entity TESTBNCH is end TESTBNCH; architecture stimulus of TESTBNCH is component DECODER3TO7 is port ( A,B,C : in std_logic; START,EN : in std_logic; Y: out std_logic_vector(6 downto 0) ); end component; constant PERIOD: time := 100 ns; signal A,B,C : std_logic; signal START,EN : std_logic; signal Y: std_logic_vector(6 downto 0); signal done: boolean := false; begin DUT: DECODER3TO7 port map ( A,B,C, START,EN, Y ); STIMULUS1 : process begin 44

48 START <= '0';wait for 50 ns; START <= '1'; wait; end process STIMULUS1; STIMULUS2 : process begin EN <= '0'; wait for 245 ns; EN <= '1'; wait for 55 ns; EN <= '0'; wait for 333 ns; EN <= '1'; wait for 55 ns; EN <= '0'; wait for 300 ns; EN <= '1'; wait for 55 ns; end process STIMULUS2; STIMULUS3 : process begin A <= '0'; wait for 25 ns; A <= '1'; wait for 25 ns; end process STIMULUS3; STIMULUS4 : process begin B <= '0'; wait for 50 ns; B <= '1'; wait for 50 ns; B <= '0'; wait for 50 ns; 45

49 end process STIMULUS4; STIMULUS5 : process begin C <= '0'; wait for 100 ns; C <= '1'; wait for 50 ns; end process STIMULUS5; end stimulus; CLK COUNT 3 START EN 1,0 COUNT A B C Y 7 46

50 START EN 1,1 START EN 1,0 DICE VHDL library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; 4.5 entity DICE is port( CLK,RESET : in std_logic; Y : out std_logic_vector(6 downto 0); --COUNT : out std_logic_vector(2 downto 0); START,EN : in std_logic ); end DICE; architecture RTL of DICE is component COUNTER port ( CLK,RESET : in std_logic; COUNT : out std_logic_vector(2 downto 0) ); end component; 47

51 component DECODER3to7 port ( A,B,C : in std_logic; START,EN : in std_logic; Y : out std_logic_vector(6 downto 0) ); end component; signal U0_COUNT : std_logic_vector(2 downto 0); begin U0 : COUNTER port map ( CLK,RESET,U0_COUNT); U1 : DECODER3to7 port map ( U0_COUNT(0),U0_COUNT(1),U0_COUNT(2), START,EN, Y ); end RTL; 4.6 library ieee; use ieee.std_logic_1164.all; use std.textio.all; use work.dice; entity TESTBNCH is end TESTBNCH; architecture stimulus of TESTBNCH is component DICE is 48

52 port ( CLK,RESET : in std_logic; Y : out std_logic_vector(6 downto 0); --COUNT : out std_logic_vector(2 downto 0); START,EN : in std_logic ); end component; constant PERIOD: time := 100 ns; signal CLK,RESET : std_logic; signal Y : std_logic_vector(6 downto 0); --signal COUNT : std_logic_vector(2 downto 0); signal START,EN : std_logic; signal done : boolean := false; begin DUT: DICE port map ( CLK,RESET, Y,--COUNT, START,EN ); CLOCK1: process begin CLK <= '1'; wait for 10 ns; CLK <= '0'; wait for 10 ns; end process CLOCK1; STIMULUS1 : process begin 49

53 START <= '0'; wait for 20 ns; START <= '1'; wait; end process STIMULUS1; STIMULUS2 : process begin EN <= '0'; wait for 145 ns; EN <= '1'; wait for 35 ns; EN <= '0'; wait for 233 ns; EN <= '1'; wait for 35 ns; EN <= '0'; wait for 70 ns; EN <= '1'; wait for 35 ns; EN <= '0'; wait for 125 ns; EN <= '1'; wait for 35 ns; EN <= '0'; wait; end process STIMULUS2; STIMULUS3 : process begin RESET <= '0'; wait for 5 ns; RESET <= '1'; wait for 10 ns; RESET <= '0'; wait for 245 ns; RESET <= '1'; wait for 10 ns; RESET <= '0'; wait; end process STIMULUS3; end stimulus; 50

54 4.3 51

55 5 IC VHDL IC VHDL 3-7 VHDL VHDL VHDL VHDL 52

56 53

57 [1] [2] [3] [4] [5] [6] CQ [7] VHDL CQ 54

58 VHDL [7] 1 VHDL VHDL VHDL signal signal BBB std_logic_vector 4 downto 0 out out [7] 55

59 for-generate if-generate 2 for in generate end generate [ ] if generate end generate [ ] for-generate for-loop exit next If-generate TRUE If else [7] wait wait Wait wait until wait on wait on wait wait 1 [7] 1 wait 56

60 case case when = = If case 1 when others others 2 case [7] 2 case and or not and or nand nor xor 6 57

61 std_logic bit std_logic_vector Boolean C VHDL 2 and or xor [7] A = B and C and D and E A = B or C or D or E A = B xor C xor D xor E 2 AND-OR A = B nand C nand D nand E -- A = B and C or D and E -- not not and 58

62 59 2 AND-OR SEL 1 A SEL 0 B [7] VHDL architecture begin component [ ] [ ] end component architecture begin [7] port map port map 2 [7]

if clear = 1 then Q <= " "; elsif we = 1 then Q <= D; end rtl; regs.vhdl clk 0 1 rst clear we Write Enable we 1 we 0 if clk 1 Q if rst =

if clear = 1 then Q <=  ; elsif we = 1 then Q <= D; end rtl; regs.vhdl clk 0 1 rst clear we Write Enable we 1 we 0 if clk 1 Q if rst = VHDL 2 1 VHDL 1 VHDL FPGA VHDL 2 HDL VHDL 2.1 D 1 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; regs.vhdl entity regs is clk, rst : in std_logic; clear : in std_logic; we

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