Intoroduction to Quartus IIマニュアル Ver. 4.2
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1 Introduction to Quartus II 4.2 Altera Corporation 101 Innovation Drive San Jose, CA (408)
2 Introduction to Quartus II Version 4.2 Rev P /JP Altera Altera FastTrack HardCopy MAX MAX+PLUS MAX+PLUS II MegaCore MegaWizard NativeLink Nios OpenCore Quartus Quartus II Quartus II SignalTap Altera Corporation Avalon ByteBlaster ByteBlasterMV Excalibur IP MegaStore Jam LogicLock MasterBlaster MegaLAB PowerFit SignalProbe USB-Blaster Altera Corporation Altera Corporation Altera Corporation ARM ARM, Limited AMBA ARM, Limited Mentor Graphics ModelSim Mentor Graphics Corporation ModelTechnology Mentor Graphics Corporation Altera reserves the right to make changes, without notice, in the devices or the device specifications identified in this document. Altera advises its customers to obtain the latest version of device specifications to verify, before placing orders, that the information being relied upon by the customer is current. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty. Testing and other quality control techniques are used to the extent Altera deems such testing necessary to support this warranty. Unless mandated by government requirements, specific testing of all parameters of each device is not necessarily performed. In the absence of written agreement to the contrary, Altera assumes no liability for Altera applications assistance, customer s product design, or infringement of patents or copyrights of third parties by or arising from use of semiconductor devices described herein. Nor does Altera warrant or represent any patent right, copyright, or other intellectual property right of Altera covering or relating to any combination, machine, or process in which such semiconductor devices might be or are used. Altera products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of Altera Corporation. As used herein: 1. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Products mentioned in this document are covered by one or more of the following U.S. patents: ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; RE35977; RE37060; and certain foreign patents. Additional patents are pending. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Copyright 2004 Altera Corporation. All rights reserved.
3 ...viii... ix EDA Tcl...23 Makefile MAX+PLUS II Quartus II...42 Quartus II...43 Quartus II...44 Verilog HDL VHDL AHDL IP Intellectual Property...47 MegaWizard Plug-In Manager...48 Quartus II...49 Verilog HDL VHDL EDA Altera Corporation Introduction to Quartus II iii
4 Settings Quartus II Verilog HDL VHDL EDA Analysis & Synthesis Quartus II Quartus II RTL Viewer Technology Map Viewer Timing Closure Floorplan Resource Optimization Advisor iv Introduction to Quartus II Altera Corporation
5 Quartus II LogicLock LogicLock LogicLock EDA LogicLock EDA EDA EDA NativeLink Quartus II Simulator Tool Quartus II Early Timing Estimate Technology Map Viewer EDA PrimeTime Tau Altera Corporation Introduction to Quartus II v
6 Timing Closure Floorplan Timing Optimization Advisor LogicLock LogicLock PowerPlay PowerPlay Early Power Estimator Programmer Quartus II JTAG SignalTap II SignalTap II SignalTap II SignalProbe In-System Memory Content Editor RTL Viewer Technology Map Viewer Chip Editor vi Introduction to Quartus II Altera Corporation
7 13 ECO ( ) Chip Editor Chip Editor Resource Property Editor Change Manager ECO EDA SOPC Builder SOPC DSP Builder DSP Quartus II Software Builder Quartus II Quartus II Quartus II Quartus II Altera Corporation Introduction to Quartus II vii
8 (Altera ) Quartus II system-on-a-programmablechip (SOPC) MAX+PLUS II ASIC Quartus II Quartus II Quartus II Quartus II Quartus II FPGA CPLD Quartus II EDA Quartus II EDA Quartus IIEDA WebQuartus II Quartus II Quartus II Quartus II viii Introduction to Quartus II Altera Corporation
9 Introduction to Quartus II : : Courier フォント Find Text Save As Start quartus d: license.dat Delete Options FLEXlm End Users Guide (< >) < > <CD-ROM > Courier quartus bin lmulti lmhostid Enter return Altera Corporation Introduction to Quartus II ix
10 : : 1 : : (choose) (select) 2 ( ) Chain Description File OK / x Introduction to Quartus II Altera Corporation
11 1 1 : EDA
12 1 : Quartus II System-ona-programmable-chip (SOPC) Quartus II FPGA CPLD 1 Quartus II 1. Quartus II Quartus II Quartus II EDA 1 2 Introduction to Quartus II Altera Corporation
13 1 : Quartus II 2 Quartus II 2. Quartus II Altera Corporation Introduction to Quartus II 3
14 1 : 3 ( ) Quartus II 3. Quartus II Quartus II Analysis & Synthesis * EDA Netlist Writer* * Start Compilation (Processing ) Start (Processing ) Start Compiler Tool (Tools ) Compiler Tool Compiler Tool 4 4 Introduction to Quartus II Altera Corporation
15 1 : 4. Compiler Tool Quartus II Processing 1 1. Quartus II Processing Start Compilation SignalProbe Early Timing Estimate Generate Functional Simulation Netlist Early Timing Estimate Start Compilation and Simulation Start > Start SignalProbe Compilation Start > Start Early Timing Estimate Altera Corporation Introduction to Quartus II 5
16 1 : Quartus II Overview: Using Compilation Flows Quartus II Quartus II Quartus II MAX+PLUS II Tools Customize MAX+PLUS II MAX+PLUS II MAX+PLUS II Quartus II 5 Customize 5. Customize 6 Introduction to Quartus II Altera Corporation
17 1 : Customize Quartus II MAX+PLUS II Quartus II Quartus II MAX+PLUS II MAX+PLUS II MAX+PLUS II MAX+PLUS II Quartus II 6 Quartus II MAX+PLUS II 6. Quartus II MAX+PLUS II Quartus II MAX+PLUS II Altera Corporation Introduction to Quartus II 7
18 1 : MAX+PLUS II WebQuartus II Handbook Volume 1 Chapter 2 Quartus II Design Flow for MAX+PLUS II Users Quartus II MAX+PLUS II Conversion module MAX+PLUS II Quartus II Overview: Working With the User Interface Customizing the User Interface Quartus II MAX+PLUS II Quick Start Guide for the Quartus II Software List of MAX+PLUS II Commands Quatus II 1. New Project Wizard (File ) 2. Verilog HDL VHDL (AHDL) MegaWizard Plug-In Manager (Tools ) IP 3. ( ) Settings (Assignments )/ LogicLock 4. ( ) SOPC Builder DSP Builder 5. ( ) Software Builder Excalibur Nios II 6. Analysis & Synthesis 7. ( ) Generate Functional Simulation Netlist 8. 8 Introduction to Quartus II Altera Corporation
19 1 : EDA 9. PowerPlay Power Analyzer ( ) LogicLock Settings Programmer 15. ( ) SignalTap II SignalProbe Chip Editor 16. ( ) Chip Editor Resource Property Editor Change Manager EDA Quartus II EDAQuartus II Quartus II 7 EDA Altera Corporation Introduction to Quartus II 9
20 1 : EDA 7. EDA 2 Quartus II EDA NativeLink NativeLink Quartus II EDAQuartus II EDA 10 Introduction to Quartus II Altera Corporation
21 1 : EDA 2. Quartus II EDA EDA Mentor Graphics Design Architect Mentor Graphics LeonardoSpectrum Mentor Graphics Precision RTL Synthesis Mentor Graphics ViewDraw Synopsys Design Compiler Synopsys Design Compiler FPGA Synopsys FPGA Compiler II Synplicity Synplify Synplicity Synplify Pro NativeLink Cadence NC-Verilog Cadence NC-VHDL Cadence Verilog-XL Mentor Graphics ModelSim Mentor Graphics ModelSim-Altera Synopsys VCS MX Synopsys VCS Synopsys VSS Mentor Graphics Tau (Stamp ) Synopsys PrimeTime Hyperlynx (Signal Integrity IBIS ) XTK (Signal Integrity IBIS ) ICX (Signal Integrity IBIS ) SpectraQuest (Signal Integrity IBIS ) Mentor Graphics Symbol Generation (Viewdraw) Cadence Incisive Conformal Synopsys Formality Magma Design Automation PALACE Altera Corporation Introduction to Quartus II 11
22 1 : EDA Settings (Assignments ) EDA Tool Settings Quartus II EDA 8 8. Settings EDA Tool Settings EDA Tool Settings EDA Quartus II EDA EDA Introduction to Quartus II Altera Corporation
23 1 : EDA 2. Verilog HDL VHDL MegaWizard Plug-In Manager (Tools ) IP 3. Quartus II EDA EDIF (.edf) VQM (.vqm) 4. ( ) Quartus II 5. Quartus II Settings (Assignments ) Quartus II 6. Quartus II a. Analysis & Synthesis b. c. d. EDA Netlist Writer EDA e. 7. ( ) Quartus II EDA 8. ( ) Quartus II EDA 9. ( ) Quartus II EDA 10. ( ) Quartus II EDA Quartus II Altera Corporation Introduction to Quartus II 13
24 1 : EDA 11. ( ) Quartus II EDA Programmer Synplicity Synplify Synplify Pro Quartus II Mentor Graphics LeonardoSpectrum Quartus II Mentor Graphics Precision RTL Synthesis Quartus II Synopsys FPGA Compiler II Quartus II Synopsis DC FPGA Quartus II Synplicity Amplify Physical Synthesis Quartus II Mentor Graphics ModelSim Quartus II Synopsys VCS Quartus II Cadence NC-Sim Quartus II Synopsys PrimeTime Quartus II Cadence Incisive Quartus II Synopsys Formality Quartus II WebQuartus II Handbook Volume 1 Chapter 8 Synplicity Synplify and Synplify Pro Support WebQuartus II Handbook Volume 1 Chapter 9 Mentor Graphics LeonardoSpectrum Support WebQuartus II Handbook Volume 1 Chapter 10 Mentor Graphics Precision RTL Synthesis Support WebQuartus II Handbook Volume 1 Chapter 11 Synopsys FPGA Compiler II BLIS and the Quartus II LogicLock Design Flow WebQuartus II Handbook Volume 1 Chapter 12 Synopsys Design Compiler FPGA Support WebQuartus II Handbook Volume 2 Chapter 11 Synplicity Amplify Physical Synthesis Support WebQuartus II Handbook Volume 3 Chapter 1 Mentor Graphics ModelSim Support WebQuartus II Handbook Volume 3 Chapter 2 Synopsys VCS Support WebQuartus II Handbook Volume 3 Chapter 3 Cadence NC-Sim Support WebQuartus II Handbook Volume 3 Chapter 6 Synopsys PrimeTime Support WebQuartus II Handbook Volume 3 Chapter 13 Cadence Incisive Conformal Support WebQuartus II Handbook Volume 3 Chapter 14 Synopsys Formality Support 14 Introduction to Quartus II Altera Corporation
25 1 : Quartus II Tcl Quartus II makefile 9 9. Altera Corporation Introduction to Quartus II 15
26 1 : Quartus II Tcl makefile 3 [ Quartus II (GUI) qmegawiz GUI MegaWizard Plug-In Manager quartus_pgmw GUI quartus_stpw SignalTap II GUI 3. ( / ) quartus_map Analysis & Synthesis quartus_fit Analysis & Synthesis quartus_drc HardCopy Analysis & Synthesis quartus_tan quartus_asm 1 quartus_eda EDA Netlist Writer EDA EDA Netlist Writer Analysis & Synthesis 16 Introduction to Quartus II Altera Corporation
27 1 : 3. ( / ) quartus_cdb (VQM Writer ) Quartus II VQM LogicLock Analysis & Synthesis quartus_sim Analysis & Synthesis quartus_pow PowerPlay Power Analyzer quartus_pgm Programmer quartus_cpf quartus_stp SignalTap II SignalTap II (.stp) SignalTap II quartus_swb Software Builder Excalibur quartus_sh Tcl Quartus II Tcl Altera Corporation Introduction to Quartus II 17
28 1 : Quartus II Quartus II < > -h < > --help < > --help=< > Quartus II Tcl API Tcl API Tcl TkGUI quartus_sh --qhelp quartus_sh --flow compile < > [-c < >] quartus_map quartus_fit quartus_asmquartus_tan quartus_drc quartus_edaquartus_cdb quartus_cmd Quartus II quartus_cmd quartus_cmd 16 3 quartus_cmd quartus_sh quartus_sh --flow compile < > [-c < > ] < >.< >.rpt 18 Introduction to Quartus II Altera Corporation
29 1 : chiptrip quartus_map quartus_map chiptrip quartus_map Analysis & Compile chiptrip.map.rpt Quartus II Quartus II Quartus IIQuartus II Quartus II (.qsf) -c speed_ch.qsf speed_ch chiptrip quartus_map quartus_map chiptrip -c speed_ch quartus_map Analysis & Synthesis speed_ch.map.rpt Quartus II Quartus II quartus_sh --flow Tcl execute_flow 4 4. ( / ) quartus_sh --flow execute_flow compile compile_and_simulate Altera Corporation Introduction to Quartus II 19
30 1 : 4. ( / ) Attempt Similar Placement SignalProbe quartus_sh --flow execute_flow attempt_similar_placement signalprobe Quartus II Overview: Using Compilation Flows Quartus IIPerl Tcl 20 Introduction to Quartus II Altera Corporation
31 1 : 10 Quartus II filtref Analysis & Synthesis /altera/qdesigns<version number>/tutorial (*.v *.bsf *.bdf) /altera/qdesigns<version number>/tutorial 10 4 /<Quartus II >/bin (UNIX Linux / <Quartus II >/<> <> solaris linux hp_ii ) PATH 10. quartus_map filtref --family=stratix quartus_fit filtref --part=ep1s10f780c5 --fmax=80mhz --tsu=8ns quartus_tan filtref Stratix Quartus II EP1S10F780C5 quartus_asm filtref 11 UNIX fir_filter Quartus II fir_filter Altera Corporation Introduction to Quartus II 21
32 1 : 11. UNIX #!/bin/sh FILES_WITH_ERRORS="" for filename in `ls *.bdf *.v` do quartus_map fir_filter --analyze_file=$filename done if [ $? -ne 0 ] then FILES_WITH_ERRORS="$FILES_WITH_ERRORS $filename" fi if [ -z "$FILES_WITH_ERRORS" ] then echo "All files passed the syntax check" exit 0 else echo "There were syntax errors in the following file(s)" echo $FILES_WITH_ERRORS exit 1 fi WebQuartus II Handbook Volume 2 Chapter 2 Command-Line Scripting WebQuartus II Scripting Reference Manual 22 Introduction to Quartus II Altera Corporation
33 1 : Tcl Quartus II Quartus II Tcl Quartus II Tcl Tcl API LogicLock Chip Editor Tcl Quartus II Tcl Quartus II APITcl Tcl Tcl (.tcl) Quartus II Templates (Edit ) Tcl Quartus II Tcl (Quartus II ) Tcl Quartus II Tcl Tcl API Generate Tcl File for Project (Project ) Tcl Tcl quartus_sh Quartus II Tcl Console Tcl Scripts (Tools ) Altera Corporation Introduction to Quartus II 23
34 1 : Tcl Quartus II Quartus II Tcl API Tcl TkGUITcl API quartus_sh --qhelp Quartus IITCL API Quartus II Overview: Using Tcl Scripting API Functions for Tcl 12 Tcl 12. Tcl ( / ) # Since ::quartus::report is not pre-loaded # by quartus_sh, load this package now # before using the report Tcl API load_package report # Since ::quartus::flow is not pre-loaded # by quartus_sh, load this package now # before using the flow Tcl API # Type "help -pkg flow" to view information # about the package load_package flow # Get Actual Fmax data from the Report File # proc get_fmax_from_report {} { # # global project_name # Load the project report database load_report $project_name # Get the actual Fmax set actual_fmax [get_timing_analysis_summary_results -clock_setup clock -actual] # Now unload the project report database unload_report } return $actual_fmax 24 Introduction to Quartus II Altera Corporation
35 1 : 12. Tcl ( / ) # Set the project name to chiptrip # set project_name chiptrip # Create or open project # if {project_exists $project_name} { # Project already exists -- open project # project_open $project_name } else { # Project does not exist -- create new project # project_new $project_name } # Fmax requirement: MHz # set required_fmax MHz # Make a clock assignment with the Fmax requirement # create_base_clock clock -fmax $required_fmax # Make global assignments # set_global_assignment -name family STRATIX set_global_assignment -name device EP1S10F484C5 set_global_assignment -name tsu_requirement 7.55ns # Make instance assignments # # The following is the same as doing: # "set_instance_assignment -name location -to clock Pin_M20" set_location_assignment -to clock Pin_M20 # Compile using ::quartus::flow # execute_flow -compile # Report Fmax from report # set actual_fmax [get_fmax_from_report] puts "" puts " " puts "Required Fmax: $required_fmax Actual Fmax: $actual_fmax" puts " " Altera Corporation Introduction to Quartus II 25
36 1 : Tcl WebQuartus II Handbook Volume 2 Chapter 3 Tcl Scripting Quartus II Overview: Using Tcl Scripting API Functions for Tcl WebQuartus II Scripting Reference Manual Makefile Quartus II Quartus II makefile 13 makefile 13. Makefile ( / ) ################################################################### # Project Configuration: # # Specify the name of the design (project) and Quartus II Settings # File (.qsf) and the list of source files used. ################################################################### PROJECT = chiptrip SOURCE_FILES = auto_max.v chiptrip.v speed_ch.v tick_cnt.v time_cnt.v ASSIGNMENT_FILES = chiptrip.qpf chiptrip.qsf ################################################################### # Main Targets # # all: build everything # clean: remove output files and database ################################################################### all: smart.log $(PROJECT).asm.rpt $(PROJECT).tan.rpt clean: rm -rf *.rpt *.chg smart.log *.htm *.eqn *.pin *.sof *.pof db 26 Introduction to Quartus II Altera Corporation
37 1 : 13. Makefile ( / ) map: smart.log $(PROJECT).map.rpt fit: smart.log $(PROJECT).fit.rpt asm: smart.log $(PROJECT).asm.rpt tan: smart.log $(PROJECT).tan.rpt smart: smart.log ################################################################### # Executable Configuration ################################################################### MAP_ARGS = --family=stratix FIT_ARGS = --part=ep1s20f484c6 ASM_ARGS = TAN_ARGS = ################################################################### # Target implementations ################################################################### STAMP = echo done > $(PROJECT).map.rpt: map.chg $(SOURCE_FILES) quartus_map $(MAP_ARGS) $(PROJECT) $(STAMP) fit.chg $(PROJECT).fit.rpt: fit.chg $(PROJECT).map.rpt quartus_fit $(FIT_ARGS) $(PROJECT) $(STAMP) asm.chg $(STAMP) tan.chg $(PROJECT).asm.rpt: asm.chg $(PROJECT).fit.rpt quartus_asm $(ASM_ARGS) $(PROJECT) $(PROJECT).tan.rpt: tan.chg $(PROJECT).fit.rpt quartus_tan $(TAN_ARGS) $(PROJECT) smart.log: $(ASSIGNMENT_FILES) quartus_sh --determine_smart_action $(PROJECT) > smart.log ################################################################### # Project initialization ################################################################### $(ASSIGNMENT_FILES): quartus_sh --prepare $(PROJECT) Altera Corporation Introduction to Quartus II 27
38 1 : 13. Makefile ( / ) map.chg: $(STAMP) map.chg fit.chg: $(STAMP) fit.chg tan.chg: $(STAMP) tan.chg asm.chg: $(STAMP) asm.chg Quartus II Overview: Using Command-Line Executables WebQuartus II Handbook Volume 2 Chapter 2 Command-Line Scripting Tcl Tcl Quartus II Overview: Using Tcl from the User Interface Overview: Using Tcl Scripting API Functions for Tcl WebQuartus II Handbook Volume 2 Chapter 3 Tcl Scripting WebQuartus II Scripting Reference Manual Quartus II LogicLock EDA 28 Introduction to Quartus II Altera Corporation
39 1 : 1 LogicLock EDA Quartus II EDA Altera Corporation Introduction to Quartus II 29
40 1 : Quartus II EDA I/O WebQuartus II Handbook Volume 1 Chapter 5 Design Recommendations for Altera Devices 30 Introduction to Quartus II Altera Corporation
41 2 2 2 :
42 2 : Quartus II (Revisions) Quartus II MegaWizard Plug-In Manager (Tools )EDA LPM (Library of Parameterized Modules) IP (Intellectual Property) Introduction to Quartus II Altera Corporation
43 2 : New Project Wizard (File) quartus_map (Quartus II ) EDA 1 Quartus II 1. Quartus II Quartus II (.qpf) Quartus II (.qsf) Quartus II Workspace (.qws) Quartus II (.qdf) Quartus II Settings (Assignments) Tcl Quartus II 1 QSF \<Quartus II >\bin QSF Settings (Assignments ) Quartus II Analysis & SynthesisQuartus II Files Copy Project (Project ) Quartus II Altera Corporation Introduction to Quartus II 33
44 2 : Project Navigator Customize Columns ( ) Project Navigator 2. Project Navigator Quartus II Quartus II Overview: Using the New Project Wizard Overview: Using the Project Navigator Overview: Working with Quartus II Projects Quartus II Design Entry module Quartus II WebQuartus II Handbook Volume 2 Chapter 4 Quartus II Project Management 34 Introduction to Quartus II Altera Corporation
45 2 : (Revisions) Quartus II QSF Revisions Settings (Assignments ) General Revisions (Project ) Revisions Create Revision ( ) Revisions 3 Altera Corporation Introduction to Quartus II 35
46 2 : 3. Revisions 36 Introduction to Quartus II Altera Corporation
47 2 : Revisions Compare Revisions Compare Revisions Results Assignments 4 Compare Revisions Results 4. Compare Revisions Results Altera Corporation Introduction to Quartus II 37
48 2 : 5 Compare Revisions Assignments 5. Compare Revisions Assignments WebQuartus II Handbook Volume 2 Chapter 4 Quartus II Project Management 38 Introduction to Quartus II Altera Corporation
49 2 : Quartus II Analysis & Synthesis quartus_map Quartus II Export Database (Project ) Quartus II Import Database (Project ) quartus_cdb Quartus II 4.1 quartus_cdb quartus_cdb quartus_cdb quartus_cdb < > -c < > --import_database= < > quartus_cdb < > -c < > --export_database= < > quartus_cdb quartus_cdb -h quartus_cdb --help quartus_cdb --help=< > Altera Corporation Introduction to Quartus II 39
50 2 : WebQuartus II Handbook Volume 2 Chapter 4 Quartus II Project Management MAX+PLUS II Convert MAX+PLUS II Project (File) MAX+PLUS II & (.acf) Quartus II MAX+PLUS II Convert MAX+PLUS II Project MAX+PLUS II Quartus II 6 Convert MAX+PLUS II Project 6. Convert MAX+PLUS II Project MAX+PLUS II Quartus II MAX+PLUS II Conversion module Quartus II Overview: Using Revisions 40 Introduction to Quartus II Altera Corporation
51 2 : Quartus II Quartus II Quartus II AHDL Verilog HDL VHDL HDL Quartus II EDIF (.edf) EDA VQM (.vqm) EDA Verilog HDL VHDL EDIF VQM Quartus II Verilog HDL VHDL EDA EDIF VQM 4 69 EDA 2 Quartus II EDA 2. EDIF Verilog VHDL VQM Quartus II EDIF EDIF MAX+PLUS II AHDL Verilog HDL VHDL Synplicity Synplify Quartus II Verilog HDL.bdf.edf.edif.gdf.tdf.v.vlg.verilog.vh.vhd.vhdl.vqm Altera Corporation Introduction to Quartus II 41
52 2 : Quartus II Quartus II MAX+PLUS II Quartus II MAX+PLUS II (.bsf) AHDL (.inc)hdl / Quartus II : MegaWizard Plug-In Manager (Tools ) LPM 48 MegaWizard Plug-In Manager 42 Introduction to Quartus II Altera Corporation
53 2 : : Quartus II LPM : Create/Update command (File ) AHDLVerilog HDL VHDL Quartus II Verilog VHDL Quartus II Quartus II AHDL VHDL Verilog HDL Tcl Quartus II ASCII AHDL Tcl VHDL Verilog HDL AHDL VHDL Verilog HDL HDL AHDL Altera Corporation Introduction to Quartus II 43
54 2 : Quartus II 1 LPM MAX+PLUS II (.sym) Verilog HDL VHDL AHDL Quartus II Verilog VHDL VerilogVHDLQuartus II Create/Update (File ) Verilog HDL VHDL Verilog HDL VHDLAHDL Verilog HDL VHDL VHDL Settings (Assignments ) Files Properties Project Navigator Files Properties VHDL Quartus II Verilog HDL VHDL 465 Quartus II Verilog HDL VHDL 44 Introduction to Quartus II Altera Corporation
55 2 : AHDL Quartus II AHDL AHDL LPM AHDL Quartus II Quartus II Quartus II Quartus II Block Editor & Symbol Editor Introduction Quartus II Text Editor Introduction Quartus II Design Entry module Quartus II LPM DSP LVDS PLLSERDES DDIO MegaWizard Plug-In Manager (Tools ) Quartus II EDA PM IP 3 MegaWizard Plug-In Manager LPM 3. LPM ( / ) LPM LPM Altera Corporation Introduction to Quartus II 45
56 2 : 3. LPM ( / ) I/O (CDR) (PLL) (DDR) (GXB) LVDS PLL FIFO Partitioner RAMROM LPM LPMAHDL VHDL MegaWizard Plug-In Manager Quartus II Overview: Using the MegaWizard Plug-In Manager Quartus II Design Entry module 46 Introduction to Quartus II Altera Corporation
57 2 : IP Intellectual Property (AMPP ) MegaCore IP MegaCore AMPP (DSP) Quartus II EDA IP AMPP : AMPP Quartus II AMPP AMPP AMPP Web IP MegaStore x MegaCore : MefgaCore MegaWizard Plug-In Manager IP IP Toolbench EDA MegaCore Quartus II MegaCore IP CD-ROM MegaCore Web IP MegaStore IP MegaCore MegaWizard Portal Extension MegaWizard Plug-In Manager MegaCore OpenCore: OpenCore AMPP OpenCore Altera Corporation Introduction to Quartus II 47
58 2 : OpenCore Plus : OpenCore Plus MegaCore Quartus II MegaCore IP OpenCore Plus Settings (Assignments ) Compilation Process Quartus II OpenCore Plus Quartus II MegaWizard Plug-In Manager MegaWizard Plug-In Manager LPM MegaCore AMPP MegaWizard Plug-In Manager MegaWizard Plug-In Manager Tools 4 MegaWizard Plug-In Manager 4. MegaWizard Plug-In Manager ( / ) < >.bsf < >.cmp < >.inc < >.tdf < >.vhd (Component Declaration File) AHDL AHDL VHDL 48 Introduction to Quartus II Altera Corporation
59 2 : 4. MegaWizard Plug-In Manager ( / ) < >.v < >_bb.v < >_inst.tdf < >_inst.vhd < >_inst.v Verilog HDL Verilog HDL EDA hollow-body (Black Box Declaration) AHDL VHDL Verilog HDL MegaWizard Plug-In Manager Quartus II MegaWizard Plug-In Manager qmegawiz Quartus II HDL ( MegaWizard Plug-In Manager )Quartus II LPM MegaWizard Plug-In Manager Altera Corporation Introduction to Quartus II 49
60 2 : Verilog HDL VHDL MegaWizard Plug-In Manager MegaWizard Plug- In Manager Verilog HDL VHDL VHDL MegaWizard Plug-In Manager Verilog HDL VHDL VHDL Quartus II Analysis & Synthesis HDL HDL RAM DSP Quartus II / RAM 50 Introduction to Quartus II Altera Corporation
61 2 : EDA EDA LPM IP EDA MegaWizard Plug-In ManagerVerilog HDL VHDL Verilog HDL MegaWizard Plug-In Manager hollow-body Verilog Verilog HDL VHDL EDA MegaWizard Plug-In Manager EDA LPM 1. MegaWizard Plug-In Manager LPM 2. MegaWizard Plug-In Manager ( ) EDA 3. EDA EDA EDA HDL (RAM ROM) DSP Verilog HDL VHDL EDA Altera Corporation Introduction to Quartus II 51
62 2 : EDA LPM EDA MegaWizard Plug-In Manager EDA LPM EDA 1. MegaWizard Plug-In Manager LPM MegaWizard Plug-In Manager Generate a Clearbox body 2. MegaWizard Plug-In Manager Verilog VHDL EDA 3. EDA LPM ( ) (Quartus II ) EDA LPM 52 Introduction to Quartus II Altera Corporation
63 2 : EDA LPM IP IP Quartus II Quartus II Overview: Creating & Instantiating Altera-Provided Functions in Other EDA Tools WebQuartus II Handbook Volume 1 Chapter 8 Synplicity Synplify and Synplify Pro Support WebQuartus II Handbook Volume 1 Chapter 9 Mentor Graphics LeonardoSpectrum Support WebQuartus II Handbook Volume 1 Chapter 10 Mentor Graphics Precision RTL Synthesis Support WebQuartus II Handbook Volume 1 Chapter 12 Synopsys Design Compiler FPGA Support Quartus II LPM MegaWizard Plug-In Manager LPM MegaCore OpenCore Plus Quartus II Design Entry module Quartus II Overview: Using the MegaWizard Plug-In Manager WebApplication Note 343 (OpenCore Evaluation of AMPP Megafunctions) WebApplication Note 320 (OpenCore Evaluation of AMPP Megafunctions) WebUsing IP Functional Simulation Models to Verify Your System Design Altera Corporation Introduction to Quartus II 53
64 3 3 : Settings
65 3 : Quartus II Settings (Assignments ) Import Assignments (Assignments ) Export (File ) Tcl EDA Quartus II Timing (Assignments ) MAX+PLUS II Assign Settings Introduction to Quartus II Altera Corporation
66 3 : Quartus II Quartus II Category 3. Node Filter Node Finder 4. Tcl Messages Export (File ) Tcl (.tcl) (.csv) Import Assignments (Project ) CSV Altera Corporation Introduction to Quartus II 57
67 3 : Quartus II Quartus II 2. Quartus II WebQuartus II Handbook Volume 2 Chapter 1 Assignment Editor Quartus II Assignment Editor Introduction Overview: Making Assignments 58 Introduction to Quartus II Altera Corporation
68 3 : Settings Settings Settings (Assignments ) Settings : EDA: / EDA Analysis & Synthesis : Analysis & Synthesis Verilog HDL VHDL : : : : ( ) PowerPlay Power Analyzer : Altera Corporation Introduction to Quartus II 59
69 3 : : SignalTap II SignalProbeHardCopy : SignalTap II SignalTap II (.stp) SignalProbe SignalProbe HardCopy HardCopy Settings Quartus II Overview: Making Assignments Import Assignments (Assignments ) Quartus II MAX+PLUS II Quartus II Import Assignments ( ) QSF Import Assignments Advanced Export (File ) CSV QSF 3 60 Introduction to Quartus II Altera Corporation
70 3 : 3. Import Assignments MAX+PLUS II MAX+PLUS II Quartus II Quartus II Quartus II Quartus II Import Assignments LogicLock Quartus II Importing Assignments Altera Corporation Introduction to Quartus II 61
71 3 : Quartus II Start > Start I/O Assignment Analysis (Processing ) I/OI/O WebQuartus II Handbook Volume 2 Chapter 5 I/O Assignment Planning and Analysis 62 Introduction to Quartus II Altera Corporation
72 4 4 : 64 Quartus II Verilog HDL VHDL 65 EDA 69 Analysis & Synthesis RTL Viewer 76 Technology Map Viewer
73 4 : Quartus II Analysis & Synthesis Analysis & Synthesis Quartus IIVerilog (.v) VHDL (.vhd) EDA Verilog HDL VHDL Quartus II EDIF (.edf) VQM (.vqm) 1 1. Quartus II Analysis & Synthesis Analysis & Synthesis Quartus II Analysis & Elaboration 64 Introduction to Quartus II Altera Corporation
74 4 : Quartus II Verilog HDL VHDL quartus_map quartus_mapanalysis & Synthesis quartus_map quartus_map quartus_map quartus_map -h quartus_map --help quartus_map --help=< > Quartus II Verilog HDL VHDL Analysis & SynthesisVerilog HDL VHDL Analysis & Synthesis Verilog HDL VHDL Quartus II Analysis & Synthesis Verilog-1995 (IEEE Std ) Verilog-2001 (IEEE Std ) VHDL 1987 (IEEE Std ) 1993 (IEEE Std ) Analysis & Synthesis Verilog-2001 VHDL 1993 EDA Quartus II (.lmf) Settings (Assignments ) Analysis & Synthesis Settings Verilog HDL Input VHDL Input 2 Altera Corporation Introduction to Quartus II 65
75 4 : Quartus II Verilog HDL VHDL 2. Settings Verilog HDL Input VHDL Input Verilog HDL Input VHDL Input 66 Introduction to Quartus II Altera Corporation
76 4 : Quartus II Verilog HDL VHDL Verilog HDL VHDL Quartus II EDA LPM (Library of parameterized modules) EDAIP (Intellectual Property) hollow-body QuartusII 49 Quartus II 2 51 EDA Verilog HDL VHDL New Project (File ) Settings Files Quartus II Quartus II VHDL FilesProperties VHDL VHDL Analysis & Synthesis VHDL work 2 41 Analysis & Synthesis Quartus II 1 Analysis & Synthesis Altera Corporation Introduction to Quartus II 67
77 4 : Quartus II Verilog HDL VHDL Analysis & Synthesis Verilog HDL VHDL + - LPM Analysis & Synthesis Analysis & Synthesis MessagesReport MessagesAnalysis & Synthesis Status Analysis & Synthesis Quartus II Verilog HDL Quartus II VHDL Quartus II Quartus II Quartus II Verilog HDL Support Quartus II Quartus II VHDL Support WebQuartus II Handbook Volume 1 Chapter 7 Quartus II Integrated Synthesis 68 Introduction to Quartus II Altera Corporation
78 4 : EDA EDA EDA Verilog HDL VHDL Quartus II EDIF VQM EDA NativeLink NativeLink Quartus II EDA Quartus IIEDA EDA Tcl Quartus II EDA Tcl 1 Quartus II EDA 1. Quartus II EDA EDIF NativeLink VQM (.vqm) (.edf) Mentor Graphics LeonardoSpectrum Mentor Graphics Precision RTL Synthesis Synopsys Design Compiler Synopsys Design Compiler FPGA Synopsys FPGA Compiler II Synplicity Synplify Synplicity Synplify Pro Settings (Assignments) EDA Tool Settings Design Entry & Synthesis EDA NativeLink EDA Quartus II EDA Tools Settings EDA 3 Altera Corporation Introduction to Quartus II 69
79 4 : EDA 3. Settings Design Entry & Synthesis Design Entry & Synthesis EDA Start > Start EDA Synthesis (Processing ) Quartus II EDA EDA Quartus II EDA 70 Introduction to Quartus II Altera Corporation
80 4 : Analysis & Synthesis Synplicity Synplify Mentor Graphics LeonardoSpectrum Mentor Graphics Precision RTL Synthesis Synopsys FPGA Compiler II Synopsys Design Compiler FPGA WebQuartus II Handbook Volume 1 Chapter 8 Synplicity Synplify and Synplify Pro Support WebQuartus II Handbook Volume 1 Chapter 9 Mentor Graphics LeonardoSpectrum Support WebQuartus II Handbook Volume 1 Chapter 10 Mentor Graphics Precision RTL Synthesis Support WebQuartus II Handbook Volume 1 Chapter 11 Synopsys FPGA Compiler II BLIS and the Quartus II LogicLock Design Flow WebQuartus II Handbook Volume 1 Chapter 12 Synopsys Design Compiler FPGA Support Analysis & Synthesis Quartus II Analysis & Synthesis Quartus II Quartus II Altera Corporation Introduction to Quartus II 71
81 4 : Analysis & Synthesis Quartus II translate_on translate_off Verilog HDL VHDL Verilog HDL VHDL Quartus II Quartus II Quartus II Verilog HDL Language Directives & Attributes VHDL Language Directives & Attributes WebQuartus II Handbook Volume 1 Chapter 7 Quartus II Integrated Synthesis Quartus II Quartus II Quartus II Settings (Assignments ) Analysis & Synthesis Settings Analysis & Synthesis 4 72 Introduction to Quartus II Altera Corporation
82 4 : Analysis & Synthesis 4. Settings Analysis & Synthesis Settings Analysis & Synthesis SettingsQuartus II DSP RAM ROM Analysis & Synthesis Altera Corporation Introduction to Quartus II 73
83 4 : Analysis & Synthesis Quartus II Quartus II Quartus II Logic Options Creating, Editing, and Deleting Assignments Specifying Settings for Default Logic Options Quartus II Compilation module WebQuartus II Handbook Volume 1 Chapter 7 Quartus II Integrated Synthesis Quartus II Quartus II Analysis & Synthesis Settings (Assignments ) Synthesis Netlist Optimizations WYSIWYG Tsu/Tco Fmax Quartus II WebQuartus II Handbook Volume 2 Chapter 8 Netlist Optimizations & Physical SynthesisChapter 6 Design Optimization for Altera Devices 74 Introduction to Quartus II Altera Corporation
84 4 : Quartus II HardCopy Settings (Assignments ) Design Assistant 5 5. Settings Design Assistant Altera Corporation Introduction to Quartus II 75
85 4 : RTL Viewer quartus_drc quartus_drc Quartus II quartus_fit quartus_drc quartus_drc quartus_drc -h quartus_drc -help quartus_drc --help=< > Quartus II Quartus II Quartus II Quartus II Analyzing Designs with the Design Assistant Overview: Using the Design Assistant Web Quartus II Handbook Volume 1 Chapter 5 Design Recommendations for Altera Devices Chapter 6 Recommended HDL Coding Styles Chapter 7 Quartus II Integrated Synthesis Quartus II AHDL, VHDL, and Verilog HDL Style Guide RTL Viewer Quartus II RTL Viewer Quartus II RTL Viewer Start > Start Analysis & Elaboration (Processing ) Analysis & Synthesis Analysis & Elaboration Analysis & ElaborationRTL Viewer (Tools ) RTL Viewer RTL Viewer 6 76 Introduction to Quartus II Altera Corporation
86 4 : RTL Viewer 6. RTL Viewer RTL Viewer Verilog HDL VHDLAHDL (.tdf) (.bdf) (.gdf)quartus II Analysis & Elaboration EDA VQM EDIF RTL Viewer WYSWYG 1 RTL Viewer fan-in fan-out RTL Viewer Chip Editor Resource Property EditorTechnology Map Viewer RTL Viewer Options (Tools ) RTL/Technology Map Viewer RTL Viewer Next Page Previous Page Go To (Edit ) RTL Viewer Altera Corporation Introduction to Quartus II 77
87 4 : Technology Map Viewer Filter ( ) 2 RTL Viewer Forward Back RTL JPEG bitmap RTL Viewer Analysis & Elaboration RTL Viewer Quartus II RTL Viewer WebQuartus II Handbook Volume 1 Chapter 13 Analyzing Designs with the Quartus II RTL Viewer and Technology Map Viewer Quartus II Overview: Viewing RTL Schematics Technology Map Viewer Quartus II Technology Map Viewer Quartus II Technology Map ViewerAnalysis & Synthesis Analysis & Synthesis Technology Map Viewer (Tools) Technology Map Viewer Technology Map Viewer 7 78 Introduction to Quartus II Altera Corporation
88 4 : Technology Map Viewer 7. Technology Map Viewer Technology Map Viewer 1 Technology Map ViewerRTL Viewer 76 RTL Viewer Technology Map Viewer Technology Map Viewer Technology Map Viewer Quartus II Technology Map Viewer WebQuartus II Handbook Volume 1 Chapter 13 Analyzing Designs with the Quartus II RTL Viewer and Technology Map Viewer Quartus II Overview: Viewing RTL Schematics Altera Corporation Introduction to Quartus II 79
89 4 : Analysis & Synthesis Analysis & Synthesis 1 1. Analysis & Elaboration 2. Project Navigator Hierarchy 1 3. Set as Incremental Design Partition ( ) Yes Enable Incremental Synthesis 4. Settings Assignments Compilation Process Settings Enable incremental synthesis 80 Introduction to Quartus II Altera Corporation
90 4 : 5. Analysis & Synthesis Start > Start Partition Merge Processing Quartus II WebQuartus II Handbook Volume 1 Chapter 7 Quartus II Integrated Synthesis Quartus II Overview: Using Incremental Synthesis Altera Corporation Introduction to Quartus II 81
91 5 5 :
92 5 : PowerFit Quartus II Quartus II Analysis & Synthesis 1 1. Settings (Assignments) Compilation Process Settings MAX+PLUS II Smart Recompile (Processing ) 84 Introduction to Quartus II Altera Corporation
93 5 : Quartus II Analysis & Synthesis quartus_fit quartus_fit Analysis & Synthesis quartus_map quartus_fit quartus_fit quartus_fit -h quartus_fit -help quartus_fit --help=< > 2 2. Altera Corporation Introduction to Quartus II 85
94 5 : Quartus II Timing Closure floorplan Chip Editor ProcessingMessages 3 3. Locate 86 Introduction to Quartus II Altera Corporation
95 5 : Help ( ) Options (Tools) Filtering Options Messages Colors Chip Editor Resource Property Editor Timing Closure Floorplan Message Location Locate Quartus II Viewing Messages Quartus II Compilation module Quartus II Locating the Source of a Message Altera Corporation Introduction to Quartus II 87
96 5 : Options (Tools ) ProcessingAutomatically open the Report window before starting a processing task if the appropriate Tool window is not already open Compiler Tool Report File 4 4. Quartus II Options Processing HTML 88 Introduction to Quartus II Altera Corporation
97 5 : Quartus II Report Window & File Format Quartus II Overview: Viewing the Results of a Compilation or Simulation in the Report Window Quartus II Compilation module Timing Closure Floorplan Timing Closure Floorplan Timing Closure floorplan LogicLock 5 5. Timing Closure Floorplan Timing Closure Floorplan Altera Corporation Introduction to Quartus II 89
98 5 : Excalibur Excalibur Timing Closure Floorplan RAM Timing Closure Floorplan MegaLAB FastTrack Timing Closure Floorplan Timing Closure Floorplan Timing Closure Floorplan Timinng Closure Floorplan Timing Closure Floorplan Timing Closure Floorplan Chip Editor Timing Closure Floorplan ECO ( ) Timing Closure floorplan Timing Closure Floorplan Quartus II Overview: Working with Assignments in the Floorplan Editor Overview: Viewing Routing Information WebQuartus II Handbook Volume 2 Chapter 7 Timing Closure Floorplan Quartus II Compilation module 90 Introduction to Quartus II Altera Corporation
99 5 : Quartus II Settings (Assignments ) Design Assistant 475 Resource Optimization Advisor Timing Closure Floorplan (LAB) Timing Closure Floorplan Assignment Editor (Tools ) Timing Closure Floorplan Tcl Settings (Assignments ) 55 3 Altera Corporation Introduction to Quartus II 91
100 5 : Timing Closure FloorplanTiming Closure Floorplan MegaLAB LAB Timing Closure Floorplan LogicLock Regions LogicLock Region Properties LogicLock Timing Closure Floorplan Regions Settings (Assignments ) Fitter Settings I/O I/O (f MAX ) ( f MAX ) ( ) Fitter Settings 1f MAX 92 Introduction to Quartus II Altera Corporation
101 5 : Quartus II Settings (Assignments ) Fitter Settings Physical Synthesis Optimizations Normal ( 2 3 ) Extra ( Normal ) Fast (Normal ) Quartus II Quartus II WebQuartus II Handbook Volume 2 Chapter 8 Netlist Optimizations & Physical Synthesis Quartus II Using Physical Synthesis Altera Corporation Introduction to Quartus II 93
102 . 5 : Quartus II (Assignments ) Quartus II Settings Fitter Settings More Settings More Fitter Settings ( ) Quartus II Quartus II Logic Options Creating, Editing & Deleting Assignments Specifying Settings for Default Logic Options Resource Optimization Advisor Resource Optimization Advisor DSP I/O Resource Optimization Advisor (Tools) Resource Optimization Advisor Resource Optimization Advisor Resource Optimization Advisor 6 Resource Optimization Advisor 94 Introduction to Quartus II Altera Corporation
103 5 : 6. Resource Optimization Advisor Summary Resource Optimization Advisor Resource Optimization Advisor 1 ( 7 ) Altera Corporation Introduction to Quartus II 95
104 5 : 7. Resource Optimization Advisor Recommendation Recommendation Recommendation Quartus II Resource Optimization AdvisorQuartus II Quartus II Web Print Recommendation ( ) Print All Recommendations ( ) Timing Optimization Advisor Timing Optimization Advisor 96 Introduction to Quartus II Altera Corporation
105 5 : Quartus II (DSE) Tcl dse.tcl DSE Quartus II quartus_sh DSE Quartus II <version number> Design Space Explorer ( Quartus II 4.2 Design Space Explorer)Quartus II Launch Design Space Explorer (Tools ) DSE DSE DSE 8 Settings 8. Settings Altera Corporation Introduction to Quartus II 97
106 5 : DSEDSE Exploration Setting Search for Best Area Search for Best Performance () Advanced Search Advanced Search Advanced 9 Advanced 9. Advanced Explore Space (Processing ) Explore 10 Explore View Last DSE Report for Project (Processing ) 98 Introduction to Quartus II Altera Corporation
107 5 : 10. Explorer DSE quartus_sh --dse DSE DSE quartus_sh --dse -nogui < > [-c < >] DSE quartus_sh --help=dse DSE Show Documentation (Help ) Altera Corporation Introduction to Quartus II 99
108 5 : DSE f MAX DSE DSE Optimization Goal DSE DSE Search Method DSE DSE DSE Quartus II WebQuartus II Handbook Volume 2 Chapter 9 Design Space Explorer WebQuartus II Handbook Volume 2 Chapter 6 Design Optimization for Altera Devices 100 Introduction to Quartus II Altera Corporation
109 5 : LogicLock Back-Annotate Assignments (Assignments ) Back-Annotate Assignments 11 Altera Corporation Introduction to Quartus II 101
110 5 : 11. Back-Annotate Assignments Back-Annotate Assignments ( ) Back-Annotate Assignments ( ) 102 Introduction to Quartus II Altera Corporation
111 5 : Back-Annotate Assignments ( ) Back-Annotate Assignments ( ) LogicLock 1 LogicLock LogicLock6 112 LogicLock LogicLock LogicLock Quartus II Back-Annotating Assignments for a Project Quartus II Back-Annotating a LogicLock Region Quartus II LogicLock module Altera Corporation Introduction to Quartus II 103
112 6 6 : 106 Quartus II 106 LogicLock EDALogicLock 115 6
113 6 : Quartus II LogicLock LogicLock LogicLock LogicLock LogicLock LogicLock LogicLock Quartus II 1 Quartus II 106 Introduction to Quartus II Altera Corporation
114 6 : Quartus II Altera Corporation Introduction to Quartus II 107
115 6 : LogicLock LogicLock LogicLock () Quartus II 1 Quartus II Quartus II LogicLock 1. LogicLock (State) (Size) (Reserved) (Enforcement) (Origin) (Floating) (Locked) (Auto) (Fixed) Quartus II Quartus II Quartus II Quartus II LogicLock LogicLock Quartus II Timing Closure Floorplan LogicLock Regions Window (Assignments ) Project Navigator Hierarchy Tcl LogicLock LogicLock ( ) Quartus II Settings File (.qsf) 108 Introduction to Quartus II Altera Corporation
116 6 : LogicLock Timing Closure Floorplan LogicLock Create New Region Timing Closure Floorplan NodeFinderProject Navigator Hierarchy LogicLock LogicLock LogicLock Regions LogicLock LogicLock 2 2. LogicLock Regions LogicLock Regions Properties LogicLock Back-Annotate Assignments LogicLock LogicLock LogicLock Quartus II LogicLock Region Properties Priority 3 Altera Corporation Introduction to Quartus II 109
117 6 : LogicLock 3. LogicLock Region Properties Analysis & Elaboration Quartus II Project Navigator Hierarchy LogicLock Timing Closure Floorplan LogicLock Quartus II Tcl Console LogigLock LogicLock Tcl Tcl LogicLock 110 Introduction to Quartus II Altera Corporation
118 6 : Quartus II LogicLock WebQuartus II Handbook Volume 2 Chapter 10 LogicLock Design Methodology Quartus II Overview: Using LogicLock Regions Quartus II LogicLock module LogicLockQSF VQM (.vqm) LogicLock IP VQM VQM VQM LogicLock QSF 1. LogicLock Back-Annotate Assignments ( ) LogicLock ( ) 4. Export Assignments (Assignments) LogicLock QSF Altera Corporation Introduction to Quartus II 111
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