Quartus II Integrated Synthesis, Quartus II 6.0 Handbook, Volume 1

Transcription

1 7. Quartus II QII Quartus II VHDL Verilog HDL Quartus II Quartus II Quartus II Quartus II HDL Quartus II HDL Quartus II VHDL & Verilog HDL Quartus II Altera Corporation 7 1

2 Quartus II Volume 1 Quartus II Analysis & Synthesis Verilog HDL VHDL 7 5 SystemVerilog LE ALM Quartus II Analysis & Synthesis Analyze Current File Processing Analyze Current File Analysis & Elaboration Processing Start Start Analysis & Elaboration Analysis & Synthesis Processing Start Start Analysis & Synthesis Quartus II Quartus II 1. Quartus II 2. Quartus II 3. Setting Files Quartus II Quartus II 7 2 Altera Corporation Preliminary

3 5. Quartus II Processing Start Start Analysis & Synthesis Processing Start Compilation 6. Quartus II TimeQuest Quartus II Quartus II Quartus II Quartus II Introduction to Quartus II Manual Altera Corporation 7 3 Preliminary

4 Quartus II Volume Quartus II 7-1. Quartus II Quartus II Verilog HDL VHDL AHDL BDF Formal Verification Using Source Code as Golden Netlist Functional/RTL Simulation Constraints & Settings Analysis & Synthesis Internal Synthesis Netlist Post Synthesis Simulation File (.vho/.vo) Gate-Level Functional Simulation Constraints & Settings Fitter Assembler Timing Analyzer Gate-Level Timing Simulation Post Place-and-Route Simulation File (.vho/.vo) No Timing & Area Requirements Satisfied? Yes Formal Verification Using VO as Revised Netlist Post Place-and-Route Formal Verification File (.vo) Configuration/ Programming Files (.sof/.pof) Configure/Program Device 7 4 Altera Corporation Preliminary

5 HDL Quartus II 1 Quartus II Verilog HDL Quartus II Verilog HDL Verilog-1995 IEEE Verilog-2001 IEEE System Verilog-2005 IEEE Quartus II Verilog HDL 1. Assignments Settings 2. Settings Category Analysis & Synthesis Settings Verilog HDL Input OK 3. Verilog HDL Input Verilog version Verilog OK Verilog HDL 7 26 Verilog VHDL Quartus II Verilog-2001 Verilog HDL Verilog-2001 Quartus II Verilog HDL Verilog HDL Altera Corporation 7 5 Preliminary

6 Quartus II Volume 1 Quartus II / \ include Quartus II Verilog 2001 Quartus II Verilog-2001 SystemVerilog Quartus II SystemVerilog logic bit byte shortint longint int enum enum struct typedef typedefs forward always_comb always_latch always_ff += -= *= /= %= &= = ^= <<= >>= <<<= >>>= case unique priority / Verilog-2001 System Verilog System Verilog Quartus II 7 6 Altera Corporation Preliminary

7 Verilog HDL Quartus II Verilog HDL `define Quartus II Verilog HDL GUI GUI Verilog GUI Assignments Settings Category Analysis & Synthesis Settings Verilog HDL Input Verilog HDL macro Setting Add Verilog 7 1 Verilog 7 1. Verilog quartus_map <Design name> --verilog_macro= "<Macro Name>=<Macro Setting>" 7 2 Verilog HDL `define a= Verilog a=2 quartus_map my_design --verilog_macro="a=2" Verilog a=2 & a=3 quartus_map my_design --verilog_macro="a=2" --verilog_macro="b=3" VHDL Quartus II VHDL VHDL 1987 IEEE VHDL 1993 IEEE Altera Corporation 7 7 Preliminary

8 Quartus II Volume 1 Quartus II VHDL 1. Assignments Settings 2. Settings Category Analysis & Synthesis Settings VHDL Input OK 3. VHDL Input VHDL version OK 4. VHDL 7 26 Verilog VHDL Quartus II VHDL 1993 VHDL VHDL 1993 VHDL Quartus II IEEE VHDL VHDL VHDL IEEE VHDL std_logic_1164 numeric_std numeric_bit math_real STD VHDL standard textio Quartus II IEEE std_logic_arith std_logic_unsigned Synopsys ARITHMETIC std_logic_arith Mentor Graphics 7 8 Altera Corporation Preliminary

9 ALTERA altera_primitives_components GLOBAL DFFE maxplus2 MAX+PLUS II ALTERA_MF altera_mf_components stratixgx_mf_components LCELL LPM library of parameterized modules LPM lpm_components Quartus II Quartus II 5.1 altera_mf_components altera_primitives_components GLOBAL DFFE Quartus II VHDL Project Add/Remove Files In Project Quartus II 5.1 VHDL Quartus II VHDL VHDL Quartus II VHDL VHDL Settings Quartus II.qsf Tcl VHDL Altera Corporation 7 9 Preliminary

10 Quartus II Volume 1 Quartus II VHDL Setting VHDL 1 1. Assignments Settings 2. Settings Files File Name 3. Properties 4. File Properties Type VHDL File 5. Library 6. OK Quartus II Tcl Quartus II Tcl VHDL_FILE -library VHDL Quartus II Tcl Quartus II my_file.vhd VHDL my_lib 7 4. set_global_assignment VHDL_FILE my_file.vhd library my_lib Tcl 7 72 VHDL VHDL library 7 10 Altera Corporation Preliminary

11 VHDL altera synthesis pragma synopsys exemplar library 7 25 library work Settings Quartus II Tcl library library 7 5 library my_entity my_lib 7 5. library -- synthesis library my_lib library ieee; use ieee.std_logic_1164.all; entity my_entity(...) end entity my_entity; Settings Quartus II Tcl 1 library VHDL 1 1 Quartus II Altera Corporation 7 11 Preliminary

12 Quartus II Volume 1 AHDL Quartus II & AHDL AHDL.tdf AHDL include AHDL.inc Quartus II AHDL Quartus II AHDL Quartus II &.bdf Quartus II MAX+PLUS II.gdf.bsf MAX+PLUS II.sym MAX+PLUS II Quartus II Quartus II BDF BSF Quartus II 7 12 Altera Corporation Preliminary

13 Quartus II Quartus II Quartus II Quartus II Quartus II Volume 1 Quartus II 7-2 Altera Corporation 7 13 Preliminary

14 Quartus II Volume Quartus II Perform Analysis & Elaboration Turn on Integrated Synthesis Create Design Partitions Repeat until Satisfied with Partitions Perform Complete Compilation (All Partitions are Compiled) Make Changes to Design Perform Incremental Compilation (Partitions are Compiled if Required) Repeat as Needed During Design & Debugging Stages 7-3 B F A B C D E F Representation A Representation B Top A 1 C F B B D E 7 14 Altera Corporation Preliminary

15 7-3. Representation A Partition Top A B C D E F Partition B Partition F Representation B A B C D E EF Quartus II 7 16 Quartus II 6.0 Quartus II Altera Corporation 7 15 Preliminary

16 Quartus II Volume 1 1. Precessing Start Start Analysis & Elaboration Quartus II 2. PARTITION_HIERARCHY Project Navigator Compilation Hierarchy Project Navigator Set as Design Partition 3. Assignments Settings Settings 4. Settings Compilation Process Settings Incremental compilation Incremental synthesis only Incremental synthesis only GUI PARTITION_HIERARCHY Project Navigator Set as Design Partition Processing Start Compilation Start Compilation 7 16 Altera Corporation Preliminary

17 Quartus II Quartus II Quartus II Volume 1 Quartus II Quartus II Quartus II Processing Start Tools Compilation Tool Processing Start Start Analysis & Synthesis Quartus II Processing Start Start Partition Merge Altera Corporation 7 17 Preliminary

18 Quartus II Volume 1 Settings Compilation Process Incremental compilation Off Incremental synthesis only 1 Quartus II Quartus II Altera LogicLock SignalTap II Quartus II Volume 1Design Recommendations for Altera Devices 7 18 Altera Corporation Preliminary

19 I/O GND Quartus II MegaWizard Plug-In Manager MegaWizard MegaWizard Quartus II Quartus II Quartus II Altera Corporation 7 19 Preliminary

20 Quartus II Volume 1 DSP RAM Quartus II LE ALM Quartus II DSP RAM 7 42 MegaWizard Plug-In Manager RAM DSP Quartus II Volume 2 Quartus II Volume 1 Quartus II 7 20 Altera Corporation Preliminary

21 Quartus II OpenCore Plus MegaCore OpenCore Plus MegaCore Quartus II Quartus II 7 22 Quartus II 3 Quartus II HDL Verilog VHDL Optimization Technique Speed Optimization Technique for Clock Domains PowerPlay Power Optimization State Machine Processing syn_encoding enum_encoding Preserve Hierarchical Boundary Restructure Multiplexers Power-Up Level Power-Up Don t Care Remove Duplicate Logic Remove Duplicate Registers Remove Redundant Logic Cells Preserve Registers Noprune Synthesis Attribute/Preserve Fanout Free Node Keep Combinational Node/Implement as Output of Logic Cell Maximum Fan-Out RAM Style & ROM Style for Inferred Memory RAM Initialization File for Inferred Memory Multiplier Style for Inferred Multipliers Full Case Parallel Case Translate Off & On Ignore Translate Off Read Comments as HDL Altera Corporation 7 21 Preliminary

22 Quartus II Volume 1 Quartus II Verilog HDL VHDL 7 54 HDL Quartus II Settings Quartus II HDL Settings Analysis & Synthesis Assignments Settings Settings Analysis & Synthesis Settings Quartus II Quartus II Quartus II Tools Assignment Editor Tcl Quartus II HDL Quartus II Quartus II Verilog HDL VHDL Verilog HDL VHDL HDL Quartus II Tcl Quartus II HDL HDL Quartus II 7 22 Altera Corporation Preliminary

23 Quartus II Quartus II Quartus II Tcl HDL Verilog-2001 SystemVerilog VHDL Verilog-1995 HDL <attribute> <attribute type> <value> <object> <object type> Verilog HDL 7 6. Verilog-1995 HDL // synthesis <attribute> [ = <value> ] /* synthesis <attribute> [ = <value> ] */ 7 6 Verilog-1995 Verilog HDL 1 HDL reg r; // synthesis <attribute> //synthesis <attribute1> [ = <value> ] <attribute2> [ = <value> ] maxfan Maximum Fan-Outmy_reg preserve 7 37 Preserve Registers reg my_reg /* synthesis maxfan = 16 preserve */; Altera Corporation 7 23 Preliminary

24 Quartus II Volume 1 synthesis pragma synopsys exemplar altera Quartus II exemplar pragma altera 7 7. Verilog-2001 & System Verilog (* <attribute> [ = <mvalue> ] *) 7 7 Verilog-2001 Verilog HDL Verilog-2001 (* <attribute1> [ = <value1>], <attribute2> [ = <value2> ] *) maxfan Maximum Fan-Outmy_reg preserve 7 37 Preserve Registers (* preserve, maxfan = 16 *) reg my_reg; 7 8. VHDL attribute <attribute> : <attribute type> ; attribute <attribute> of <object> : <object type> is <value>; 7 8 VHDL VHDL Altera altera_syn_attributes VHDL 7 24 Altera Corporation Preliminary

25 Quartus II LIBRARY altera; USE altera.altera_syn_attributes.all; QuartusII Verilog HDL VHDL Verilog HDL VHDL <directive> <value> Verilog HDL 7 9. Verilog HDL // synthesis <directive> [ =<value> ] /* synthesis <directive> [ =<value> ] */ VHDL -- synthesis <directive> [ =<value> ] synthesis Verilog HDL VHDL pragma synopsys exemplar altera Quartus II exemplar pragma altera Quartus II Altera Corporation 7 25 Preliminary

26 Quartus II Volume 1 Verilog VHDL Verilog HDL VHDL Settings Quartus II VERILOG_INPUT_VERSION VHDL_INPUT_VERSION Verilog HDL // synthesis VERILOG_INPUT_VERSION <language version> <language version> VERILOG_1995 VERILOG_2001 SYSTEMVERILOG_ VHDL --synthesis VHDL_INPUT_VERSION <language version> <language version> VHDL87 VHDL93 VERILOG_INPUT_VERSION VHDL_INPUT_VERSION VERILOG_INPUT_VERSION VHDL_INPUT_VERSION Verilog VHDL 7 26 Altera Corporation Preliminary

27 Quartus II Optimization Technique Optimization Technique 7 1 Settings Analysis & Synthesis Settings 7 1. Optimization Technique Area Speed Balanced (1) f MAX f MAX 7 1 (1) / Speed Optimization Technique for Clock Domains Speed Optimization Technique for Clock Domains Analysis & Synthesis Settings Optimization Technique Optimization Technique Altera Corporation 7 27 Preliminary

28 Quartus II Volume 1 Speed Optimization Technique for Clock Domains 1 Stratix II Stratix II GX Stratix Stratix GX Cyclone II Cyclone HardCopy II HardCopy Stratix MAX II PowerPlay Power Optimization Analysis & Synthesis Analysis & Synthesis Assingments Settings Category Analysis & Synthesis Settings Analysis & Synthesis Settings PowerPlay 3 Off Analysis & Synthesis Normal Compilation Analysis & Synthesis Extra Effort Analysis & Synthesis 7 28 Altera Corporation Preliminary

29 Quartus II State Machine Processing 7 2 Settings Analysis & Synthesis Settings 7 2. State Machine Processing Auto Minimal Bits One-Hot One Hot User-Encoded Auto FPGA one hit CPLD minimal bits Quartus II Recommended HDL Coding Styles Verilog HDL State Machine Processing User-Encoded Verilog HDL parameter S0 = 4'b1010, S1 = 4'b0101,... S0 S1... 4'b1010 4'b Altera Corporation 7 29 Preliminary

30 Quartus II Volume 1 VHDL User-Encoded State Machine Processing VHDL syn_encoding 7 30 syn_encoding syn_encoding Quartus II 7 29 State Machine Processing VHDL VHDL User-Encoded State Machine Processing syn_encoding 7 13 syn_encoding count_state 0 = 11 1 = 01 2 = 10 3 = syn_encoding VHDL ARCHITECTURE rtl OF my_fsm IS TYPE count_state is (zero,one,two,three); ATTRIBUTE syn_encoding : STRING; ATTRIBUTE syn_encoding OF count_state : TYPE IS" "; SIGNAL present_state next_state : count_state; BEGIN enum_encoding Quartus II one-hot enum_encoding one-hot 7 30 Altera Corporation Preliminary

31 Quartus II enum_encoding Report State Machine Processing syn_encoding synthesis VHDL enum_encoding enum_encoding defaultsequentialgrayone-hot IEEE std_logic_1164 std_ulogic 7 14 enum_encoding fruit type fruit is (apple, orange, pear, mango); attribute enum_encoding : string; attribute enum_encoding of fruit : type is " "; apple = "11" orange = "01" pear = "10" mango = "00" Quartus II 4 Altera Corporation 7 31 Preliminary

32 Quartus II Volume 1 default 5 sequential 6 50 one-hot gray sequential gray 1 one-hot N N 7 14 enum_encoding fruit gray 7 15 gray gray type fruit is (apple, orange, pear, mango); attribute enum_encoding : string; attribute enum_encoding of fruit : type is "gray"; Preserve Hierarchical Boundary Quartus II 6.0 Preserve Hierarchical Boundary Preserve Hierarchical Boundary Quartus II 7 15 Restructure Multiplexers Quartus II 7 32 Altera Corporation Preliminary

33 Quartus II LE ALM Stratix II Stratix Stratix GX Cyclone II Cyclone MAX II Restructure Multiplexers ifcase?: Verilog HDL VHDL Verilog HDL VHDL STD_LOGIC_VECTOR Restructure Multiplexers Restructure Multiplexers 20% f MAX 7 3 Settings Analysis & Synthesis Settings 7 3. Restructure Multiplexers On Off f MAX f MAX Auto Quartus II Optimization Technique Area Balanced On Optimization Technique Speed Off Optimization Technique Stratix Stratix II Balanced Altera Corporation 7 33 Preliminary

34 Quartus II Volume 1 Compilation Report Analysis & Synthesis Analysis & Synthesis Optimization Results Multiplexer Statistics Multiplexer Restructuring Statistics 7 4 Multiplexer Restructuring Statistics 7 4. Multiplexer Inputs Bus Width Baseline Area Area if Restructured Saving if Restructured Registered Example Multiplexer Output Multiplexer Restructuring Multiplexer Restructuring Multiplexer Restructuring 2 Quartus II Volume 1Design Recommendations for Altera Devices Power-Up Level High (1) Low (0) 0 High NOT-gate push back NOT-gate push back High Low High 7 34 Altera Corporation Preliminary

35 Quartus II VHDL Quartus II VHDL Power-Up Level VHDL Quartus II Verilog HDL NOT gate push-back set reset Quartus II Volume 1Recommended HDL Coding Styles Power-Up Don t Care D VCC High Low High Altera Corporation 7 35 Preliminary

36 Quartus II Volume 1 VCC Power-Up Level High Low Remove Duplicate Logic Remove Duplicate Registers Remove Duplicate Registers 7 5 LCELL Remove Duplicate Logic LCELL Remove Duplicate Registers Remove Duplicate Logic Remove Duplicate Logic 7 36 Altera Corporation Preliminary

37 Quartus II Off Remove Duplicate Logic & Remove Duplicate Registers Remove Duplicate Logic Remove Duplicate Registers Remove Duplicate Registers Remove Redundant Logic Cells LCELL WYSIWYG Preserve Registers SignalTap II I/O 1 I/O 1 2 preserve Altera Corporation 7 37 Preliminary

38 Quartus II Volume Noprune Synthesis Attribute/Preserve Fanout Free Node Preserve Registers Preserve Registers Quartus II GUI HDL preserve my_reg preserve Quartus II syn_preserve Verilog HDL preserve reg my_reg /* synthesis preserve = 1 */; Verilog-2001 syn_preserve (* syn_preserve = 1 *) reg my_reg; preserve = VHDL preserve signal my_reg : stdlogic; attribute preserve : boolean; attribute preserve of my_reg : signal is true; Noprune Synthesis Attribute/Preserve Fanout Free Node Reserve Registers 7 38 Altera Corporation Preliminary

39 Quartus II SignalTap II Preserve Fanout Free Node Quartus II GUI HDL noprune my_reg noprune syn_noprune Verilog HDL noprune reg my_reg /* synthesis noprune = 1 */; Verilog 2001 noprune (* noprune = 1 *) reg my_reg; VHDL noprune signal my_reg : stdlogic; attribute noprune: boolean; attribute noprune of my_reg : signal is true; Keep Combinational Node/Implement as Output of Logic Cell keep Altera Corporation 7 39 Preliminary

40 Quartus II Volume 1 Implement as Output of Logic Cell SignalTrap II <net name>~reg0 Implement as Output of Logic Cell Quartus II GUI HDL keep my_wire. keep Quartus II syn_keep Verilog HDL keep wire my_wire /* synthesis keep = 1 */; Verilog-2001 keep (* keep = 1 *) wire my_wire; VHDL syn_keep signal my_wire: bit; attribute syn_keep: boolean; attribute syn_keep of my_wire: signal is true; Maximum Fan-Out 7 40 Altera Corporation Preliminary

41 Quartus II Fitter MAX 3000 MAX 7000 FLEX 10K ACEX 1K Mercury Quartus II DSP RAM / 3 Quartus II Quartus II maxfan preserve preserve Quartus II Volume 2Netlist Optimization & Physical Synthesis Maximum Fan-Out Quartus II GUI HDL maxfan clk_gen 50 maxfan Quartus II syn_maxfan Altera Corporation 7 41 Preliminary

42 Quartus II Volume Verilog HDL syn_maxfan reg clk_gen /* synthesis syn_maxfan = 50 */; Verilog-2001 maxfan (* maxfan = 50 *) reg clk_gen; VHDL maxfan signal clk_gen : stdlogic; attribute maxfan : signal ; attribute maxfan of clk_gen : signal is 50; Quartus II HDL HDL RAM DSP Quartus II Volume 1Recommended HDL Coding Styles Quartus II - & - Auto DSP Block Replacement DSP 7 42 Altera Corporation Preliminary

43 Quartus II Settings Analysis & Synthesis Settings Assignment Editor altmult_accum altmult_add DSP Auto Shift Register Replacement Settings Analysis & Synthesis Settings Assignment Editor Allow Any Shift Register Size for Recognition altmult_taps RAM Auto Shift Register Replacement EDA Tool Settings MegaWizard Plug-in Manager / RAM & ROM RAM ROM Auto RAM Replacement Auto ROM Replacement Settings Altera Corporation 7 43 Preliminary

44 Quartus II Volume 1 Analysis & Synthesis Settings Assignment Editor RAM ROM Allow Any RAM Size for Recognition Allow Any ROM Size for Recognition Auto ROM Replacement EDA Tool Settings ROM MegaWizard Plug-in Manager ROM / ROM RAM RAM EDA Tool Settings Auto RAM Replacement Quartus II RAM RAM RAM 7 44 Altera Corporation Preliminary

45 Quartus II RAM Style & ROM Style for Inferred Memory RAM ROM TriMatrix LE ALM TriMatrix ramstyle romstyle 1 M512 M4KM-RAM RAM ROM logic RAM ROM VHDL Verilog HDL logic RTL RAM ROM ramstyle romstyle Quartus II syn_ramstyle my_memory_blocks Verilog-1995 romstyle module my_memory_blocks (...) /* synthesis romstyle = "M4K" */ Verilog-2001 ramstyle (* ramstyle = "M512" *) module my_memory_blocks (...); VHDL romstyle architecture rtl of my_ my_memory_blocks is attribute romstyle : string; attribute romstyle of rtl : architecture is "M-RAM"; begin Altera Corporation 7 45 Preliminary

46 Quartus II Volume my_ram my_rom TriMatrix Verilog-1995 syn_ramstyle reg [0:7] my_ram[0:63] /* synthesis syn_ramstyle = "logic" */; Verilog-2001 romstyle (* romstyle = "logic" *) reg [0:7] my_rom[0:63]; VHDL ramstyle type memory_t is array (0 to 63) of std_logic_vector (0 to 7); signal my_ram : memory_t; attribute ramstyle : string; attribute ramstyle of my_ram : signal is "logic"; RAM Initialization File for Inferred Memory ram_init_file.mif RAM Verilog-1995 ram_init_file reg [7:0] mem[0:255] /* synthesis ram_init_file = " my_init_file.mif" */; Verilog-2001 ram_init_file (* ram_init_file = "my_init_file.mif" *) reg [7:0] mem[0:255]; VHDL ram_init_file type mem_t is array(0 to 255) of unsigned(7 downto 0); signal ram : mem_t; attribute ram_init_file : string; attribute ram_init_file of ram : signal is "my_init_file.mif"; 7 46 Altera Corporation Preliminary

47 Quartus II VHDL Quartus II RAM MIF Multiplier Style for Inferred Multipliers multstyle * HDL multstyle dsp Quartus II DSP multstyle logic dsp Verilog HDL * VHDL multstyle Quartus II syn_multstyle Verilog HDL * multstyle my_module Quartus II Verilog 1995 multstyle module my_module (...) /* synthesis multstyle = "dsp" */; Verilog 2001 multstyle (* multstyle = "dsp" *) module my_module(...); Altera Corporation 7 47 Preliminary

48 Quartus II Volume 1 Verilog HDL multstyle result multstyle a * b Quartus II Verilog 2001 multstyle wire [8:0] a, b; (* multstyle = "logic" *) wire [17:0] result; assign result = a * b; //Multiplication must be //directly assigned to result Verilog 1995 multstyle wire [8:0] a, b; wire [17:0] result /* synthesis multstyle = "logic" */; assign result = a * b; //Multiplication must be //directly assigned to result * multstyle 7 41 multstyle a * b Verilog 2001 multstyle wire [8:0] a, b; wire [17:0] result; assign result = a * (* multstyle = "dsp" *) b; Verilog-1995 multstyle VHDL * 7 42 multstyle my_entity rtl Quartus II 7 48 Altera Corporation Preliminary

49 Quartus II VHDL multstyle architecture rtl of my_entity is attribute multstyle : string; attribute multstyle of rtl : architecture is "dsp"; begin VHDL * multstyle 7 43 result multstyle a * b Quartus II VHDL multstyle signal a, b : unsigned(8 downto 0); signal result : unsigned(17 downto 0); attribute multstyle : string; attribute multstyle of result : signal is "logic"; result <= a * b; Full Case Verilog HDL case case case case case full_case don t care VHDL case VHDL case Quartus II Volume 1Design Recommendations for Altera Devices case full_case 7 22 Altera Corporation 7 49 Preliminary

50 Quartus II Volume 1 full_case Verilog HDL Quartus II case case sel 2'b11 HDL Quartus II don t care full_case HDL case full 7 44 case sel full_case sel 2'b11 don t care Verilog HDL full_case module full_case (a, sel, y); input [3:0] a; input [1:0] sel; output y; reg y; (a or sel) case (sel) // synthesis full_case 2'b00: y=a[0]; 2'b01: y=a[1]; 2'b10: y=a[2]; endcase endmodule Verilog case Verilog-2001 full_case (* full_case *) case (sel) 7 50 Altera Corporation Preliminary

51 Quartus II Parallel Case parallel_case Verilog HDL case 1 case Verilog HDL case case case Verilog HDL case case case case Quartus II Case parallel_case Quartus II case case case 1 case VHDL case case Verilog HDL Verilog HDL Quartus II parallel_case Verilog HDL SystemVerilog-2005 SystemVerilog unique parallel_case case casez HDL 3 case sel sel[2] sel[1] sel[1] sel[0] parallel_case sel High a b c High HDL Altera Corporation 7 51 Preliminary

52 Quartus II Volume Verilog HDL parallel_case module parallel_case (sel, a, b, c); input [2:0] sel; output a, b, c; reg a, b, c; (sel) begin {a, b, c} = 3'b0; casez (sel) // synthesis parallel_case 3'b1??: a = 1'b1; 3'b?1?: b = 1'b1; 3'b??1: c = 1'b1; endcase end endmodule Verilog case casez Verilog-2001 (* parallel_case *) casez (sel) Translate Off & On translate_off translate_on Quartus II HDL translate_off translate_on Verilog HDL Translate Off & On // synthesis translate_off parameter tpd = 2; // #tpd; // synthesis translate_on 7 52 Altera Corporation Preliminary

53 Quartus II VHDL Translate Off & On -- synthesis translate_off use std.textio.all; -- synthesis translate_on Quartus II altera // altera translate_off // altera translate_on Quartus II Ignore Translate Off Ignore Translate Off Quartus II translate_off translate_on Quartus II Ignore Translate Off Settings Analysis & Synthesis Settings More Settings Read Comments as HDL read_comments_as_hdl Quartus II HDL Quartus II HDL read_comments_as_hdl on read_comments_as_hdl off translate_off translate_on 1 HDL Altera Corporation 7 53 Preliminary

54 Quartus II Volume 1 read_comments_as_hdl read_comments_as_hdl Quartus II Verilog HDL Verilog HDL Read Comments as HDL // synthesis read_comments_as_hdl on // my_rom lpm_rom (.address (address), //.data (data)); // synthesis read_comments_as_hdl off VHDL Read Comments as HDL -- synthesis read_comments_as_hdl on -- my_rom : entity lpm_rom -- port map ( -- address => address, -- data => data, ); -- synthesis read_comments_as_hdl off HDL Quartus II HDL Quartus II Quartus II chip_pin Use I/O Flip-Flops HDL Altera AttributeHDL Quartus II Quartus II Quartus II Tcl Use I/O Flip-Flops I/O I/O Quartus II useioff clock-to-output clockto-output I/O 7 54 Altera Corporation Preliminary

55 HDL Quartus II Assignment Editor Fast Input Register Fast Output Register Fast Output Enable Register Quartus II useioff Verilog HDL VHDL 1 Verilog HDL TRUE VHDL I/O Quartus II 0 Verilog HDL FALSE VHDL I/O useioff a_reg b_reg o_reg a b o I/O Quartus II Verilog HDL useioff module top_level(clk, a, b, o); input clk; input [1:0] a, b /* synthesis useioff = 1 */; output [2:0] o /* synthesis useioff = 1 */; reg [1:0] a_reg, b_reg; reg [2:0] o_reg; (posedge clk) begin a_reg <= a; b_reg <= b; o_reg <= a_reg + b_reg; end assign o = o_reg; endmodule Verilog Verilog-2001 useioff (* useioff = 1 *) input [1:0] a, b; (* useioff = 1 *) output [2:0] o; Altera Corporation 7 55 Preliminary

56 Quartus II Volume useioff VHDL library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity top_level is port ( clk : in std_logic; a, b : in unsigned(1 downto 0); o : out unsigned(1 downto 0)); attribute useioff : boolean; attribute useioff of a : signal is true; attribute useioff of b : signal is true; attribute useioff of o : signal is true; end top_level; architecture rtl of top_level is signal o_reg, a_reg, b_reg : unsigned(1 downto 0); begin process(clk) begin a_reg <= a; b_reg <= b; o_reg <= a_reg + b_reg; end process; o <= o_reg; end rtl; Altera Attribute HDL Quartus II altera_attribute HDL HDL Fitting Analysis & Synthesis Altera Attribute Quartus II Quartus II Tcl HDL 7 22 Quartus II 7 56 Altera Corporation Preliminary

57 HDL Quartus II -name <variable_1> <value_1>;-name <variable_2> <value_2>[; ] Quartus II Quartus II -from <source> -to <target> -section_id <section> -name <variable> <value> 2 Quartus II "[-from <source_1>] [-to <target_1>] [-section_id <section_1>] -name <variable_1> <value_1>; [-from <source_2>] [-to <target_2>] [-section_id <section_2>] -name <variable_2> <value_2>" Verilog HDL "VARIABLE_NAME \"STRING_VALUE\"" VHDL "VARIABLE_NAME""STRING_VALUE"" Quartus II Quartus II Setting File Quartus II Quartus II Quartus II Settings File Reference Manual altera_attribute 1 Quartus II Verilog-1995 Altera Attribute reg my_reg /* synthesis altera_attribute = "-name POWER_UP_LEVEL HIGH" */; Altera Corporation 7 57 Preliminary

58 Quartus II Volume Verilog-2001 Altera Attribute (* altera_attribute = "-name POWER_UP_LEVEL HIGH" *) reg my_reg; VHDL Altera Attribute signal my_reg : std_logic; attribute altera_attribute : string; attribute altera_attribute of my_reg: signal is "-name POWER_UP_LEVEL HIGH"; altera_attribute Auto Shift Register Replacement VHDL Altera Attribute Verilog-1995 Altera Attribute module my_entity( ) /* synthesis altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF" */; Verilog-2001 Altera Attribute (* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF" *) module my_entity( ) ; VHDL Altera Attribute entity my_entity is -- Declare generics and ports end my_entity; architecture rtl of my_entity is attribute altera_attribute : string; -- Attribute set on architecture, not entity attribute altera_attribute of rtl: architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF"; begin -- The architecture body end rtl; 7 58 Altera Corporation Preliminary

59 HDL Quartus II altera_attribute altera_attribute reg1 reg2 Tcl QSF set_instance_assignment -name CUT ON -from reg1 -to reg Verilog to Altera Attribute reg reg2; reg reg1 /* synthesis altera_attribute = "-name CUT ON -to reg2" */; Verilog to Altera Attribute reg reg2; (* altera_attribute = "-name CUT ON -to reg2" *) reg reg1; VHDL -to Altera Attribute signal reg1, reg2 : std_logic; attribute altera_attribute: string; attribute altera_attribute of reg1 : signal is "-name CUT ON -to reg2"; 1 altera_attribute -to -from altera_attribute -to reg2 * Quartus II reg1 altera_attribute Altera Corporation 7 59 Preliminary

60 Quartus II Volume 1 chip_pin HDL 1 chip_pin chip_pin Quartus II Quartus my_pin1 Pin C1 my_pin2 Pin Verilog-1995 Chip Pin input my_pin1 /* synthesis chip_pin = "C1" */; input my_pin2 /* synthesis altera_chip_pin_lc = "@4" */; Verilog-2001 Chip Pin (* chip_pin = "C1" *) input my_pin1; (* altera_chip_pin_lc = "@4" *) input my_pin2; VHDL Chip Pin entity my_entity is port(my_pin1: in std_logic; my_pin2: in std_logic; ); end my_entity; attribute chip_pin : string; attribute altera_chip_pin_lc : string; attribute chip_pin of my_pin1 : signal is "C1"; attribute altera_chip_pin_lc of my_pin2 : signal is "@4" I/O 7 60 Altera Corporation Preliminary

61 7 67 my_pin[2] Pin_4 my_pin[1] Pin_5 my_pin[0] Pin_ Verilog-1995 Chip Pin input [2:0] my_pin /* synthesis chip_pin = "4, 5, 6" */; 7 68 my_pin[0] Pin_4 my_pin[2] Pin_6 my_pin[1] Verilog-1995 Chip Pin input [0:2] my_pin /* synthesis chip_pin = "4,,6" */; 7 69 my_pin[2] Pin 4 my_pin[0] Pin 6 my_pin[1] VHDL Chip Pin entity my_entity is port(my_pin: in std_logic_vector(2 downto 0); ); end my_entity; attribute chip_pin of my_pin: signal is "4,, 6"; Messages Analysis & Synthesis Project Navigator Messages Analysis & Synthesis Altera Corporation 7 61 Preliminary

62 Quartus II Volume 1 Analysis & Synthesis Processing Analysis & Synthesis Fitter Summary Analysis & Synthesis Analysis & Synthesis Quartus II Project Navigator Project Navigator Hierarchy Analysis & Synthesis Fitter Project Navigator Hierarchy Altera Corporation Preliminary

63 VHDL & Verilog HDL VHDL & Verilog HDL Quartus II Verilog HDL VHDL HDL HDL HDL Info Warning Error 3 Info Warning HDL HDL Error HDL HDL 7 70 i Verilog HDL / j HDL //dup.v module dup(input i, input j, output reg o); (i) o = i & j; endmodule HDL Quartus II Warning: (10276) Verilog HDL sensitivity list warning at dup.v(2): sensitivity list contains multiple entries for "i". Altera Corporation 7 63 Preliminary

64 Quartus II Volume 1 Verilog HDL 7 71 my_reg MY_REG 2 VHDL HDL Info // namecase.v module namecase (input i, output o); reg my_reg; reg MY_REG; assign o = i; endmodule HDL Quartus II Info: (10281) Verilog HDL information at namecase.v(3): variable name "MY_REG" and variable name "my_reg" should not differ only in case. Quartus II my_reg MY_REG HDL Info Info: (10035) Verilog HDL or VHDL information at namecase.v(3): object "my_reg" declared but not used Info: (10035) Verilog HDL or VHDL information at namecase.v(4): object "MY_REG" declared but not used HDL Quartus II HDL HDL HDL Message Level 7 25 Quartus II Quartus II Volume 2 Quartus II Project Management 7 64 Altera Corporation Preliminary

65 VHDL & Verilog HDL HDL Message Level HDL Message Level Quartus II 7 6 HDL 7 6. HDL Info Level1 HDL Level1 Level1 Quartus II Level2 Level3 HDL Level2 HDL Level3 HDL LINT Level1 HDL Level2 HDL Message Level Assignments Settings Category Analysis & Synthesis Settings HDL Message Level message_level synthesis level1 level2 level Verilog HDL message_level // altera message_level level1 /* altera message_level level3 */ VHDL message_level -- altera message_level level2 Altera Corporation 7 65 Preliminary

66 Quartus II Volume 1 message_level message_level VHDL message_level HDL Message Level HDL Message Level message_level Verilog HDL HDL Message Level message_level HDL HDL Message ID Message ID HDL Message Level HDL GUI Settings Analysis & Synthesis Settings HDL Message Level Advanced Advanced Message Settings Message ID HDL HDL message_on message_off Message ID Verilog HDL VHDL VHDL HDL message_on message_off HDL Message Level message_level message_on message_off ID Verilog HDL message_off // altera message_off /* altera message_off */ 7 66 Altera Corporation Preliminary

67 Quartus II ID VHDL message_off -- altera message_off Quartus II Quartus II HDL Verilog HDL VHDL AHDL BDF Quartus II LE ALM LE ALM Quartus II Volume 2Netlist Optimizations & Physical Synthesis Quartus II Fitter Fitter I/O - Quartus II : A my_a_inst A:my_A_inst Altera Corporation 7 67 Preliminary

68 Quartus II Volume 1 <entity 0>:<instance_name 0> <entity 1>: <instance_name 1>... <instance_name n> A DFF atom my_dff A:my_A_inst my_dff Settings Compilation Process Settings Display Entity Name for Node Name <instance_name 0> <instance_name 1>... <instance_name n> DFF D Virilog HDL VHDL reg signal DFF my_dff_out Verilog HDL Verilog HDL wire dff_in, my_dff_out, clk; (posedge clk) my_dff_out <= dff_in; 7 77 my_dff_out DFF VHDL VHDL signal dff_in, my_dff_out, clk; process (clk) begin if (rising_edge(clk)) then my_dff_out <= dff_in; end if; end process; 7 68 Altera Corporation Preliminary

69 Quartus II AHDL DFF BDF DFF my_dff_out Quartus II I/O my_dff_out Quartus II ~reg Verilog HDLq~reg Verilog HDL module my_dff (input clk, input d, output q); (posedge clk) q <= d; endmodule q DSP RAM FPGA DSP Altera Corporation 7 69 Preliminary

70 Quartus II Volume 1 RAM DSP HDL 1 one-hot Verilog HDL VHDL parameter state0 = 1 state1 = 2 state2 = 3 reg [1:0] my_fsm Verilog HDL 3 one-hot my_fsm.state0 my_fsm.state1 my_fsm.state2 AHDL my_fsm 4 my_fsm~12 my_fsm~13 my_fsm~14 my_fsm~15 DSP Quartus II RAM ROM DSP Verilog HDL VHDL Quartus II Recommended HDL Coding Styles DSP RAM DSP LE ALM 7 70 Altera Corporation Preliminary

71 Quartus II RAM & DSP & RAM DSP LE ALM RAM DSP Quartus II Recommended HDL Coding Styles Verilog HDL VHDL AHDL Quartus II 7 79 Verilog HDL Quartus II c d e f Verilog HDL wire c; reg d, e, f; assign c = a b; (a or b) d = a & b; (a or b) begin : my_label e = a ^ b; end (a or b) f = ~(a b); BDF Stratix Cyclone Stratix II Cyclone II Altera Corporation 7 71 Preliminary

72 Quartus II Volume 1 (~ 1 w w w~1 w~2 w rtl~123 Quartus II ~< > Tcl Quartus II Command-Line Tcl API Help Help quartus_sh --qhelp Scripting Reference Manual PDF Tcl Quartus II Volume 1 Tcl Quartus II Quartus II Settings File Reference Manual Quartus IIVolume 1Command- Line Scripting Tcl set_global_assignment -name <QSF Variable Name> <Value> Tcl set_instance_assignment -name <QSF Variable Name> <Value>\ -to <Instance Name> 7 72 Altera Corporation Preliminary

73 Quartus II 7 7 Quartus II Quartus II Tcl Type 7 7. Quartus II ( / ) Quartus II Allow Any RAM Size for Recognition ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON, OFF Allow Any ROM Size for Recognition Allow Any Shift Register Size for Recognition Auto DSP Block Replacement Auto RAM Replacement Auto ROM Replacement Auto Shift-Register Replacement ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON, OFF ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_ RECOGNITION ON, OFF AUTO_DSP_RECOGNITION ON, OFF AUTO_RAM_RECOGNITION ON, OFF AUTO_ROM_RECOGNITION ON, OFF AUTO_SHIFT_REGISTER_RECOGNITION ON, OFF Fast Input Register FAST_INPUT_REGISTER ON, OFF Fast Output Enable Register Fast Output Register Implement as Output of Logic Cell FAST_OUTPUT_ENABLE_REGISTER ON, OFF FAST_OUTPUT_REGISTER ON, OFF IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL ON, OFF Maximum Fan-Out MAX_FANOUT <Maximum Fan-Out Value> Altera Corporation 7 73 Preliminary

74 Quartus II Volume Quartus II ( / ) Quartus II Optimization Technique < > _OPTIMIZATION_TECHNIQUE Area, Speed, Balanced PowerPlay Power Optimization OPTIMIZE_POWER_DURING_SYNTHESIS "NORMAL COMPILATION", "EXTRA EFFORT", OFF Power-Up Don t Care ALLOW_POWER_UP_DONT_CARE ON, OFF Power-Up Level POWER_UP_LEVEL HIGH, LOW Preserve Hierarchical Boundary PRESERVE_HIERARCHICAL_BOUNDARY Off, Relaxed, Firm Preserve Registers PRESERVE_REGISTER ON, OFF Remove Duplicate Logic Remove Duplicate Registers Remove Redundant Logic Cells Restructure Multiplexers Speed Optimization Technique for Clock Domains State Machine Processing REMOVE_DUPLICATE_LOGIC ON, OFF REMOVE_DUPLICATE_REGISTERS ON, OFF REMOVE_REDUNDANT_LOGIC_CELLS ON, OFF MUX_RESTRUCTURE On, Off, Auto SYNTH_CRITICAL_CLOCK ON, OFF STATE_MACHINE_PROCESSING AUTO, "MINIMAL BITS", "ONE HOT", "USER-ENCODED" 7 74 Altera Corporation Preliminary

75 Tcl set_location_assignment -to <signal name> <location> For example, set_location_assignment -to data_input Pin_A3 I/O EDGE_BOTTOM EDGE_LEFT EDGE_TOP EDGE_RIGHT I/O IOBANK_1 IOBANK_n n I/O set_instance_assignment -name PARTITION_HIERARCHY \ <file name> -to <destination> -section_id <partition name> <destination> ram:ram_unit altsyncram:altsyncram_component 7 67 Quartus II <partition name> 1024 : _ Altera Corporation 7 75 Preliminary

76 Quartus II Volume 1 <file name> Quartus II Tcl my_file MY_FILE db Tcl set_global_assignment -name INCREMENTAL_COMPILATION \ INCREMENTAL_SYNTHESIS Quartus II Tcl quartus_sh execute_flow compile quartus_sh execute_flow compile quartus_map quartus_fit quartus_map 2 1. quartus_map --incremental compilation=incremental_synthesis 7 76 Altera Corporation Preliminary

77 quartus_map 2. Quartus II quartus_cdb merge Quartus II Verilog HDL VHDL Altera Corporation 7 77 Preliminary

78 Quartus II Volume Altera Corporation Preliminary