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1 1 Kazutoshi Kobayashi

2 1, Verilog-HDL, Verilog-HDL Verilog-HDL,, FPGA,, HDL, 11, 1 (a) (b) (c) FPGA (d) 2 10,, Verilog-HDL, FPGA, 12,,,, html % netscape file://home/users11/kobayasi/kobayasi/refresh/indexhtml,, View Encoding Japanese (Auto-Detect) 1

3 2 21 FPGA, Verilog-HDL RTL, FPGA, Synplicity SynplifyPro( Synplify ) Synplify Verilog-HDL RTL( ), FPGA,, FPGA Synplify, circuit, circuitedf EDIF, FPGA circuitacf 2 FPGA, FPGA ALTERA MAX+PLUSII(, MPII) MPII, Synplify edf acf, FPGA, acf FPGA SRAM FPGA, sof, ttf, pof MPII, SRAM acf Synplify, MPII FPGA 22 Verilog-HDL 1 Verilog roulettev roulettesimv 2 verilog Verilog-XL % verilog roulettesimv roulettev 0: xxxxxx 10: : :

4 81950: : : Verilog, 7 LED LED 1 1: roulettev module roulette(out,clk,rst); input CLK,RST; output [5:0] out; reg [5:0] out; reg [10:0] divide; // 11, 2 11 (2048 ) CLK or negedge RST) if(!rst) out<=1;divide<=0; else if(divide==0)// 2048, out[0]<=out[5]; out[1]<=out[0]; out[2]<=out[1]; out[3]<=out[2]; out[4]<=out[3]; out[5]<=out[4]; divide<=divide+1; // 1 module 2: roulettesimv timescale 1ns/100ps // 1ns, 100ps module roulettesim; reg CLK,RST; wire [5:0] out; ifdef MAX roulette I0(out5(out[5]),out4(out[4]),out3(out[3]),out2(out[2]), out1(out[1]),out0(out[0]),clk(clk),rst(rst)); //, else roulette I0(out(out),CLK(CLK),RST(RST)); if initial CLK=0;RST=1; #10 RST=0; #10 RST=1;// 10ns 3

5 # $finish;//, 200usec always #10 //, 20ns CLK= CLK; initial $monitor("%d: ",$time,"%b",out); initial $dumpfile("roulettevcd"); // $dumpvars;// ifdef SDF initial $sdf_annotate("roulette/roulettesdo",i0,,"sdflog", "TOOL_CONTROL", " : : ","FROM_MTM" ); // SDF if module 23 SynplifyPro 1 SynplifyPro, FPGA,, roulette netscape, roulettesdc 2 SynplifyPro % synplify_pro 3, Synplicity License Agreement, YES 4, Tip of the Day, Show Tips at Startup, OK File Build Project, verilog, roulettev, Add ( 22) 7, Files of type Constraint Files(*sdc), roulettesdc, Add OK, ( 23), Verilog-HDL, Add File, 4

6 21: SynplifyPro 22: 5

7 23: 24: 25: FPGA 6

26: Implementation Name 8 rouletteprj, roulette(project) verilog, constraint, rev 1(roulette) ( 24) 9 Impl Options ( 25) Device, 21 21: Device Technology Altera Flex10K Part EPF10K40 Speed -4 Packege

8 26: Implementation Name 8 rouletteprj, roulette(project) verilog, constraint, rev 1(roulette) ( 24) 9 Impl Options ( 25) Device, 21 21: Device Technology Altera Flex10K Part EPF10K40 Speed -4 Packege RC208 10, Implementation Results, Implementation Name roulette ( 26), OK 11 ( 24) Run, roulette ( ),,, roulettev EDIF rouletteedf 12 File Exit Save changes to project roulette, Yes, Save 24 MAX+plusII FPGA 241 MAX+PLUS2 1 MAX+plusII % max2win 7

MAX+PLUSII 101,, (project) Processing Fitter Setting ( 211),

9 27: 28: 2 27 OK, 3, 28, Yes 4 File Project Name, ( ) edf ( 29), roulette/rouletteedf 5 MAX+plus II Compiler, ( 210) 6 MAX+PLUSII 101,, (project) Processing Fitter Setting ( 211), Use Quartus Fitter for FLEX 10K and ACEX 1K Devices 7 Start, Warning,, 8

10 29: 210: 211: Fitter Setting 9

11 212: Programmer 213: Hardware Setup 25 1, 41 2 MAX+plusII Programmer 3, Options Hardware Setup, Hardware, MasterBlaster(COM) ( 213) 4 Programmer Configure, LED 10

12 BCD 2 51 binshiftreg module module binshiftreg1v module binshiftreg(out,decimal,clk,rst,ce); output [6:0] out; input [9:0] decimal; input CLK,RST,CE; // input, output module assign unction binshiftreg function dectobin d binshiftreg2v module binshiftreg(out,decimal,clk,rst,ce); output [6:0] out; input [9:0] decimal; input CLK,RST,CE; wire [3:0] d; // 1 wire assign d=dectobin(decimal); // function dectobin d function [3:0] dectobin; // [3:0] input [9:0] in; // function if(in[9]) // function if, case dectobin = 9; else if(in[8]) dectobin = 8; else if(in[7]) dectobin = 7; // else if(in[0]) dectobin = 0; function module // else count REGA always binshiftreg 11

13 54 out assign binshiftregv module binshiftreg(out,decimal,clk,rst,ce); output [6:0] out; input [9:0] decimal; input CLK,RST,CE; wire [3:0] d; reg [1:0] count; reg [6:0] REGA; assign d=dectobin(decimal); function [3:0] dectobin; input [9:0] in; if(in[9]) dectobin = 9; else if(in[8]) dectobin = 8; else if(in[7]) dectobin = 7; else if(in[6]) dectobin = 6; else if(in[5]) dectobin = 5; else if(in[4]) dectobin = 4; else if(in[3]) dectobin = 3; else if(in[2]) dectobin = 2; else if(in[1]) dectobin = 1; else if(in[0]) dectobin = 0; function CLK or negedge RST) if(!rst) REGA<=0; count<=0; else if((decimal!= 0) && (count < 2)) REGA<=(REGA*10)+d; count<=count+1; else if(ce) REGA<=0; count<=0; assign out=rega; module 12

14 55 6 (syncro) 2 BCD 7 LED (binled) syncro, ledout, bintobcd verilog (otherv) module syncro(out,in,clk,rst); parameter WIDTH = 1; input [WIDTH-1:0] in; output [WIDTH-1:0] out; input CLK,RST; reg [ WIDTH-1:0] q0,q1,q2; CLK or negedge RST) if(!rst) q0<=0; else q0<= in; CLK or negedge RST) if(!rst) q1<=0; else q1<=q0; CLK or negedge RST) if(!rst) q2<=0; else q2<=q1; assign out=q1&( q2); module module binled(in,ledh,ledl); input [6:0] in; output [6:0] ledh,ledl; wire [3:0] outh,outl; bintobcd I0(in(in),outl(outl),outh(outh)); ledout I1(in(outl),out(ledl)); ledout I2(in(outh),out(ledh)); module module bintobcd(in,outl,outh); input [6:0] in; output [3:0] outl,outh; wire [6:0] tmp1,tmp2,tmp3; assign outh[3] = (in>=80)? 1 : 0; assign tmp1 = (in>=80)? in-80 : in; assign outh[2] = (tmp1>=40)? 1 : 0; assign tmp2 = (tmp1>=40)? tmp1-40 : tmp1; assign outh[1] = (tmp2>=20)? 1 : 0; assign tmp3 = (tmp2>=20)? tmp2-20 : tmp2; assign outh[0] = (tmp3>=10)? 1 : 0; assign outl = (tmp3>=10)? tmp3-10 : tmp3; module 13

15 define SEG_OUT_0 7 b011_1111 define SEG_OUT_1 7 b000_0110 define SEG_OUT_2 7 b101_1011 define SEG_OUT_3 7 b100_1111 define SEG_OUT_4 7 b110_0110 define SEG_OUT_5 7 b110_1101 define SEG_OUT_6 7 b111_1101 define SEG_OUT_7 7 b010_0111 define SEG_OUT_8 7 b111_1111 define SEG_OUT_9 7 b110_1111 define SEG_OUT_ERR 7 b011_1001 module ledout(out,in); input [3:0] in; output [6:0] out; function [6:0] convert; input [3:0] in ; case (in) 0: convert = SEG_OUT_0; 1: convert = SEG_OUT_1; 2: convert = SEG_OUT_2; 3: convert = SEG_OUT_3; 4: convert = SEG_OUT_4; 5: convert = SEG_OUT_5; 6: convert = SEG_OUT_6; 7: convert = SEG_OUT_7; 8: convert = SEG_OUT_8; 9: convert = SEG_OUT_9; default: convert = SEG_OUT_ERR; // If the above line is omitted, A warning messsage is shown in Synplify Pro case function assign out=convert(in); module 56 binshifttop binshifttop binshifttop GTK binshifttopsdc: 311,, X Window GUI, GUI, verilog PLI(Programming Language Interface) C GUI, verilog gtksimsh Verilog binshifttop, UNIX 14

31: GUI % gtksimsh binshiftsimgtkv binshifttopv binshiftregv otherv, GUI( 31) Q,,,, binshifttop 10 CE RST 7 LED LED, overflow 312 SynplifyPro binshifttop, synplifypro binshifttop, FPGA, enzantop,

16 31: GUI % gtksimsh binshiftsimgtkv binshifttopv binshiftregv otherv, GUI( 31) Q,,,, binshifttop 10 CE RST 7 LED LED, overflow 312 SynplifyPro binshifttop, synplifypro binshifttop, FPGA, enzantop, calctop 1 2 binshifttopsdc 3 SynplifyPro, % synplify_pro 4 File Build Project, verilog, binshifttopv, binshiftregv, otherv, Add, Ctrl 5, Files of type Constraint Files(*sdc), binshifttopsdc, Add OK, 6, (project) roulette(project), 15

17 7 Impl Options Device, 31 31: Device Technology Altera Flex10K Part EPF10K40 Speed Packege RC208-4, Implementation Results, Implementation Name binshifttop, Result File Name binshifttopedf, OK 8 Run, binshifttop ( ),,, binshifttop EDIF binshifttopedf 9 File Exit Save changes to project binshifttop, Yes, Save 313 max+plus2 1 max+plus2 % max2win 2 File Project Name, FPGA CompilerII ( ) edf, binshifttop/binshifttopedf 3 MAX+plus II Compiler, 4 Processing Fitter Setting, Use Quartus Fitter for FLEX 10K and ACEX 1K Devices 5 Start, 6 25, 16

18 enzan Verilog-HDL module + = out enzanv 58 enzantop enzantop enzantop GTK enzantopsdc: 321 % gtksimsh enzansimgtkv enzantopv enzanv otherv inversev module inverse; reg [4:0] A,B,C;// 5 initial A=3;B=-2; $display("a=%d,%b, B=%d,%b",A,A,B,B); C=8-5; // 3 #100 C=5-8; // -3 #100 C=-10-8; // -18( ) #100 initial C=10+10; // 20( ) $monitor("%d: ",$time,"c=%d, -%d, %b",c, C+5 b00001,c); // C+1, 32 module inversesignedv(signed ) 17

19 module inverse; reg signed [4:0] A,B,C;// 5 initial A=3;B=-2; $display("a=%d,%b, B=%d,%b",A,A,B,B); C=8-5; // 3 #100 C=5-8; // -3 #100 C=-10-8; // -18( ) #100 initial C=10+10; // 20( ) $monitor("%d: ",$time,"c=%d, %b",c,c); // C 10 2 module (signed ) (calctopv) verilog/calcsimgtkv calctopsdc: 331 % gtksimsh calcsimgtkv calctopv calcsignedv otherv 18

20 4 FPGA 41, Power Medusa MU200-EA40 42, LED( ) 41: 183 CLK 7 A 7 E 180 RST 208 h (7) 163 h (7) 207 g (6) 162 g (6) 86 SW f (5) 161 f (5) 89 SW e (4) 160 e (4) 93 SW d (3) 159 d (3) 94 SW c (2) 158 c (2) 85 SW b (1) 157 b (1) 88 SW a (0) 150 a (0) 92 SW25 7 B 7 F 75 SW h (7) 149 h (7) 83 SW g (6) 148 g (6) 87 SW f (5) 147 f (5) 90 SW e (4) 144 e (4) 74 SW d (3) 143 d (3) 65 SW c (2) 142 c (2) 68 SW b (1) 141 b (1) 70 SW a (0) 136 a (0) 73 SW34 7 C 7 G 64 SW h (7) 139 h (7) 67 SW g (6) 134 g (6) 69 SW f (5) 133 f (5) continued on next page 19

21 continued from previous page 71 SW e (4) 132 e (4) LED 177 d (3) 131 d (3) 103 LED-A 176 c (2) 128 c (2) 102 LED-B 175 b (1) 127 b (1) 101 LED-C 174 a (0) 122 a (0) 100 LED-D 7 D 7 H 99 LED-E 173 h (7) 121 h (7) 97 LED-F 172 g (6) 120 g (6) 96 LED-G 170 f (5) 119 f (5) 95 LED-H 169 e (4) 116 e (4) 168 d (3) 115 d (3) 167 c (2) 112 c (2) 166 b (1) 111 b (1) 164 a (0) 104 a (0) 43 7 LED 7 LED FPGA 1 LED LED FPGA, 20MHz/2ˆ( ), 4, 125MHz 45 ( ON/OFF ),,, 4 (125MHz ) 1, ,, ON 20

22 ON ON ON ON ON ON OFF ON ON LED-A LED-B LED-C LED-D LED LED-E LED-F LED-G LED-H / / EPF10K 40RC RST ON ON A B C D E F G H 7 LED SW19 SW23 SW27 SW31 SW35 SW20 SW24 SW28 SW32 SW36 SW21 SW25 SW29 SW33 SW37 SW22 SW26 SW30 SW34 SW : FPGA e f d a g c b h 42: 7 LED 21

23 SW19 SW23 SW27 SW31 SW SW20 SW24 SW28 SW32 SW = SW21 SW25 SW29 SW33 SW FPGA 0 CE SW22 SW26 SW30 SW34 SW : 2 1, 0 22

24 5 51,, GUI PLI,,,, PLI, kobayasi/refresh 52 Verilog, signed, Verilg-XL, NC-verilog Cadence : Solaris, HP-UX, Windows VCS Synopsys : Solaris, HP-UX, Windows, Linux modelsim Mentor Graphics : Solaris, HP-UX, Windows, Linux PLI,,,, Windows Modelsim, PLI, Solaris, Linux Verilog-XL PLI 53 Modelsim on Windows 531 Modelsim Windows Verilog, Verilog 2001 signed, Mentor Graphics ( Modelsim Modelsim, Altera( Xilinx( Modelsim Altera Edition, Xilinx Edition,, Altera, Max+PlusII, Quartus, Modelsim, Xilinx, 23

25 , Modelsim XE Starter,, Xilinx /wwwxilinxcojp/,, ModelSim, MXE Starter - Limited Version of MXE(Free), WEB, 532 GTK+ GUI, GTK+ tml/gimp/win32/, libiconv-1x*zip libintl-0*zip glib-2*zip gtk+-1*zip zip dll, C:\windows\system\ (NT, 2000 C:\winnt\system32\), gtkcalc/modelsim/gtkcalcexe,, 533 gtkcalc/modelsim/mti pli appsdll,gtkcalc/modelsim/mti pli appslib,gtkcalc/modelsim/mti pli appsexp,, ModelSim win32xoem modelsim modelsimini,, modelsimini, ; List of dynamically loaded objects for Verilog PLI applications ; Veriuser = veriusersl Veriuser = $MODEL_TECH/mti_pli_appsdll [lmc], modelsim,, 54 Verilog-XL on Solaris 541 GTK+ gtkcalc/gtklibtgz,,, 24

26 542 gtkcalc/solaris/libvpiso 543 gtkcalc/solaris/gtksimsh, CALCLIB= GTKLIB= CALCLIB=, libvpiso, GTKLIB= gtksimsh, chmod +x gtksimsh 55 Verilog-XL on Linux Linux,, GTK+,, GTK+, libvpiso, 551 gtkcalc/linux/libvpiso 552 gtkcalc/linux/gtksimsh, CALCLIB= CALCLIB=, libvpiso gtksimsh, chmod +x gtksimsh 56 PLI PLI gtkcalc/gtkcalctgz 25

VLD Kazutoshi Kobayashi

VLD Kazutoshi Kobayashi (kobayasi@kuee.kyoto-u.ac.jp) 2005 8 26-29 1, Verilog-HDL, Verilog-HDL. Verilog-HDL,, FPGA,, HDL,. 1.1, 1. (a) (b) (c) FPGA (d). 2. 10,, Verilog-HDL, FPGA,. 1.2,,,, html. % netscape