DS30292A-J-page 2 Preliminary 2000 Microchip Technology Inc. PIC16F876/

Transcription

1 PDIP H ) MCLR/VPP/THV RA0/AN0 RA1/AN1 RA2/AN2/VREF- RA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RD0/PSP0 RD1/PSP PIC16F877/ RB7/PGD RB6/PGC RB5 RB4 RB3/PGM RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 H H In-Circuit Serial Programming H H H 2000 Microchip Technology Inc. Preliminary DS30292A-J-page 1

2 DS30292A-J-page 2 Preliminary 2000 Microchip Technology Inc. PIC16F876/ MCLR/VPP/THV RA0/AN0 RA1/AN1 RA2/AN2/VREF- RA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RB7/PGD RB6/PGC RB5 RB4 RB3/PGM RB2 RB1 RB0/INT VDD VSS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA PIC16F877 RA4/T0CKI RA5/AN4/SS RE0/RD/AN5 OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CK1 NC RE1/WR/AN6 RE2/CS/AN7 VDD VSS RB3/PGM RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT RA3/AN3/VREF+ RA2/AN2/VREF- RA1/AN1 RA0/AN0 MCLR/VPP/THV NC RB7/PGD RB6/PGC RB5 RB4 NC NC RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1 RC1/T1OSI/CCP PIC16F RA3/AN3/VREF+ RA2/AN2/VREF- RA1/AN1 RA0/AN0 MCLR/VPP/THV NC RB7/PGD RB6/PGC RB5 RB4 NC RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1 RC1/T1OSI/CCP2 NC NC RC0/T1OSO/T1CKI OSC2/CLKOUT OSC1/CLKIN VSS VDD RE2/AN7/CS RE1/AN6/WR RE0/AN5/RD RA5/AN4 RA4/T0CKI RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 VSS VDD RB0/INT RB1 RB2 RB3/PGM PLCC QFP DIP, SOIC PIC16F874 PIC16F874

3 PICmicro (DS33023) PIC16F873 PIC16F874 PIC16F876 PIC16F877 DC - 20 MHz DC - 20 MHz DC - 20 MHz DC - 20 MHz POR, BOR (PWRT, OST) POR, BOR (PWRT, OST) POR, BOR (PWRT, OST) POR, BOR (PWRT, OST) 4K 4K 8K 8K Ports A,B,C Ports A,B,C,D,E Ports A,B,C Ports A,B,C,D,E MSSP, USART MSSP, USART MSSP, USART MSSP, USART PSP PSP Microchip Technology Inc. Preliminary DS30292A-J-page 3

4 DS30000A DS30000 A ( ( (U.S. FAX: (602) ) E tech@microchip.co.jp DS30292A-J-page 4 Preliminary 2000 Microchip Technology Inc.

5 EEPROM PIC16F873 4K PIC16F876 8K Program Bus OSC1/CLKIN OSC2/CLKOUT FLASH Program Memory 14 Instruction reg Instruction Decode & Control Timing Generation 8 13 Program Counter 8 Level Stack (13-bit) Direct Addr 7 Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset In-Circuit Debugger Low-Voltage Programming Data Bus 8 RAM File Registers RAM Addr (1) Addr MUX ALU W reg Indirect 8 Addr FSR reg STATUS reg MUX PORTA PORTB PORTC RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4/SS RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT MCLR VDD, VSS Timer0 Timer1 Timer2 10-bit A/D Data EEPROM CCP1,2 Synchronous Serial Port USART 2000 Microchip Technology Inc. Preliminary DS30292A-J-page 5

6 EEPROM PIC16F874 4K PIC16F877 8K Program Bus OSC1/CLKIN OSC2/CLKOUT FLASH Program Memory 14 Instruction reg Instruction Decode & Control Timing Generation 8 13 Program Counter 8 Level Stack (13-bit) Direct Addr 7 Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset In-Circuit Debugger Low-Voltage Programming Data Bus RAM File Registers RAM Addr (1) Addr MUX ALU W reg 8 Indirect 8 Addr FSR reg STATUS reg MUX Parallel Slave Port PORTA PORTB PORTC PORTD PORTE RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4/SS RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT RD7/PSP7:RD0/PSP0 RE0/AN5/RD MCLR VDD, VSS RE1/AN6/WR RE2/AN7/CS Timer0 Timer1 Timer2 10-bit A/D Data EEPROM CCP1,2 Synchronous Serial Port USART DS30292A-J-page 6 Preliminary 2000 Microchip Technology Inc.

7 DIP Pin# SOIC Pin# I/O/P Type Buffer Type OSC1/CLKIN 9 9 I ST/CMOS (3) OSC2/CLKOUT O MCLR/VPP/THV 1 1 I/P ST RA0/AN0 2 2 I/O TTL RA1/AN1 3 3 I/O TTL RA2/AN2/VREF- 4 4 I/O TTL RA3/AN3/VREF+ 5 5 I/O TTL RA4/T0CKI 6 6 I/O ST RA5/SS/AN4 7 7 I/O TTL RB0/INT I/O TTL/ST (1) RB I/O TTL RB I/O TTL RB3/PGM I/O TTL RB I/O TTL RB I/O TTL RB6/PGC I/O TTL/ST (2) RB7/PGD I/O TTL/ST (2) RC0/T1OSO/T1CKI I/O ST RC1/T1OSI/CCP I/O ST RC2/CCP I/O ST RC3/SCK/SCL I/O ST RC4/SDI/SDA I/O ST RC5/SDO I/O ST RC6/TX/CK I/O ST RC7/RX/DT I/O ST VSS 8, 19 8, 19 P VDD P 2000 Microchip Technology Inc. Preliminary DS30292A-J-page 7

8 DIP Pin# PLCC Pin# QFP Pin# I/O/P Type Buffer Type OSC1/CLKIN I ST/CMOS (4) OSC2/CLKOUT O MCLR/VPP/THV I/P ST RA0/AN I/O TTL RA1/AN I/O TTL RA2/AN2/VREF I/O TTL RA3/AN3/VREF I/O TTL RA4/T0CKI I/O ST RA5/SS/AN I/O TTL RB0/INT I/O TTL/ST (1) RB I/O TTL RB I/O TTL RB3/PGM I/O TTL RB I/O TTL RB I/O TTL RB6/PGC I/O TTL/ST (2) RB7/PGD I/O TTL/ST (2) DS30292A-J-page 8 Preliminary 2000 Microchip Technology Inc.

9 RD7/PSP I/O ST/TTL (3) PIC16F87X DIP Pin# PLCC Pin# QFP Pin# I/O/P Type Buffer Type RC0/T1OSO/T1CKI I/O ST RC1/T1OSI/CCP I/O ST RC2/CCP I/O ST RC3/SCK/SCL I/O ST RC4/SDI/SDA I/O ST RC5/SDO I/O ST RC6/TX/CK I/O ST RC7/RX/DT I/O ST RD0/PSP I/O ST/TTL (3) RD1/PSP I/O ST/TTL (3) RD2/PSP I/O ST/TTL (3) RD3/PSP I/O ST/TTL (3) RD4/PSP I/O ST/TTL (3) RD5/PSP I/O ST/TTL (3) RD6/PSP I/O ST/TTL (3) RE0/RD/AN I/O ST/TTL (3) RE1/WR/AN I/O ST/TTL (3) RE2/CS/AN I/O ST/TTL (3) VSS 12,31 13,34 6,29 P VDD 11,32 12,35 7,28 P NC 1,17,28, 40 12,13, 33, Microchip Technology Inc. Preliminary DS30292A-J-page 9

10 NOTES: DS30292A-J-page 10 Preliminary 2000 Microchip Technology Inc.

11 CALL, RETURN RETFIE, RETLW PC<12:0> Stack Level 1 Stack Level 2 13 Stack Level 8 Reset Vector 0000h CALL, RETURN RETFIE, RETLW PC<12:0> 13 On-chip Program Memory Interrupt Vector Page 0 Page h 0005h 07FFh 0800h 0FFFh 1000h Stack Level 1 Stack Level 2 1FFFh Stack Level 8 Reset Vector 0000h On-chip Program Memory Interrupt Vector Page 0 Page 1 Page 2 Page h 0005h 07FFh 0800h 0FFFh 1000h 17FFh 1800h 1FFFh 2000 Microchip Technology Inc. Preliminary DS30292A-J-page 11

12 RP1 RP0 (STATUS<6:5>) = 00 Bank0 = 01 Bank1 = 10 Bank2 = 11 Bank3 DS30292A-J-page 12 Preliminary 2000 Microchip Technology Inc.

13 File Address Indirect addr. (*) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD (1) (1) PORTE PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRESH ADCON0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h Indirect addr. (*) 80h Indirect addr. (*) OPTION_REG PCL STATUS FSR TRISA TRISB TRISC (1) TRISD 81h 82h 83h 84h 85h 86h 87h 88h TMR0 PCL STATUS FSR PORTB (1) TRISE 89h PCLATH INTCON PIE1 PIE2 8Ah 8Bh 8Ch 8Dh PCLATH INTCON EEDATA EEADR PCON 8Eh 8Fh EEDATH EEADRH 90h SSPCON2 91h PR2 SSPADD SSPSTAT 92h 93h 94h 95h 96h 97h TXSTA 98h SPBRG 99h 9Ah 9Bh 9Ch 9Dh ADRESL 9Eh ADCON1 9Fh A0h 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h Indirect addr. (*) OPTION_REG PCL STATUS FSR TRISB PCLATH INTCON EECON1 EECON2 Reserved (2) Reserved (2) h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h 96 70h-7Fh 7Fh Bank 0 Bank 1 80 EFh F0h FFh 16Fh 170h 70h-7Fh 70h - 7Fh 17Fh Bank 2 Bank 3 1EFh 1F0h 1FFh * 2000 Microchip Technology Inc. Preliminary DS30292A-J-page 13

14 File Address Indirect addr. (*) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD (1) (1) PORTE PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRESH ADCON0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h Indirect addr. (*) 80h Indirect addr. (*) OPTION_REG PCL STATUS FSR TRISA TRISB TRISC (1) TRISD 81h 82h 83h 84h 85h 86h 87h 88h TMR0 PCL STATUS FSR PORTB (1) TRISE 89h PCLATH INTCON PIE1 PIE2 8Ah 8Bh 8Ch 8Dh PCLATH INTCON EEDATA EEADR PCON 8Eh 8Fh EEDATH EEADRH 90h SSPCON2 91h PR2 SSPADD SSPSTAT 92h 93h 94h 95h 96h 97h TXSTA 98h SPBRG 99h 9Ah 9Bh 9Ch 9Dh ADRESL 9Eh ADCON1 9Fh A0h 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 120h Indirect addr. (*) OPTION_REG PCL STATUS FSR TRISB PCLATH INTCON EECON1 EECON2 Reserved (2) Reserved (2) 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 1A0h General Purpose Register General Purpose Register 96 Bytes 96 Bytes accesses 20h-7Fh 16Fh 170h accesses A0h - FFh 1EFh 1F0h 7Fh Bank 0 Bank 1 FFh 17Fh Bank 2 Bank 3 1FFh * DS30292A-J-page 14 Preliminary 2000 Microchip Technology Inc.

15 2000 Microchip Technology Inc. Preliminary DS30292A-J-page 15

16 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bank 0 Value on: POR, BOR Value on all other resets (2) 00h (4) INDF h TMR0 xxxx xxxx uuuu uuuu 02h (4) PCL h (4) STATUS IRP RP1 RP0 TO PD Z DC C xxx 000q quuu 04h (4) FSR xxxx xxxx uuuu uuuu 05h PORTA --0x u h PORTB xxxx xxxx uuuu uuuu 07h PORTC xxxx xxxx uuuu uuuu 08h (5) PORTD xxxx xxxx uuuu uuuu 09h (5) PORTE RE2 RE1 RE xxx uuu 0Ah (1,4) PCLATH Bh (4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF x u 0Ch PIR1 PSPIF (3) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF Dh PIR2 (6) EEIF BCLIF CCP2IF -r r Eh TMR1L xxxx xxxx uuuu uuuu 0Fh TMR1H xxxx xxxx uuuu uuuu 10h T1CON T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON uu uuuu 11h TMR h T2CON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS h SSPBUF xxxx xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM h CCPR1L xxxx xxxx uuuu uuuu 16h CCPR1H xxxx xxxx uuuu uuuu 17h CCP1CON CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D x x 19h TXREG Ah RCREG Bh CCPR2L xxxx xxxx uuuu uuuu 1Ch CCPR2H xxxx xxxx uuuu uuuu 1Dh CCP2CON CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M Eh ADRESH xxxx xxxx uuuu uuuu 1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/ DONE ADON x u q DS30292A-J-page 16 Preliminary 2000 Microchip Technology Inc.

17 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bank 1 Value on: POR, BOR Value on all other resets (2) 80h (4) INDF h OPTION_RE G RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS h (4) PCL h (4) STATUS IRP RP1 RP0 TO PD Z DC C xxx 000q quuu 84h (4) FSR xxxx xxxx uuuu uuuu 85h TRISA h TRISB h TRISC h (5) TRISD h (5) TRISE IBF OBF IBOV PSPMODE Ah (1,4) PCLATH Bh (4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF x u 8Ch PIE1 PSPIE (3) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE Dh PIE2 (6) EEIE BCLIE CCP2IE -r r Eh PCON POR BOR qq uu 8Fh 90h 91h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN h PR h SSPADD h SSPSTAT SMP CKE D/A P S R/W UA BF h 96h 97h 98h TXSTA CSRC TX9 TXEN SYNC BRGH TRMT TX9D h SPBRG Ah 9Bh 9Ch 9Dh 9Eh ADRESL xxxx xxxx uuuu uuuu 9Fh ADCON1 ADFM PCFG3 PCFG2 PCFG1 PCFG x u q 2000 Microchip Technology Inc. Preliminary DS30292A-J-page 17

18 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bank 2 Value on: POR, BOR Value on all other resets (2) 100h (4) INDF h TMR0 xxxx xxxx uuuu uuuu 102h (4) PCL h (4) STATUS IRP RP1 RP0 TO PD Z DC C xxx 000q quuu 104h (4) FSR xxxx xxxx uuuu uuuu 105h 106h PORTB xxxx xxxx uuuu uuuu 107h 108h 109h 10Ah (1,4) PCLATH Bh (4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF x u 10Ch EEDATA xxxx xxxx uuuu uuuu 10Dh EEADR xxxx xxxx uuuu uuuu 10Eh EEDATH xxxx xxxx uuuu uuuu 10Fh EEADRH xxxx xxxx uuuu uuuu Bank 3 180h (4) INDF h OPTION_RE G RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS h (4) PCL h (4) STATUS IRP RP1 RP0 TO PD Z DC C xxx 000q quuu 184h (4) FSR xxxx xxxx uuuu uuuu 185h 186h TRISB h 188h 189h 18Ah (1,4) PCLATH Bh (4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF x u 18Ch EECON1 EEPGD WRERR WREN WR RD x--- x000 x--- u000 18Dh EECON Eh Fh x u q DS30292A-J-page 18 Preliminary 2000 Microchip Technology Inc.

19 CLRF STATUS 000u u1uu u BCF BSF SWAPF MOVWF SUBLW SUBWF R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x IRP RP1 RP0 TO PD Z DC C R = bit7 bit0 W = U = - n = bit 7: IRP: 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh) bit 6-5: RP1:RP0: 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) bit 4: TO: 1 = CLRWDT SLEEP 0 = bit 3: PD: 1 = CLRWDT 0 = SLEEP bit 2: Z: 1 = 0 = bit 1: DC: ADDWF ADDLW SUBLW SUBWF 1 = 0 = bit 0: C: ADDWF ADDLW SUBLW SUBWF 1 = 0 = : RRF, RLF 2000 Microchip Technology Inc. Preliminary DS30292A-J-page 19

20 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 R= bit7 bit0 W= U= - n= bit 7: RBPU: 1 = 0 = bit 6: INTEDG: 1 = 0 = bit 5: T0CS: 1 = 0 = bit 4: T0SE: 1 = 0 = bit 3: PSA: 1 = 0 = bit 2-0: PS2:PS0: : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : : : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 DS30292A-J-page 20 Preliminary 2000 Microchip Technology Inc.

21 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE PEIE T0IE INTE RBIE T0IF INTF RBIF R= bit7 bit0 W= U= - n= bit 7: GIE: 1 = 0 = bit 6: PEIE: 1 = 0 = bit 5: T0IE: 1 = 0 = bit 4: INTE: 1 = 0 = bit 3: RBIE: 1 = 0 = bit 2: T0IF: 1 = 0 = bit 1: INTF: 1 = 0 = bit 0: RBIF: 1 = 0 = 2000 Microchip Technology Inc. Preliminary DS30292A-J-page 21

22 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIE (1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE R= bit7 bit0 W= U= - n= bit 7: PSPIE (1) : 1 = 0 = bit 6: ADIE: 1 = 0 = bit 5: RCIE: 1 = 0 = bit 4: TXIE: 1 = 0 = bit 3: SSPIE: 1 = 0 = bit 2: CCP1IE: 1 = 0 = bit 1: TMR2IE: 1 = 0 = bit 0: TMR1IE: 1 = 0 = DS30292A-J-page 22 Preliminary 2000 Microchip Technology Inc.

23 PIC16F87X R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIF (1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF R= bit7 bit0 W= - n= bit 7: PSPIF (1) : 1 = 0 = bit 6: ADIF: 1 = 0 = bit 5: RCIF: 1 = 0 = bit 4: TXIF: 1 = 0 = bit 7: SSPIF: 1 = SPI I 2 C I 2 C. 0 = bit 2: CCP1IF: 1 = 0 = 1 = 0 = bit 1: TMR2IF: 1 = 0 = bit 0: TMR1IF: 1 = 0 = 2000 Microchip Technology Inc. Preliminary DS30292A-J-page 23

24 U-0 R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 (1) EEIE BCLIE CCP2IE R= bit7 bit0 W= U= - n= bit 7: : bit 6: : bit 5: : bit 4: EEIE: 1 = 0 = bit 3: BCLIE: 1 = 0 = bit 2-1: : bit 0: CCP2IE: 1 = 0 = DS30292A-J-page 24 Preliminary 2000 Microchip Technology Inc.

25 . U-0 R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 (1) EEIF BCLIF CCP2IF R= bit7 bit0 W= U= - n= bit 7: : bit 6: : bit 5: : bit 4: EEIF: 1 = 0 = bit 3: BCLIF: 1 = 0 = bit 2-1: : bit 0: CCP2IF: 1 = 0 = 1 = 0 = 2000 Microchip Technology Inc. Preliminary DS30292A-J-page 25

26 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-1 POR BOR R= bit7 bit0 W= U= - n= bit 7-2: : bit 1: POR: 1 = 0 = bit 0: BOR: 1 = 0 = DS30292A-J-page 26 Preliminary 2000 Microchip Technology Inc.

27 CALL RETURN RETLW RETFIE CALL GOTO CALL GOTO CALL GOTO CALL Microchip Technology Inc. Preliminary DS30292A-J-page 27

28 movlw 0x20 ;initialize pointer movwf FSR ; to RAM NEXT clrf INDF ;clear INDF register incf FSR ;inc pointer btfss FSR,4 ;all done? goto NEXT ;NO, clear next CONTINUE : ;YES, continue RP1: RP0 6 from opcode 0 IRP 7 FSR 0 bank select location select bank select location select h 80h 100h 180h (1) 7Fh FFh 17Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 DS30292A-J-page 28 Preliminary 2000 Microchip Technology Inc.

29 BCF STATUS, RP0 ; CLRF PORTA ; ; ; BSF STATUS, RP0 ; MOVLW 0xCF ; ; ; MOVWF TRISA ; <3:0> ; <5:4> ; <7:6> ; WR WR TRIS RD PORT D D CK CK TRIS To A/D Converter WR PORT WR TRIS RD PORT Q Q Q Q RD TRIS Q D EN VDD P N VSS I/O pin (1) TTL D CK Data Latch D CK Q Q Q Q TRIS Latch RD TRIS Q N Vss D EN EN I/O pin(1) TMR0 clock input 2000 Microchip Technology Inc. Preliminary DS30292A-J-page 29

30 Name Bit# Buffer RA0/AN0 bit0 TTL RA1/AN1 bit1 TTL RA2/AN2 bit2 TTL RA3/AN3/VREF bit3 TTL RA4/T0CKI bit4 ST RA5/SS/AN4 bit5 TTL Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets 05h PORTA RA5 RA4 RA3 RA2 RA1 RA0 --0x u h TRISA PORTA Data Direction Register Fh ADCON1 ADFM PCFG3 PCFG2 PCFG1 PCFG x u - DS30292A-J-page 30 Preliminary 2000 Microchip Technology Inc.

31 BCF STATUS, RP0 ; CLRF PORTB ; ; ; BSF STATUS, RP0 ; MOVLW 0xCF ; ; ; MOVWF TRISB ; <3:0> ; <5:4> <7:6> ; RBPU(2) WR Port WR TRIS Data Latch D Q CK TRIS Latch D Q CK TTL VDD P I/O pin(1) RBPU(2) WR Port WR TRIS Set RBIF Data Latch D Q CK TRIS Latch D Q CK RD TRIS RD Port Latch Q D EN VDD P TTL I/O pin(1) ST Q1 RD TRIS RD Port Q D EN RB7:RB4 RB7:RB6 Q D EN RD Port Q3 RB0/INT RD Port 1:. 2: 1:. 2: 2000 Microchip Technology Inc. Preliminary DS30292A-J-page 31

32 Name Bit# Buffer RB0/INT bit0 TTL/ST (1) RB1 bit1 TTL RB2 bit2 TTL RB3/PGM bit3 TTL RB4 bit4 TTL RB5 bit5 TTL RB6/PGC bit6 TTL/ST (2) RB7/PGD bit7 TTL/ST (2) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 86h, 186h TRISB PORTB Data Direction Register h, 181h OPTION_ REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS x u DS30292A-J-page 32 Preliminary 2000 Microchip Technology Inc.

33 BCF STATUS, RP0 ; CLRF PORTC ; ; ; BSF STATUS, RP0 ; MOVLW 0xCF ; ; ; MOVWF TRISC ; <3:0> ; <5:4> ; <7:6> PORT/PERIPHERAL Select(2) Peripheral Data Out Data bus WR PORT WR TRIS Peripheral OE(3) RD PORT Peripheral input D CK Q Q Data Latch D Q CK Q TRIS Latch RD TRIS 0 1 Q D EN VDD P N VSS I/O pin(1) PORT/PERIPHERAL Select(2) Peripheral Data Out Data bus WR PORT WR TRIS D CK Q Q Data Latch D Q CK Q TRIS Latch 0 1 VDD P N VSS I/O pin(1) Peripheral OE(3) SSPl input RD PORT RD TRIS Q D EN 0 1 Schmitt Trigger with SMBus levels CKE SSPSTAT<6> 2000 Microchip Technology Inc. Preliminary DS30292A-J-page 33

34 Name Bit# Buffer Type RC0/T1OSO/T1CKI bit0 ST RC1/T1OSI/CCP2 bit1 ST RC2/CCP1 bit2 ST RC3/SCK/SCL bit3 ST RC4/SDI/SDA bit4 ST RC5/SDO bit5 ST RC6/TX/CK bit6 ST RC7/RX/DT bit7 ST Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu 87h TRISC PORTC Data Direction Register x u DS30292A-J-page 34 Preliminary 2000 Microchip Technology Inc.

35 WR PORT WR TRIS D CK Q Data Latch D CK Q TRIS Latch I/O pin (1) RD TRIS Q D RD PORT EN EN : Name Bit# Buffer Type RD0/PSP0 bit0 ST/TTL (1) RD1/PSP1 bit1 ST/TTL (1) RD2/PSP2 bit2 ST/TTL (1) RD3/PSP3 bit3 ST/TTL (1) RD4/PSP4 bit4 ST/TTL (1) RD5/PSP5 bit5 ST/TTL (1) RD6/PSP6 bit6 ST/TTL (1) RD7/PSP7 bit7 ST/TTL (1) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 08h PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu 88h TRISD PORTD Data Direction Register h TRISE IBF OBF IBOV PSPMODE PORTE Data Direction Bits x u Microchip Technology Inc. Preliminary DS30292A-J-page 35

36 WR PORT WR TRIS RD PORT D CK Q Data Latch D CK Q TRIS Latch RD TRIS Q D EN EN I/O pin (1) : R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 IBF OBF IBOV PSPMODE bit2 bit1 bit0 R= t bit7 bit0 W= U= - n= bit 7 : bit 6: bit 5: bit 4: bit 3: bit 2: bit 1: bit 0: IBF: 1 = 0 = OBF: 1 = 0 = IBOV: 1 = 0 = PSPMODE: 1 = 0 = : Bit2: 1 = 0 = Bit1: 1 = 0 = Bit0: 1 = 0 = DS30292A-J-page 36 Preliminary 2000 Microchip Technology Inc.

37 Name Bit# Buffer Type RE0/RD/AN5 bit0 ST/TTL (1) : RD 1 = 0 = RE1/WR/AN6 bit1 ST/TTL (1) : WR 1 = 0 = RE2/CS/AN7 bit2 ST/TTL (1) : CS 1 = 0 = Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 09h PORTE RE2 RE1 RE xxx uuu 89h TRISE IBF OBF IBOV PSPMODE PORTE Data Direction Bits Fh ADCON1 ADFM PCFG3 PCFG2 PCFG1 PCFG x u Microchip Technology Inc. Preliminary DS30292A-J-page 37

38 w WR PORT RD PORT D Q CK One bit of PORTD Set interrupt flag PSPIF (PIR1<7>) Q D EN EN TTL Read TTL Chip Select TTL Write TTL RDx pin RD CS WR : Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF DS30292A-J-page 38 Preliminary 2000 Microchip Technology Inc.

39 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 08h PORTD : xxxx xxxx uuuu uuuu 09h PORTE RE2 RE1 RE xxx uuu 89h TRISE IBF OBF IBOV PSPMODE PORTE Data Direction Bits Ch PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF Ch PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE Fh ADCON1 ADFM PCFG3 PCFG2 PCFG1 PCFG x u Microchip Technology Inc. Preliminary DS30292A-J-page 39

40 NOTES: DS30292A-J-page 40 Preliminary 2000 Microchip Technology Inc.

41 EECON1 EECON2 EEDATA EEDATH EEADR EEADRH 2000 Microchip Technology Inc. Preliminary DS30292A-J-page 41

42 R/W-x U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD WRERR WREN WR RD R= bit7 bit0 W= S= U= - n= bit 7: EEPGD: 1 = 0 = bit 6:4: : bit 3: bit 2: bit 1: bit 0: WRERR: 1 = 0 = WREN: 1 = 0 = WR: 1 = 0 = RD: 1 = 0 = DS30292A-J-page 42 Preliminary 2000 Microchip Technology Inc.

43 BSF STATUS, RP1 ; BCF STATUS, RP0 ; Bank 2 MOVLW DATA_EE_ADDR ; MOVWF EEADR ; Data Memory Address to read BSF STATUS, RP0 ; Bank 3 BCF EECON1, EEPGD ; Point to DATA memory BSF EECON1, RD ; EEPROM Read BCF STATUS, RP0 ; Bank 2 MOVF EEDATA, W ; W = EEDATA BSF STATUS, RP1 ; BCF STATUS, RP0 ; Bank 2 MOVLW DATA_EE_ADDR ; MOVWF EEADR ; Data Memory Address to write MOVLW DATA_EE_DATA ; MOVWF EEDATA ; Data Memory Value to write BSF STATUS, RP0 ; Bank 3 BCF EECON1, EEPGD ; Point to DATA memory BSF EECON1, WREN ; Enable writes BCF INTCON, GIE ; Disable Interrupts MOVLW 55h ; Required MOVWF EECON2 ; Write 55h Sequence MOVLW AAh ; MOVWF EECON2 ; Write AAh BSF EECON1, WR ; Set WR bit to begin write BSF INTCON, GIE ; Enable Interrupts SLEEP ; Wait for interrupt to signal write complete BCF EECON1, WREN ; Disable writes 2000 Microchip Technology Inc. Preliminary DS30292A-J-page 43

44 BSF EECON1,RD BSF EECON1,RD BSF STATUS, RP1 ; BCF STATUS, RP0 ; Bank 2 MOVLW ADDRH ; MOVWF EEADRH ; MSByte of Program Address to read MOVLW ADDRL ; MOVWF EEADR ; LSByte of Program Address to read BSF STATUS, RP0 ; Bank 3 BSF EECON1, EEPGD ; Point to PROGRAM memory BSF EECON1, RD ; EEPROM Read NOP NOP ; Any instructions here are ignored as program ; memory is read in third cycle after BSF EECON1,RD BCF STATUS, RP0 ; Bank 2 MOVF EEDATA, W ; W = LSByte of Program EEDATA MOVF EEDATH, W ; W = MSByte of Program EEDATA DS30292A-J-page 44 Preliminary 2000 Microchip Technology Inc.

45 BSF EECON1,WR BSF EECON1,WR BSF STATUS, RP1 ; BCF STATUS, RP0 ; Bank 2 MOVLW ADDRH ; MOVWF EEADRH ; MSByte of Program Address to read MOVLW ADDRL ; MOVWF EEADR ; LSByte of Program Address to read MOVLW DATAH ; MOVWF EEDATH ; MS Program Memory Value to write MOVLW DATAL ; MOVWF EEDATA ; LS Program Memory Value to write BSF STATUS, RP0 ; Bank 3 BSF EECON1, EEPGD ; Point to PROGRAM memory BSF EECON1, WREN ; Enable writes BCF INTCON, GIE ; Disable Interrupts MOVLW 55h ; Required MOVWF EECON2 ; Write 55h Sequence MOVLW AAh ; MOVWF EECON2 ; Write AAh BSF EECON1, WR ; Set WR bit to begin write ; ; NOP ; Instructions here are ignored by the microcontroller ; NOP ; Microcontroller will halt operation and wait for ; a write complete. After the write ; the microcontroller continues with 3rd instruction BSF INTCON, GIE ; Enable Interrupts BCF EECON1, WREN ; Disable writes 2000 Microchip Technology Inc. Preliminary DS30292A-J-page 45

46 CP1 CP0 WRT ICSP ICSP 0 0 x Yes No No No Yes No Yes No Yes No No No Yes Yes Yes No Yes No No No Yes No Yes No Yes No No No Yes Yes Yes No Yes No No No Yes No Yes Yes Yes Yes Yes Yes DS30292A-J-page 46 Preliminary 2000 Microchip Technology Inc.

47 - CLRF TMR0 MOVWF TMR0 BSF TMR0 x CLRWDT RA4/T0CKI pin T0SE Fosc/4 0 1 T0CS 3 PS2, PS1, PS0 PSout 1 0 PSA PSout (2 ) Data bus 8 TMR Microchip Technology Inc. Preliminary DS30292A-J-page 47

48 CLKOUT (=Fosc/4) RA4/T0CKI pin 0 M U X M U X SYNC 2 Cycles 8 TMR0 reg T0SE T0CS PSA Set flag bit T0IF on Overflow 0 1 M U X 8 8 PSA 8 - to - 1MUX PS2:PS0 WDT Enable bit 0 1 M U X PSA WDT Time-out T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 01h,101h TMR0 Timer0 module s register xxxx xxxx uuuu uuuu 0Bh,8Bh, 10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF x u 81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS h TRISA PORTA x u - DS30292A-J-page 48 Preliminary 2000 Microchip Technology Inc.

49 - U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON R= bit7 bit0 W= U= - n= bit 7-6: : bit 5-4: T1CKPS1:T1CKPS0: 11 = 1:8 10 = 1:4 01 = 1:2 00 = 1:1 bit 3: T1OSCEN: 1 = 0 = bit 2: T1SYNC: TMR1CS = 1 1 = 0 = bit 1: bit 0: TMR1CS = 0 TMR1CS: 1 = ( 0 = TMR1ON: 1 = 0 = 2000 Microchip Technology Inc. Preliminary DS30292A-J-page 49

50 T1CKI (Default high) T1CKI (Default low) Set flag bit TMR1IF on Overflow TMR1 0 Synchronized clock input TMR1H TMR1L 1 RC0/T1OSO/T1CKI RC1/T1OSI T1OSC T1OSCEN Enable Oscillator(1) Fosc/4 Internal Clock TMR1ON on/off 1 0 T1SYNC Prescaler 1, 2, 4, 8 2 T1CKPS1:T1CKPS0 Synchronize det SLEEP input TMR1CS DS30292A-J-page 50 Preliminary 2000 Microchip Technology Inc.

51 Osc Type Freq C1 C2 LP 32 khz 33 pf 33 pf 100 khz 15 pf 15 pf 200 khz 15 pf 15 pf Crystals Tested: khz Epson C-001R32.768K-A ± 20 PPM 100 khz Epson C KC-P ± 20 PPM 200 khz STD XTL khz ± 20 PPM Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0Bh,8Bh, 10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF x u 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE Eh TMR1L xxxx xxxx uuuu uuuu 0Fh TMR1H xxxx xxxx uuuu uuuu 10h T1CON T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON uu uuuu x u Microchip Technology Inc. Preliminary DS30292A-J-page 51

52 NOTES: DS30292A-J-page 52 Preliminary 2000 Microchip Technology Inc.

53 7.0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit7 TOUTPS 3 TOUTPS 2 TOUTPS 1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit0 R= W= U= 0 - n= bit 7: bit 6-3: TOUTPS3:TOUTPS0: 0000 = 1: = 1: = 1:16 bit 2: TMR2ON: 1 = 0 = bit 1-0: T2CKPS1:T2CKPS0: 00 = 01 = 1x = 2000 Microchip Technology Inc. Preliminary DS30292A-J-page 53

54 Sets flag bit TMR2IF 1:1 to 1:16 4 TMR2 (1) Reset EQ TMR2 reg Comparator PR2 reg 1:1, 1:4, 1:16 2 Fosc/4 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0Bh,8Bh, 10Bh, 18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF x u 0Ch PIR1 PSPIF (1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF Ch PIE1 PSPIE (1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE h TMR2 Timer2 module s register h T2CON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS h PR2 Timer2 Period Register x u - DS30292A-J-page 54 Preliminary 2000 Microchip Technology Inc.

55 PIC16F87X U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CCPxX CCPxY CCPxM3 CCPxM2 CCPxM1 CCPxM0 R = bit7 bit0 W = U = - n = bit 7-6: : bit 5-4: CCPxX:CCPxY: : : PWM : bit 3-0: CCPxM3:CCPxM0: 0000 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 = 1010 = 1011 = 11xx = 2000 Microchip Technology Inc. Preliminary DS30292A-J-page 55

56 . ;Turn CCP module off CLRF CCP1CON MOVLW NEW_CAPT_PS ;Load the W reg with ; the new prescaler ; mode value and CCP ON MOVWF CCP1CON ; value ;Load CCP1CON with this RC2/CCP1 Pin CCP1IF (PIR1<2>) ³ 1, 4, 16 and edge detect Q s CCP1CON<3:0> CCPR1H TMR1H CCPR1L TMR1L DS30292A-J-page 56 Preliminary 2000 Microchip Technology Inc.

57 Q A/D CCP2 RC2/CCP1 Pin TRISC<2> S R Output Logic CCP1CON<3:0> (PIR1<2>) match CCPR1H CCPR1L Comparator TMR1H TMR1L Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0Bh,8Bh, 10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF x u 0Ch PIR1 PSPIF (1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF Ch PIE1 PSPIE (1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE h TRISC PORTC Data Direction Register Eh TMR1L xxxx xxxx uuuu uuuu 0Fh TMR1H xxxx xxxx uuuu uuuu 10h T1CON T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON uu uuuu 15h CCPR1L (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M x u Microchip Technology Inc. Preliminary DS30292A-J-page 57

58 PWM = [(PR2) + 1] 4 TOSC (TMR2 ) [ ] Duty cycle registers CCP1CON<5:4> CCPR1L CCPR1H (Slave) Comparator TMR2 Comparator PR2 (Note 1) Clear Timer, CCP1 pin and latch D.C. R S Q TRISC<2> RC2/CCP1 1: Period Duty Cycle TMR2 = PR2 = Fosc log ( Fpwm ) log (2) bits TMR2 = PR2 TMR2 = Duty Cycle DS30292A-J-page 58 Preliminary 2000 Microchip Technology Inc.

59 PWM 1.22 khz 4.88 khz khz khz khz khz (1, 4, 16) PR2 0xFF 0xFF 0xFF 0x3F 0x1F 0x Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR BOR 0Bh,8Bh, 10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF x u 0Ch PIR1 PSPIF (1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF Ch PIE1 PSPIE (1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE h TRISC h TMR h PR h T2CON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS h CCPR1L (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M x u Microchip Technology Inc. Preliminary DS30292A-J-page 59

60 NOTES: DS30292A-J-page 60 Preliminary 2000 Microchip Technology Inc.

61 +0 Peripheral Interface Inter-Integrated Circuit 2000 Microchip Technology Inc. Preliminary DS30292A-J-page 61

62 R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF R = bit7 bit0 W = U = - n = bit 7: bit 6: bit 5: bit 4: bit 3: bit 2: bit 1: bit 0: SMP: 1 = 0 = : 1= 0= CKE: SPI Mode: CKP = 0 1 = 0 = CKP = 1 1 = 0 = : 1 = 0 = D/A: 1 = 0 = P: 1 = 0 = S: 1 = 0 = R/W: I 2 C : 1 = 0 = : 1 = 0 = UA: 1 = 0 = BF: 1 = 0 = 1 = 0 = DS30292A-J-page Microchip Technology Inc.

63 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 R = bit7 bit0 W = - n = bit 7: WCOL: : 1 = 0 = : 1 = 0 = bit 6: SSPOV: 1 = 0 = 1 = 0 = bit 5: SSPEN: 1 = 0 = 1 = 0 = bit 4: CKP: 1 = 0 = 1 = 0 = bit 3-0: SSPM3:SSPM0: 0000 = FOSC/ = FOSC/ = FOSC/ = TMR2 / = 0101 = 0110 = 0111 = 1000 = FOSC / (4 * (SSPADD+1) ) 1011 = 1110 = 1111 = 1001, 1010, 1100, 1101 = 2000 Microchip Technology Inc. Preliminary DS30292A-J-page 63

64 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN R = bit7 bit0 W = U = - n = bit 7: GCEN: 1 = 0 = bit 6: bit 5: bit 4: bit 3: bit 2: bit 1: ACKSTAT: : 1 = 0 = ACKDT: : 1 = 0 = ACKEN: : 1 = 0 = RCEN: 1 = 0 = PEN: 1 = 0 = RSEN: 1 = 0 = bit 0: SEN: 1 = 0 = DS30292A-J-page Microchip Technology Inc.

65 SDI SDO bit0 SSPBUF reg SSPSR reg SS SCK SS 2 SSPM3:SSPM0 SMP:CKE 4 2 TMR2 2 4, 16, 64 TOSC 2000 Microchip Technology Inc. Preliminary DS30292A-J-page 65

66 BSF STATUS, RP0 ;Specify Bank 1 LOOP BTFSS SSPSTAT, BF ;Has data been ;received ;(transmit ;complete)? GOTO LOOP ;No BCF STATUS, RP0 ;Specify Bank 0 MOVF SSPBUF, W ;W reg = contents ;of SSPBUF MOVW RXDATA ;Save in user RAM F MOVF TXDATA, W ;W reg = contents ; of TXDATA MOVW SSPBUF ;New data to xmit F SPI Master SSPM3:SSPM0 = 00xxb SPI Slave SSPM3:SSPM0 = 010xb SDO SDI (SSPBUF) (SSPBUF) (SSPSR) SDI SDO (SSPSR) MSb LSb MSb LSb SCK SCK 1 2 DS30292A-J-page Microchip Technology Inc.

67 FOSC/4 ( TCY) FOSC/16 ( 4 TCY) FOSC/64 ( 16 TCY) 2 /2 SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) SCK (CKP = 0 CKE = 1) 4 SCK (CKP = 1 CKE = 1) SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 (CKE = 0) SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 (CKE = 1) SDI (SMP = 0) bit7 bit0 (SMP = 0) SDI (SMP = 1) bit7 bit0 (SMP = 1) SSPIF SSPSR to SSPBUF Next Q4 cycle after Q Microchip Technology Inc. Preliminary DS30292A-J-page 67

68 0100 SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) SSPBUF SDO bit7 bit6 bit7 bit0 SDI (SMP = 0) (SMP = 0) bit7 bit7 bit0 SSPIF SSPSR to SSPBUF Next Q4 cycle after Q2 DS30292A-J-page Microchip Technology Inc.

69 SS optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) SSPBUF SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDI (SMP = 0) (SMP = 0) SSPIF SSPSR to SSPBUF bit7 bit0 Next Q4 cycle after Q2 SS not optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SSPBUF SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDI (SMP = 0) (SMP = 0) bit7 bit0 SSPIF SSPSR to SSPBUF Next Q4 cycle after Q Microchip Technology Inc. Preliminary DS30292A-J-page 69

70 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR MCLR, WDT 0Bh, 8Bh, 10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF x u 0Ch PIR1 PSPIF (1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF Ch PIE1 PSPIE (1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE h SSPBUF / xxxx xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM h SSPSTAT SMP CKE D/A P S R/W UA BF x u - DS30292A-J-page Microchip Technology Inc.

71 SCL SDA MSb SSPBUF reg SSPSR reg Match SSPADD reg LSb Addr Match S, P (SSPSTAT reg) SSPADD<6:0> 7 Baud Rate Generator SCL SDA MSb SSPBUF reg SSPSR reg Match SSPADD reg LSb / Addr Match Set/Clear S bit and Clear/Set P bit (SSPSTAT reg) and Set SSPIF 2000 Microchip Technology Inc. Preliminary DS30292A-J-page 71

72 a) b) a) b) c) d) A9 A DS30292A-J-page Microchip Technology Inc.

73 SSPIF BF SSPOV SSPSR SSPBUF ACK 0 0 Yes Yes Yes 1 0 No No Yes 1 1 No No Yes 0 1 Yes No Yes SDA A7 A6 A5 A4 A3 A2 A1 R/W=0 ACK ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 Not ACK D0 SCL S P SSPIF BF (SSPSTAT<0>) SSPOV (SSPCON<6>) SSPBUF ACK 2000 Microchip Technology Inc. Preliminary DS30292A-J-page 73

74 SDA R/W = 1 ACK A7 A6 A5 A4 A3 A2 A1 R/W = 0 Not ACK D7 D6 D5 D4 D3 D2 D1 D0 SCL SSPIF S Data in sampled P BF (SSPSTAT<0>) SSPBUF SSP CKP (SSPCON<4>) SSPBUF (SSPBUF DS30292A-J-page Microchip Technology Inc.

75 Clock is held low until update of SSPADD has tacken place Receive First Byte of Address R/W = 0 Receive Second Byte of Address Receive First Byte of Address R/W=1 SDA A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK A9 A8 SCL S Sr SSPIF (PIR1<3>) Cleared in software Cleared in software BF (SSPSTAT<0>) SSPBUF is written with contents of SSPSR Dummy read of SSPBUF to clear BF flag Dummy read of SSPBUF to clear BF flag UA (SSPSTAT<1>) UA is set indicating that the SSPADD needs to be updated Cleared by hardware when SSPADD is updated. Cleared by hardware when SSPADD is updated. UA is set indicating that SSPADD needs to be updated ACK Master sends NACK Transmit is complete Transmitting Data Byte ACK D7 D6 D5 D4 D3 D2 D1 D P CKP has to be set for clock to be released Cleared in software Bus Master terminates transfer Write of SSPBUF initiates transmit 2000 Microchip Technology Inc. Preliminary DS30292A-J-page 75

76 Clock is held low until update of SSPADD has tacken place Receive First Byte of Address Receive Second Byte of Address R/W = 0 Receive Data Byte R/W = 1 SDA A9 A8 ACK ACK A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 ACK SCL S SSPIF (PIR1<3>) Cleared in software Cleared in software BF (SSPSTAT<0>) SSPBUF is written with contents of SSPSR Dummy read of SSPBUF to clear BF flag Dummy read of SSPBUF to clear BF flag UA (SSPSTAT<1>) UA is set indicating that the SSPADD needs to be updated Cleared by hardware when SSPADD is updated with low byte of address. Cleared by hardware when SSPADD is updated with high byte of address. UA is set indicating that SSPADD needs to be updated Bus Master terminates transfer P Read of SSPBUF clears BF flag DS30292A-J-page Microchip Technology Inc.

77 Address is compared to General Call Address after ACK, set interrupt flag SDA R/W = 0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK SCL SSPIF S BF (SSPSTAT<0>) SSPOV (SSPCON<6>) SSPBUF '0' GCEN (SSPCON2<7>) '1' 2000 Microchip Technology Inc. Preliminary DS30292A-J-page 77

78 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR MCLR, WDT 0Bh, 8Bh, 10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF x u 0Ch PIR1 PSPIF (1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF Ch PIE1 PSPIE (1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE Dh PIR2 (2) EEIF BCLIF CCP2IF -r r Dh PIE2 (2) EEIE BCLIE CCP2IE -r r h SSPBUF xxxx xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN h SSPSTAT SMP CKE D/A P S R/W UA BF x u - DS30292A-J-page Microchip Technology Inc.

79 SSPM3:SSPM0, SSPADD<6:0> SSPBUF SDA SCL SDA in Receive Enable MSb SSPSR LSb,, clock cntl clock arbitrate/wcol detect (hold off clock source) SCL in Bus Collision, Write collision detect Clock Arbitration State counter for end of XMIT/RCV S, P, WCOL (SSPSTAT) / SSPIF, BCLIF ACKSTAT, PEN (SSPCON2) 2000 Microchip Technology Inc. Preliminary DS30292A-J-page 79

80 a) b) c) d) e) f) g) h) DS30292A-J-page Microchip Technology Inc.

81 i) j) k) l) SSPM3:SSPM0 SSPADD<6:0> SSPM3:SSPM0 SCL CLKOUT BRG Down Counter Fosc/4 SDA DX DX-1 SCL SCL de-asserted but slave holds SCL low (clock arbitration) SCL allowed to transition high BRG value BRG reload BRG ( Q2 Q4 ) 03h 02h 01h 00h (hold off) 03h 02h SCL, BRG 2000 Microchip Technology Inc. Preliminary DS30292A-J-page 81

82 SEN SDA = 1, SCL = 1 (SSPSTAT<3>) SSPIF T BRG T BRG SSPBUF SDA 1st Bit T BRG 2nd Bit SCL S T BRG DS30292A-J-page Microchip Technology Inc.

83 SSPEN = 1, SSPCON<3:0> = 1000 Idle Mode SEN (SSPCON2<0> = 1) Bus collision detected, No Set BCLIF, SDA = 1? Release SCL, SCL = 1? Clear SEN Yes Load BRG with SSPADD<6:0> No Yes SCL= 0? No SDA = 0? No BRG Rollover? Yes Yes Reset BRG Force SDA = 0, Load BRG with SSPADD<6:0>, Set S bit. No SCL = 0? No BRG rollover? Yes Yes Reset BRG Force SCL = 0, Start Condition Done, Clear SEN and set SSPIF 2000 Microchip Technology Inc. Preliminary DS30292A-J-page 83

84 Set S (SSPSTAT<3>) SSPCON2 SDA = 1,, SDA = 1, SCL = 1 SCL ) SSPIF T BRG T BRG T BRG SDA End of Xmit 1st Bit SSPBUF T BRG SCL T BRG Sr = DS30292A-J-page Microchip Technology Inc.

85 Start B SSPEN = 1, SSPCON<3:0> = 1000 RSEN = 1 Force SCL = 0 SCL = 0? No Yes, BRG SSPADD<6:0> BRG rollover? No Yes SCL SCL = 1? No ( ) Yes Bus Collision, Set BCLIF, Release SDA, Clear RSEN No SDA = 1? Yes BRG SSPADD<6:0> C A 2000 Microchip Technology Inc. Preliminary DS30292A-J-page 85

86 B C A Yes No No No SCL = 1? SDA = 0? BRG rollover? Yes Yes BRG Force SDA = 0, BRG SSPADD<6:0> No SCL = '0'? No BRG rollover? Yes Yes Reset BRG Force SCL = 0, RSEN SSPIF DS30292A-J-page Microchip Technology Inc.

87 2000 Microchip Technology Inc. Preliminary DS30292A-J-page 87

88 SSPBUF Num_Clocks = 0, BF = 1 Force SCL = 0 Num_Clocks = 8? Yes Force BF i = 0 No BRG SSPADD<6:0> BRG SDA = Current Data bit BRG SSPADD<6:0> BRG BRG rollover? No BRG rollover? No Yes Yes Stop BRG, Force SCL = 1 Force SCL = 1, Stop BRG SCL = 1? No ( ) ( ) SCL = 1? No Yes Yes Read SDA and place into ACKSTAT bit (SSPCON2<6>) SDA = Data bit? Yes No Bus collision detected Set BCLIF, hold prescale off, Clear XMIT enable BRG SSPADD<6:0> BRG SSPADD<6:0> SCL Yes Rollover? No BRG rollover? No SCL = 0? No SDA = Data bit? No Yes Yes Num_Clocks = Num_Clocks + 1 Yes BRG Force SCL = 0, SSPIF DS30292A-J-page Microchip Technology Inc.

89 PIC16F87X SDA Write SSPCON2<0> SEN = 1 START condition begins SEN = 0 Transmit Address to Slave R/W = 0 From slave clear ACKSTAT bit SSPCON2<6> Transmitting Data or Second Half of 10-bit Address A7 A6 A5 A4 A3 A2 A1 ACK = 0 D7 D6 D5 D4 D3 D2 D1 D0 ACK ACKSTAT in SSPCON2 = 1 SSPBUF written with 7 bit address and R/W start transmit SCL SSPIF S cleared in software SCL held low while CPU responds to SSPIF cleared in software service routine From SSP interrupt P Cleared in software BF (SSPSTAT<0>) SSPBUF written SSPBUF is written in software SEN After start condition SEN cleared by hardware. PEN R/W 2000 Microchip Technology Inc. Preliminary DS30292A-J-page 89

90 DS30292A-J-page Microchip Technology Inc.

91 RCEN = 1 Num_Clocks = 0, SDA Force SCL=0, BRG SSPADD<6:0> BRG rollover? No Yes SCL ( ) SCL = 1? No Yes Sample SDA, SSPSR BRG SSPADD<6:0> BRG rollover? No SCL = 0? No Yes Yes Num_Clocks = Num_Clocks + 1 No Num_Clocks = 8? Yes Force SCL = 0, SSPIF BF SSPSR SSPBUF RCEN 2000 Microchip Technology Inc. Preliminary DS30292A-J-page 91

92 SDA Write to SSPCON2<0> (SEN = 1) Begin Start Condition SEN = 0 Write to SSPBUF occurs here Start XMIT Transmit Address to Slave A7 A6 A5 A4 A3 A2 A1 ACK from Slave R/W = 1 Master configured as a receiver by programming SSPCON2<3>, (RCEN = 1) ACK D7 Receiving Data from Slave D6 D5 D4 D3 D2 RCEN cleared automatically D1 D0 Write to SSPCON2<4> to start acknowledge sequence SDA = ACKDT (SSPCON2<5>) = 0 ACK from Master SDA = ACKDT = 0 ACK RCEN = 1 start next receive D7 Receiving Data from Slave D6 D5 D4 D3 D2 Set ACKEN start acknowledge sequence SDA = ACKDT = 1 RCEN cleared automatically D1 D0 ACK PEN bit = 1 written here ACK is not sent SCL SSPIF S Set SSPIF interrupt at end of receive Data shifted in on falling edge of CLK 5 Set SSPIF interrupt at end of acknowledge sequence Set SSPIF at end of receive P SDA = 0, SCL = 1 while CPU responds to SSPIF Cleared in software Cleared in software Cleared in software Cleared in software Cleared in software BF (SSPSTAT<0>) Last bit is shifted into SSPSR and contents are unloaded into SSPBUF SSPOV SSPOV is set because SSPBUF is still full ACKEN Bus Master terminates transfer Set SSPIF interrupt at end of acknowledge sequence Set P bit (SSPSTAT<4>) and SSPIF DS30292A-J-page Microchip Technology Inc.

93 SSPCON2 ACKEN = 1, ACKDT = 0 ACKEN SDA D0 Tbrg ACK Tbrg SCL 8 9 SSPIF SSPIF SSPIF Note: Tbrg= Microchip Technology Inc. Preliminary DS30292A-J-page 93

94 ACKEN Force SCL = 0 BRG rollover? Yes No SCL = 0? No Yes ACKDT (SSPCON2<5>) SDA BRG SSPADD<6:0> Yes Force SCL = 0, SCL = 0? BRG ACKEN, SSPIF No No ACKDT = 1? No BRG rollover? Yes Force SCL = 1 Yes Yes SDA = 1? No No ( ) SCL = 1? Yes Bus collision detected, BCLIF SCL ACKEN BRG SSPADD <6:0> DS30292A-J-page Microchip Technology Inc.

95 SSPCON2 PEN SCL = 1 for T BRG, followed by SDA = 1 for T BRG after SDA sampled high. P bit (SSPSTAT<4>) is set PEN (SSPCON2<2>) SCL T BRG SDA ACK T BRG T BRG P T BRG SCL brought high after T BRG SDA asserted low before rising edge of clock to setup stop condition. : T BRG = 2000 Microchip Technology Inc. Preliminary DS30292A-J-page 95

96 SSPEN = 1, SSPCON<3:0> = 1000 PEN = 1 BRG Force SDA = 0 SCL BRG rollover? No SDA = 0? No Yes SDA, BRG Yes BRG BRG rollover? No BRG rollover? No Yes Yes De-assert SCL, SCL = 1 P bit Set? Yes No Bus Collision detected, BCLIF PEN ( ) SCL = 1? No SDA going from 0 to 1 while SCL = 1 Set SSPIF, Stop Condition done PEN cleared. Yes DS30292A-J-page Microchip Technology Inc.

97 BRG SCL SCL = 1 BRG SSPADD<6:0> BRG SCL, SCL SCL = 1 BRG SCL SCL (T osc 4) SCL SDA T BRG T BRG T BRG 2000 Microchip Technology Inc. Preliminary DS30292A-J-page 97

98 SCL = 0 SDA SDA SDA SCL SDA SCL BCLIF DS30292A-J-page Microchip Technology Inc.

99 a) b) If: then: SDA SEN. BCLIF SDA = 0, SCL = 1 S SSPIF SDA SCL SEN BCLIF S SEN, SDA = 1 SCL=1 START SDA BCLIF SDA = 0, SCL = 1 S SSPIF SEN SSP SSPIF BCLIF SSPIF SSPIF BCLIF 2000 Microchip Technology Inc. Preliminary DS30292A-J-page 99

100 SDA = 0, SCL = 1 SDA T BRG T BRG SCL SEN BCLIF S SSPIF SEN, SDA = 1 SCL = 1 BRG SCL = 0, BCLIF '0' '0' SDA = 0 SCL = 0 Bus, BCLIF '0' '0' SDA = 0, SCL = 1 Set S SSPIF SDA Less than T BRG SDA BRG SDA TBRG SCL SEN BCLIF '0' S SCL pulled low after BRG Timeout SEN, SDA = 1, SCL = 1 S SSPIF SDA = 0, SCL = 1 SSPIF DS30292A-J-page Microchip Technology Inc.

101 a) b) SDA SCL Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL RSEN BCLIF S SSPIF '0' '0' Cleared in software '0' '0' TBRG TBRG SDA SCL BCLIF RSEN SCL goes low before SDA, Set BCLIF. Release SDA and SCL Interrupt cleared in software S SSPIF '0' '0' '0' '0' 2000 Microchip Technology Inc. Preliminary DS30292A-J-page 101

102 a) b) SDA TBRG TBRG TBRG SDA sampled low after TBRG, Set BCLIF SCL SDA asserted low PEN BCLIF P SSPIF '0' '0' '0' '0' TBRG TBRG TBRG SDA SCL Assert SDA SCL goes low before SDA goes high Set BCLIF PEN BCLIF P SSPIF '0' '0' DS30292A-J-page Microchip Technology Inc.

103 R p R s VOL max = 0.4V R p VDD = 5V+10% 3 ma VOL max = 0.4V R p min = ( )/0.003 = 1.7 kω R p VDD VDD R s R p VDD + 10% R p R p DEVICE R s R s SDA SCL : VDD C b = pf 2000 Microchip Technology Inc. Preliminary DS30292A-J-page 103

104 NOTES: DS30292A-J-page Microchip Technology Inc.

105 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN SYNC BRGH TRMT TX9D R = bit7 bit0 W = U = - n = bit 7: CSRC: Don t care 1 = 0 = bit 6: TX9: 1 = 0 = bit 5: TXEN: 1 = 0 = bit 4: SYNC: 1 = 0 = bit 3: : bit 2: BRGH: 1 = 0 = bit 1: TRMT: 1 = 0 = bit 0: TX9D: 2000 Microchip Technology Inc. Preliminary DS30292A-J-page 105

106 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D R = bit7 bit0 W = U = - n = bit 7: SPEN: 1 = 0 = bit 6: RX9: 1 = 0 = bit 5: SREN: Don t care 1 = 0 = bit 4: CREN: 1 = 0 = 1 = 0 = bit 3: ADDEN: 1 = 0 = bit 2: FERR: 1 = 0 = bit 1: OERR: 1 = 0 = bit 0: RX9D: DS30292A-J-page 106 Preliminary 2000 Microchip Technology Inc.

107 FOSC = 16 MHz = 9600 BRGH = 0 SYNC = 0 = Fosc / (64 (X + 1)) 9600 = /(64 (X + 1)) X = = 25 = / (64 (25 + 1)) = 9615 = ( - ) = ( ) / 9600 = 0.16% FOSC/(16(X + 1)) SYNC 0 1 X = value in SPBRG (0 to 255) BRGH = 0 ( ) = FOSC/(64(X+1)) = FOSC/(4(X+1)) BRGH = 1 ( ) = FOSC/(16(X+1)) NA Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 98h TXSTA CSRC TX9 TXEN SYNC BRGH TRMT TX9D h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D x x 99h SPBRG x Microchip Technology Inc. Preliminary DS30292A-J-page 107

108 (K) FOSC = 20 MHz K % SPBRG (decimal) 16 MHz K % SPBRG (decimal) 10 MHz K % SPBRG (decimal) MHz K % SPBRG (decimal) 0.3 NA - - NA - - NA - - NA NA - - NA - - NA - - NA NA - - NA - - NA - - NA NA - - NA NA - - HIGH LOW (K) FOSC = MHz K % SPBRG (decimal) 4 MHz K % SPBRG (decimal) MHz K % SPBRG value (decimal) 1 MHz KBAUD % SPBRG (decimal) khz K % SPBRG (decimal) 0.3 NA - - NA - - NA - - NA NA - - NA - - NA NA - - NA - - NA NA NA NA NA NA - - NA NA NA - - NA NA - - NA - - NA - - NA - - NA - - HIGH LOW (K) FOSC = 20 MHz K % 16 MHz SPBRG (decimal) K % 10 MHz SPBRG (decimal) K % SPBRG MHz (decimal) K % SPBRG (decimal) 0.3 NA - - NA - - NA - - NA NA NA - - NA - - NA NA - - NA - - NA NA - - NA - - NA - - NA - - HIGH LOW (K) FOSC = MHz K % SPBRG (decimal) 4 MHz K % SPBRG (decimal) MHz K % SPBRG (decimal) 1 MHz K % SPBRG (decimal) khz K % SPBRG (decimal) NA NA NA NA - - NA NA NA - - NA NA - - NA - - NA - - NA NA - - NA - - NA - - NA - - NA NA - - NA - - NA - - NA - - NA NA - - NA - - NA - - NA - - NA - - HIGH LOW DS30292A-J-page 108 Preliminary 2000 Microchip Technology Inc.