. ( ) IC (Programmable Logic Device, PLD) VHDL 2. IC PLD 2.. PLD PLD PLD SIC PLD PLD CPLD(Complex PLD) FPG(Field Programmable Gate rray) 2.2. PLD PLD PLD I/O I/O : PLD D PLD Cp D / Q
3. VHDL 3.. HDL (Hardware Description Language, HDL) HDL SIC(pplication Specified Integrated Circuit ) FPG CPLD 2 HDL : HDL HDL 2 3 4 ( ) HDL ( ) X Y S C library IEEE; use IEEE.std_logic_64.all; entity HLFDD is port ( X, Y : in std_logic; S, C : out std_logic ); end HLFDD; architecture DTFLOW of HLFDD is signal T, T : std_logic begin T <= X or Y; T <= X nand Y; S <= T and T; C <= not T; end DTFLOW ( ) X Y S C 2: HDL () 2
3.2. HDL HDL VHDL Verilog-HDL VHDL 3.3. VHDL VHDL ( ) () (RTL Register Transfer Level ) 4. Windows LTER Quartus II (Quartus II ) ltera DE DE VHDL and or VHDL Verilog-HDL VHDL ( ) 2 4 FPG 3 ( ) 5 UP 3: 3
5. 5.. 3 DE ( ) MX+PLUS II UP- 2 4 4 4 (4 ) UP- 2 3 7 LED 8P 2 - UP- 3 3 2 2 CI F3 C3 F2 C2 F C F CO S 2 3 2 2 2 2 3 S 2 S S 4: 4 Quartus II DE 5.2. (i) ( 2) 2(a) / 2(b) L/H 2 S = X Y CI + X Y CI + X Y CI + X Y CI = (X Y + X Y ) CI +(X Y + X Y ) CI = (X Y ) CI +(X Y ) CI = (X Y ) CI CO = X Y CI + X Y CI + X Y CI + X Y CI = X Y (CI + CI)+(X Y + X Y ) CI = X Y +(X Y ) CI ( + ) 4
2: (a) / ( ) X Y CI S CO (b) L/H X Y CI S CO L L L L L H L L H L L H L H L H H L L H L L H H L H L H L H L H H L H H H H H H 2 VHDL ( ) -- ( ) library IEEE; use IEEE.std logic 64.all; entity FULLDDER is port(,, CI : in std_logic; S, CO : out std_logic ); end FULLDDER; architecture DTFLOW of FULLDDER is begin S <= ( xor ) xor CI; CO <= ( and ) or ( ( xor ) and CI); end DTFLOW; ( -- ) 5
(ii) Quartus II ( ) Quartus II Quartus II ( ) windows 2 Quartus II ( Quartus II P4) Quartus II ( ) Quartus II Quartus II 9. 3 ( Quartus II P5 P) Quartus II ( P6) fulladder ( P7)Next ( P8) Family: Cyclone III vailable devices: EP3C6F484C6 Next ( P9)Next 4 (HDL )( Quartus II P P2) VHDL ( ) ( ) fulladder.vhd 5 ( Quartus II P3 P5) ( ) (and or ) 6 ( Quartus II P6 P8) ( ) DE FPG FPG Quartus II 3 7 ( Quartus II P9 P27 P32 P33) Quartus II ( ) Grid Size 2ns End Time 2ns 6
3: X J6 SW Y H5 SW CI H6 SW2 S J LED CO J2 LED 8 DE ( Quartus II P28-P3) Quartus II DE () LED ( ) Quartus II 28 7
5.3. 4 4 4 2 -- ( ) 4 library IEEE; use IEEE.std_logic_64.all; entity FULLDDER4 is port(,, 2, 3 : in std_logic;,, 2, 3 : in std_logic; CI : in std_logic; S, S, S2, S3 : out std_logic; CO : out std_logic ); end FULLDDER4; architecture STRUCTURE of FULLDDER4 is component FULLDDER port(,, CI : in std_logic; S, CO : out std_logic ); end component; signal C, C2, C3 : std_logic; begin F : FULLDDER port map (,, CI, S, C ); -- F : 3 F2 : F3 : end STRUCTURE; 8
(i) 4 Quartus II DE FULLDDER4 2 Quartus II P6 Next 3 Quartus II P6 fulladder,vhd ( dd ll ) 4 2 F, F2, F3 F F F3 5 F F3 5 2 9 + 5 (CO = ) 4 9
5.4. 7 LED 2-2 - DE 7 LED( ) 4 4 2 9 DE LED / LED 4 LED 7 LED 4... (i) 4 OFF ON 7 LED OFF ON 4: ON/OFF 7 LED I3 I2 I I a b c d e f g OFF OFF OFF OFF ON ON ON ON ON ON OFF OFF OFF OFF ON OFF ON ON OFF OFF OFF OFF OFF OFF ON OFF ON ON OFF ON ON OFF ON OFF OFF ON ON ON ON ON ON OFF OFF ON OFF ON OFF OFF OFF ON ON OFF OFF ON ON OFF ON OFF ON ON OFF ON ON OFF ON ON OFF ON ON OFF ON OFF ON ON ON ON ON OFF ON ON ON ON ON ON OFF OFF OFF OFF ON OFF OFF OFF ON ON ON ON ON ON ON ON OFF OFF ON ON ON ON ON OFF ON ON (ii) 4 DE 7 LED OFF = ON = a VHDL a = I I I2 I3+I I I2 I3 ( ) a<=(not I and I and I2 and I3) or (I and I and not I2 and I3) ( VHDL ) b g ( ) (iii) VHDL 2 - Quartus II 5
a I J6 SW I H5 SW f g b I2 H6 SW2 I3 G4 SW3 a E 7 LED HEX D e c b F 7 LED HEX D c H2 7 LED HEX D2 d H3 7 LED HEX D3 d Decimal Point e G2 7 LED HEX D4 f F2 7 LED HEX D5 g F3 7 LED HEX D6 5: 7 LED 2 - ( ) ( = entity = ) (7segment ) (iv) I I3 (v) UP- b c 2 -
6. ( ) ii. 2 2 ( ) ( ) Quartus II 4 4 7 LED 7 LED... ( ) ( ) [] [2] VHDL Primer Jayaram hasker [3] [4] 2