ATLAS 2011/3/25-26
2 LHC (Large Hadron Collider)/ATLAS LHC - CERN - s=7 TeV ATLAS - LHC 1 Higgs 44 m 44m 22m 7000t 22 m
3 SCT( ) SCT(SemiConductor Tracker) - - 100 fb -1 SCT
3 SCT( ) R eta=1.0 eta=1.5 R 1080 TRT ( Barrel ) TRT ( Endcap ) eta=2.0 R 559 R 514 R 299 R 122.5 R 50.5 SCT ( Barrel ) SCT ( Endcap ) PIXEL p-beam 0 0 Interaction Point SCT(SemiConductor Tracker) - - 100 fb -1 SCT beam line Z eta=2.5
4 SCTモジュール 1280 strips /18 新型SCTモジュール 現行SCTモジュール 24.5 mm 128 mm Readout Chips Readout Chips 768 strips 放射線耐性の向上 ストリップの長さ 現行 新型 # channels/chip 128 128 strip length 128 mm 24.5 mm # modules 4088 7000 今回 新型SCTの為に開発された読み出しチップ(ABCNチップ) の性能評価テスト用のDAQシステムを開発した
5 4 SCT (ABCN320 ) 4 modules test - 1 48kByte 38 I/O DAQ
6 ABCN ABCN (bit pattern) ABCN PC ABCN
6 ABCN ABCN (bit pattern) ABCN Write Register... 0010 000 000 1111111 1011 1000 1110 101 PC ABCN
6 ABCN ABCN (bit pattern) ABCN Data Taking Mode... 101 1111111 1011 0000 1110 101 Write Register... 0010 000 000 1111111 1011 1000 1110 101 PC ABCN
6 ABCN ABCN (bit pattern) ABCN Data Taking Mode... 101 1111111 1011 0000 1110 101 bit pattern Write Register... 0010 000 000 1111111 1011 1000 1110 101 PC ABCN
6 ABCN ABCN (bit pattern) ABCN Data Taking Mode bit... 101 1111111 1011 pattern 0000 1110 101 Write Register... 0010 000 000 1111111 1011 1000 1110 101 PC DAQ Hardware FPGA ABCN DAQ FPGA
7 DAQ SEABAS DAQ SEABAS - 162kByte RAMFPGA(>48kByte) - 120 I/O (>38 ) 4 module - PC TCP/IP95Mbps SEABAS PC 95 Mbps Internet ABCN
8 ABCN SEABAS FPGA - Verilog-HDL SEABAS PC - C/C++ DAQ DAQ Software PC 95 Mbps SEABAS FPGA Internet ABCN
PC SEABAS ABCN 9
PC SEABAS ABCN 9 TCP Connection
PC SEABAS ABCN 9 TCP Connection (Configuration) Write Register (Configuration)
PC SEABAS ABCN 9 TCP Connection (Configuration) Write Register DAQ (Configuration) DAQ
PC SEABAS ABCN 9 TCP Connection (Configuration) Write Register DAQ DAQ (Configuration) Trigger Data Data Data FIFO Data
PC SEABAS ABCN 9 TCP Connection (Configuration) Write Register DAQ DAQ (Configuration) Trigger Loop Data Data Data FIFO Data TCP Disconnection
10 DAQ(1) 1 ABCN Calibration - Calibration3, 7, 11, 15,... - Issue Calibration Pulse Trigger 100 100 # hit channel
11 DAQ(2) ABCN20 - ABCN 20 Data - 2 FIFO 2N 20 ABCN
Noise[e] Gain[mV/fC] 12 Gain[mV/fC] 100 chip0 chip1 chip2 chip3 chip4 chip5 chip6 chip7 chip8 chip9 Gain : ~100mV/fC 0 [e] channel Noise : ~ 400 e 400 0 channel
Noise[e] Gain[mV/fC] 12 Gain[mV/fC] 100 chip0 chip1 chip2 chip3 chip4 chip5 chip6 chip7 chip8 chip9 Gain : ~100mV/fC ABCN 0 [e] channel 20 ABCN Noise : ~ 400 e 400 0 channel
13 (1) 1. 2. SEABAS NIM
14 (2) 2.4 cm chip : 0 1 2 3 4 -
15 - [e] C [pf] Noise[e]=a+b C [pf] chip 0 10.3 chip 1 10.3 chip 2 7.7 chip 3 5.1 chip 4 2.6 Noise[e] a : 366.8±4.6 b : 83.5±0.8 a : 370 b : 76.7 fit reference C[pF]
15 - [e] C [pf] Noise[e]=a+b C a b [pf] chip 0 10.3 chip 1 10.3 chip 2 7.7 chip 3 5.1 chip 4 2.6 Noise[e] a : 366.8±4.6 b : 83.5±0.8 a : 370 b : 76.7 fit reference C[pF]
16 chip : 0 1 2 3 4 3
16 1 32 cm 3 2 chip : 0 1 2 3 4 3
- 360-1 328 98.5±0.7% >99% 17
18 DAQ - SEABAS FPGA 120 I/O 4-20 ABCN 2N 4 DAQ fin
backup
20 ABCN ABCN - ABCN bit stream( ) Write register, Data Taking, Trigger etc... 1. PC ABCNSEABAS SEABAS 2. PC SEABAS ABCN DAQ
21 chip : 0 1 2 3 4 channel chip0 chip1 chip2 chip3 chip4
22 259 I 98 78 15 7 chip : 0 1 2 3 4 chip0 chip1 chip2 chip3 chip4 chip3 I N I = (98/78) (15+7) ~ 27 N I 98.5±0.7
Calibration - Calibration Pulse delay 0 ns~63 ns - delay delay Calibration Pulse Signal Clock 40MHz sample 25 ns
Calibration - Calibration Pulse delay 0 ns~63 ns - delay DAQ delay delay[ns] Calibration Pulse Signal Clock 40MHz sample 25 ns channel
DAQ delay[ns] Calibration - Calibration Pulse delay 0 ns~63 ns - delay DAQ delay channel delay[ns] Calibration Pulse Signal Clock 40MHz sample 25 ns channel
σ[mv] Noise(=σ/Gain)[ENC] DAQ 24 Noise[ENC] 400 Noise : ~ 400 e 0 DAQ channel Noise[ENC] Noise : ~ 400 e 400 0 channel
Vt50[mV] Gain(=Vt50/Pulse charge)[mv/fc] DAQ 25 Gain[mV/fC] 100 Gain : ~ 100mV/fC DAQ channel Gain[mV/fC] 100 Gain : ~100mV/fC 0 channel
26 SEABAS SEABAS(Soipix EvAluation BoArd with Sitcp) - SiTCP(network processor), ADC, DAC, NIM, FPGA - 4 ~230mm PROM NIM I/O User FPGA Ethernet ADC DAC DIP SW LED SiTCP FPGA Power
Burst - (0 mv) - Trigger 100 0 chip 0 chip 1 chip 3 chip 4 chip 5 27 1280 channel
Cal. delay - Strobe delay scan Chip efficiency/ - Efficiency50% delay1/4 delay cal. delay efficiency Strobe delay scan, efficiency, chip address:0 1.2 1 Strobedelay1Dhist_0 Entries 344258 Mean 12.36 RMS 3.903 0.8 0.6 1/4 0.4 0.2 0 0 10 20 30 40 50 60 delay Cal. delay 28
IntL~ 100fb -1 LHC HL LHC integrated luminosity[fb -1 ] 700 3000 luminosity[s -1 cm -2 ] 10-34 5 10-34 events/crossing 30 150 29
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