PTM - 152 -
- 153-1900 (MR) MRAM AMR 1960 1970 1980 1990 GMR TMR ( 75) MR MRAM ( 72) GMR ( 88) GMR (IBM, 91) (IBM, 9 ) GMR MRAM (IBM, 95) GMR MRAM ( 93) DARPA ( 96 02) GMR MRAM (Honeywell, 99) TMR MRAM (IBM,Motorola, 99) GMR (IBM, 97) MR18%TMR ( 94) 1900 (MR) MRAM AMR 1960 1970 1980 1990 GMR TMR ( 75) MR MRAM ( 72) GMR ( 88) GMR (IBM, 91) (IBM, 9 ) GMR MRAM (IBM, 95) GMR MRAM ( 93) DARPA ( 96 02) GMR MRAM (Honeywell, 99) TMR MRAM (IBM,Motorola, 99) GMR (IBM, 97) MR18%TMR ( 94) Magnetic-Tunnel-Junction
GMR:Giant Magneto-Resistance TMR:Tunneling Magneto-Resistance GMR-MRAM TMR-MRAM MR GMR=% TMR= % = = K X Y N X Y SNR SN=SNR( )/N GMR TMR - 154 -
- 155 -
Free-layer Element He HBL H HBL - 156 -
TMR 2~3 I DL DL I BL BL WL (n+) MRAM WRITE READ MRAM - 157 -
- 158 -
1M / Wh 100 10 1 0.1 NAND DRAM FeRAM eptm SRAM emram esram NOR-FLASH 10us 100us 1ms 10ms 100ms 1s 10s 1M / - 159 -
Reference Voltage Generator 64 Column Select (4th Cu layer) 256Kb Lines(CSL) 256Kb 256Kb 128 Main Word Lines(MWL) (3rd Cu layer) 256Kb 64Kb 64Kb Col. I/O Dec. Col. I/O Dec. Redundancy Fuse Elements Center Control Circuit MRAM 16M bit Memory Array Row/Col. Decoder 16M bit Memory Array µ - 160 -
BL0 (2nd Cu) LI TV MTJ V2 WWL0 WWL1 (1st Cu) V1 WL0 WL1 WL2 WL3 n+ n+ Iso- n+ n+ Iso - n+ (SL) lation (SL) lation Psub WWL : Write Word Line n+ diffusion/co-salicide WL : Read Word Line SL : Source Line MRAM WWL0 WWL1 MTJ LI MC0 V1/V2 BL0 BL1 BL2 MC1 WL0 WL1 WL2 WL3 n+/cosi n+/cosi (SL) (SL) MRAM - 161 -
Dummy Cell S.A. MTJ WL SL n+ diffusion Cell Array RBL BL1 BL0 a b - 162 -
µ MTJ BL MTJ WWL MRAM - 163 -
Normal Cell Area Reference Cell Area CSL PCG Pre-charge Bus Swap (to Vpre ) Switch RDB<0> /RDB<0> S.A. Dout 0 RDB<1> /RDB<1> S.A. Dout 1 RDB: Read Data Bus Dout 3 255 BL Current Source/Sink 0 Vcc=1.2V WL0 MTJ SL(n+/CoSi) WWL0 WL1 Dummy WL0 MTJ (0) (1) (1) (0) BL3 BL2 BL1 BL0 255 BL Current Source/Sink 0 SL(n+/CoSi) 0 0 WL Driver WWL Current Source 256 Dummy WWL 513 Dummy WL1-164 -
Dout Amp /Sout Sout /SE Vref Vref SE /RDB RDB or RDB or /RDB Sub array size (32K) (64K) (96k) (128k) 11 Conventional Read Error 10 (dummy Column) 9 FSCW 8 (dummy Row) 7 6 5 4 This work 3 2 32 64 128 256 384 512 Length of n+/cosi Source Line [Number of Cells connecting SL] Sense Access Time (tsa) [ns] - 165 -
Bit Line Pre-charge Data Bus and WL activation Sense Equalize 1.2V WL CSL PCG Sout 0.6V /Sout BL Dout tc=7.0ns tra=5.1ns 0V 10ns 12ns 14ns 16ns 18ns - 166 -
Reference Voltage Generator tc(write) : Vcc=1.2V MWL BLVref CSL?PL Iref? NR BLVref < Vcc?PL p1 p2?pr Write Write BL I (WWL) Timing Timing Gen.? NL? NR Gen. I (BL) CSL n1 n2 CSL WDT Memory Switching /WDT Array magnetization - 167 -
Row Decoder Technology 0.13 um CMOS, 4Level Cu technology n+ diffusion source with Co-salicide Cell size 1.14 x 0.72 = 0.81 um 2 TMR size 0.26 x 0.48 um 2 Chip Size 1.40 x 2.77 = 3.88 mm 2 Supply Voltage 1.2V only Organization 64K word x 16 bit Operating Frequency 100MHz (no-wait) / 143MHz(1-wait) (read/write) Pd 60mW (100MHz write cycle) Col. Dec. Col. Dec. VREF Generator - 168 -
NEC - 169 -
- 170 -
/SE 2 3 1 Vref RD Select Gate Bit Lines Word Lines + - Offset Amp. Dout Source Line - 171 -
CLK 1 2 3 RD WT S.G. SE Bit-line RD Dout1-172 -
- 173 -
RD Memory Cell Select Gate Bit Lines Word Lines µ Source Line - 174 -
µ µ - 175 -
- 176 -
57 05-2P-032004-177 -