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2 謝辞本報告で出等の表示のない部分の資料は筆者が東芝在籍中に外部発表で使用した資料に基づいて再構成し作成したものです関係する方々に感謝の意を表します中川コンサルティング事務所

4 Application fields of Power Devices

5 Evolution of high power devices in Toshiba Three waves in device development Power rating (VA) 100M 10M 1M 100K 10K A2500V 150A1000V 80A400V 1970 SCR 2 nd wave 200A600V 3000A4000V BTr BTr 1500A2500V 600A2500V 40A400V 400A300V 100A600V 1980 Year 200A900V LTT 3000A4000V 2500A6000V 3500A8000V GTO 300A450V 3000A4500V 400A1000V 25A1000V 2500A6000V 1000A2500V 600A1200V 300A1000V 200A500V 1990 IGBT 6000A6000V 1200A3300V 360A1700V 3 rd wave 750A4500V 1500A3300V 1200A1700V 2000 Press Pack IGBT 1500A4500V

6 IGBT Family Power Module IPM TM-IPM One Chip Inverter ICs Press Pack IGBT

7 CEATEC 2007 資料 GTOを置き換えたIGBT(IEGT) JR 東海 300 系 (1990) JR 東海西日本 700 系 (1999,2002) SG3000GXH24 ST1000EX21 MG1200FXF1US53 GTO IGBT IEGT Oct 2007 TOSHIBA semiconductor 5

11 I ATO = G max I g V J 1 ρ SPB R b

12 200A I ATO 100A V J 1 ρ SPB

13 1978 SSDM

14 GTO V 1

15 ISPSD 1992

17 1970

18 UMASS!!!!! 2 TONADDE GTO IEDM

19 1982 IEDM

20 Baliga!!! 10μsec

21 1980 MOS MOS

22 BiMOS 1980 Hans Becke 1982 Baliga IEDM 1983 J.P. Russel EDL GE RCA IGR IGT COMFET GEMFET Bipolar-mode MOSFET +

23 1983 MOS Tr 1 BTr 1400V NPN + PNP = NMOS + PNP = IGBT!!! IGBT!!! --- BTr!!!

24 !!!

25 Non-Latch-Up IGBT Non-Latch-up IGBT!!!

26 V C I C > 300kW/cm 2

27 Tr 2 V A J C 1 2 v ε E s s 2 c 200 kw cm 2

28 1 N P + N +

29 P + N!!! P +

30 2

33 RCA 1983 IEDM!!!!!!!!!

34 Latch up current level V G =20V V G =15V

35 Non-Latch Latch-Up IGBT Hole Bypass!!!

36 1000 A/cm (V)

37 !!!

38 500V25A V25A 6.5mm

40 V IGBT!! Epi OH

41 IGBT!!! 1700V IGBT

42 Reduction of chip size (Fine patterning & Trench technology) Improvement in Vce(sat) Reduction of Power dissipation Large RBSOA Soft turn-off Improved temperature dependency 3rd Gen. 2nd Gen. Trench Gate FS-IGBT PT-IGBT NPT Tech.

44 PT-IGBT NPT-IGBT Very thin wafer FS-IGBT

45 PTIGBT PT-IGBT NPT-IGBT FS-IGBT p-emitter high efficiency low efficiency low efficiency n-drift thin medium thin n-buffer highly doped none lightly doped thin lifetime low high high

46 Temperature dependence of trade-off relation

47 Punch through & Low efficiency emitter Thin wafer technology p+ n + 2 μ m p-base 55 μ m n-drift Trench Gate New n-buffer Low efficiency p-emitter

49 @ 150 A/cm2 Carrier distribution (/cm 3 ) surface Hole 58 μm thick PT-trench IGBT Electron Depth (μm) Hole Electron PT-trench IGBT Lifetime 58 μm thick PT-TIGBT => 10 μsec conventional PT-TIGBT => 0.1 μsec

51 J p = qd p p x

52 kV IEGT kV IGBT kV IGBT IEGT)

55 Trench-IGBT IEGT Planar-IGBT

59 E c / ) ( ) ( cm W E v JV V E v N qv J W E V v J qn W E W E C s C s D s C s D C = = + = = = = ε ε ε W a b c d e

60 J= (εv s E c2 ) 2V + qv s N D JV (εv s E c2 )/2 2x10 5 W/cm 2

63 J p =J C J ch =0 Depletion layer p-emitter = ND + J C qv s V BD = EG 60( ) ( N D + J 10 C 16 / qv s ) 3/ 4

65 9x10 5 W/cm 2

68 p-emitter J ch Depletion layer J p =J C -J ch 4 3/ ) 10 / 2 / ( ) ( 2 N N D D + = + = + = s ch s C D G BD s ch s C ns ch ps ch C qv J qv J N E V qv J qv J qv J qv J J

69 γ γ if γ < + γ γ = = γ = p-base Electric field n-buffer Electric field Carrier density

70 Q = qn D + J*(γ/v h + (γ -1)/v e ) qn D 0 p-base n-buff J C J C V BD

71 2.0E+05 V CC =600V 1E+17 Electric Field (V/cm) 1.5E E E+04 Electron Hole Electric Field 1800A/cm E+16 1E+15 1E+14 Carrier Concentration (cm -3 ) P-base N-buffer 0.0E Distance (μm) 1E+13 Q/q = N D + (γ/v h + (γ -1)/v e )J/q

72 2.0E+05 V CC =600V 1E+17 Electric Field (V/cm) 1.5E E E E+00 Electron Hole Electric Field 1800A/cm Distance (μm) 1E+16 1E+15 1E+14 1E+13 Carrier Concentration (cm -3 ) 1.5 e5 1.0 e5 0.5 e5 0.0 e0 1800A/cm Distance (μm)

73 γ J C =qn D /((1- γ)/v e - γ/v h ) ; = = + γ γ=0.47 J=J c p-base n-buff

74 Current Density 2000 TCAD Analytical On-state Voltage

75 γ

77 Where silicon limit of IGBTs exist? Forward voltage can be greatly improved by reducing mesa width. 600V IGBT nm 200nm Mesa width 40nm 0.5μm 2.2μm Current Density (A/cm 2 ) Conv Forward Voltage (V)

78 Analytical I-V curve for ideal silicon limit IGBT 2kT 1 QJ JW i V F = ln[ {( + b) exp( ) b}] + q n qd 2qa i pe R ch J μ > μ electron hole If all current flows by electron, this gives the lowest forward voltage! The silicon limit I-V relation can be derived based on the assumption: n W (1) No hole current flow. J J p n = qd p + nμ pe x (2) All current flows by electrons. = J = 2 n qd n n x = 0 Emitter n pb Gate W i n n 1 nbuff L e p Collector

79 Practical Limit Assumption (1)Flat carrier profile in the n-base (2)All current flows by drift V F kt = ln q qd pe μ n 2 i n QJ (μ n + μ p ) + W i qμ n (μ D n pe + J μ p )Q + n n L e μ μ n n R + ch μ p J Emitter n p b Gate n n buff p Collector

80 Predicted I-V of Ideal and Practical IGBT Limit 600V IGBT Current Density [A/cm 2 ] Ideal Limit Practical Limit Forward Voltage [V]Conv. IGBT

81 Comparison of two IGBT limits and TCAD results 600V IGBT Mesa width=40nm 0.2μm Current Density [A/cm 2 ] Ideal Limit 0.5μm 2.2μm Practical Limit Forward Voltage [V]Conv. IGBT

82 Theoretical limit of IGBT IGBTs can still be greatly improved in future R on A(mΩcm 2 ) Si IGBT Si SJ -MOS SiC MOS GaN HEMT Si Limit SiC Limit SJ- Breakdown Voltage (V) SJ MOS GaN Limit Si IGBT Si IGBT Practical Limit Ideal IGBT Limit

83 Data from Fuji Electric

84 Trends of 600V IGBT IGBT On-resistance has been steadily improved In the past, It is predicted that it will approach the practical limit in the future. R on A(mΩcm 2 ) IGBT IGBT Practical Limit

86 Trends of Voltage Regulator Module 1999

87 P loss =(I loss =(I 2 d 2 x d R on ) on ) + (I (I x Q gd /i gd /i g x g V in x in f) f) + (Q (Q g x g V g x g f) f) + (Q (Q oss /3 oss /3x V in x in f) f) Control MOSFET D S L FOM=R on Q gd G Vcc G D S C P loss =(I loss =(I 2 d 2 x d R on ) on ) + (Q (Q g x g V g x g f) f) + (Q (Q oss /3 oss /3x V in x in f) f) Synchronous MOSFET FOM=R on A

88 Evolution of 60V Power MOSFET π -MOS I π -MOS II BV DSS =60V type π -MOS III π -MOS IV π -MOS V U-MOS (I) U-MOS (II) (U-MOS:Trench Gate) U-MOS (III)

89 Trend of High Speed MOSFET Figure of Merit: R on Q gd V G =4.5V, V DD =24V UMOS II High Speed UMOS III Ultra-High Speed UMOS IV Ultra-High Speed UMOS V UMOS VI UMOS VII UMOS VIII

90 Influence of parasitic inductances Vin Parasitic inductances in the power stage circuit greatly influence the converter efficiency. Q1 LHD Driver Circuit Lx Q2 LHS L LD L LS SBD Vout 4 parasitic inductances are examined, using circuit simulator. Conversion Efficiency (%) Low Side drain High Side Source L LD Low Side Source L LS High Side Drain L HD L HS Inductance (nh)

91 L HS =0.44nH L HS =1.24nH Id Id Vds Vgs Vds Vgs

92 V in Driver output L HD Driver L HS Actual Gate-Source voltage Voltage drop in parasitic inductance (L HS )

93 Influence of parasitic inductances There is an optimum inductance value that minimizes the total power loss. Total power loss (MOSFET + driver) Vin:12V, Vg:5V,Iout:20A,fsw:1MHz Impedance of gate driver circuits 3.7Ω 2.2Ω 0.4Ω Total Parasitic Inductance L S (nh)

94 Why there is optimum inductance value? Power loss (W) High side MOSFET turn-off loss High side MOSFET turn-on loss Total inductance L S (nh) Turn-on waveforms Drain voltage Drain Current

95 Calculated waveforms of High side MOSFET Power consumption (W) Power consumption (W) Large power loss occurs during turnon period Id Vg Vds Id Vg Vds Ls=2 nh Ls=0.1 nh

96 HS-MOS Top view Driver IC Bottom view Driver High side IC MOSFET LS-MOS Low side MOSFET Discrete MCM Driver

97 t f = (Q (I str D ) )

98 Conventional Switching Theoretical limit: plateau t f = Q I str D Mirror period = Q I gd G V G V D I D P R loss on I = 2 D R + on I D Q str + V V A f Q gd AI D IG Major loss 2 f Q str 1 3 V I A 2 D f V A f

99 Ideal MOSFET Switching New FOM = R on Q str Theoretical limit: t f t f = Q I str D Mirror period = Q I gd G V G V D I D P = loss R on = I R 2 D on I + 2 D V Q str A V I A D f Q I gd G 2 f Q str R on Q str New FOM V A 1 3 I f 2 D V A f

100 Ideal MOSFET Switching Theoretical limit: t f t f = Q I str D Mirror period = Q I gd G V G V D I D P R loss on I = 2 D R + on I D Q + V V A f I D Q I 2 gd G f Q Low Impedance str A gate drive is a key technology A to supply a large gate current to eliminate mirror period. str 1 3 V I A 2 D f V f

101 Effect of low impedance gate drive 95 Low impedance gate drive R driver =0.4Ω Rg+Rdriver=0.4 Ω Efficiency (%) Conventional R driver =3.7Ω Rg+Rdriver=3.66 Ω Vin:12V, Vg:5V,Vout:1.3V,fsw:1MHz Iout(A)

102 Power loss analysis 3.5 Power loss (W) low side loss high side loss driver dead time (off) conduction self turn-on dead time (on) driver turn-off conduction turn-on Gate circuit resistance gate resistance + driver resistance (Ω) Remaining major loss Low impedance gate drive reduces the switching loss of high side MOSFET

103 Predicted Silicon Limit Efficiency Si Limit (R on =5mΩmm 2 ) Low impedance gate drive R driver =0.4Ω Efficiency (%) Conventional R driver =3.7Ω Rg+Rdriver=3.66 Ω Rg+Rdriver=0.4 Ω Vin:12V, Vg:5V,Vout:1.3V,fsw:1MHz MOSFET R on Improvement Iout(A)

104 Power loss analysis 2.5 Vin:12V, Vg:5V,Vout:1.3V,Iout:20A, Rg+Rdriver=0.4Ω Power loss (W) low side loss high side loss driver dead time (off) conduction self turn-on dead time (on) driver turn-off conduction turn-on 29mΩmm 2 5mΩmm 5 2 MOSFET RonA (mωmm2) R on A

105 GaN1.1

106 Predicted Silicon Limit Efficiency Si Limit (R on =5mΩmm 2 ) Low impedance gate drive R driver =0.4Ω 95 Rg+Rdriver=0.4 Ω MOSFET R on Improvement Efficiency (%) Conventional R driver =3.7Ω Rg+Rdriver=3.66 Ω GaN 1.1 Competitor B 80 Vin:12V, Vg:5V,Vout:1.3V,fsw:1MHz Iout(A)

107 New FOM IGBT IGBT SiC MOS SJMOS GaN GaN FET FET 30VMOSFET SiC Limit GaN Limit Si Limit V 10 V Breakdown Voltage [V] Ron Q str [mωnc] e2 1e3 1e4 1e5 1e6

108

109 12V 10A 1 Chip DCDC Converter 1A More than 10A 1chip DC/DC converter 1chip DC/DC converter Large drive Current 1 chip solution is adequate for high speed DCDC converter Low impedance gate drive can be easily implemented

110 0.6 CMOS nm

111 5V LDMOS Specific On-Resistance (mω/mm 2 )

112 25V n-ch LDMOS 2-step lightly doped drift layers --- Adaptive Resurf --- V BD =25V V th =0.85V R on =23mΩmm 2

Adaptive Resurf (2 step n-drift layer) 70.0E-3 60.

113 Adaptive Resurf (2 step n-drift layer) 70.0E E-3 (a)nch LDMOS (1-step n-implant) Avalanche current Drain Current Ids (A) 50.0E E E E-3 V G =5V (b)nch LDMOS (2-step n-implant) 10.0E E Drain-Source Voltage (V)

114 Issue of Interconnection resistance Equivalent circuit D Rd Rch R = R + DSON MOSFET R INTERCONNECTION Rs S Interconnection resistance

115 Top Metal thickness:1um Bonding PAD 432um 480um

116 Interconnection resistance can be reduced by Bump Tec Assembled image Flip chip PCB Thick Cu metal in PCB reduces interconnection resistance.

117 Output characteristics of large area device R on :9.7m (@V gs =5V, I ds =5A, effective area =3.6mm 2 )

118 Single driver circuit layout Gate Current Non-uniform switching LDMOS Concentrated Driver Circuit Single driver Parasitic metal layer resistance Gate & capacitance Signal interconnection Bus Line Load Drain Current Parasitic Gate Resistance

119 Distributed driver circuit layout Distributed Driver Circuit Pre-driver circuit Signal Current Gate interconnection Signal Bus Line Load Segmented LDMOS LDMOS Gate Current Drain Current frequency=780khz, Input Voltage=12V, Load resistance=1.2ω)

120 Switching waveforms V(switching node)

121 Measured efficiency vs. output current

122 4V 5V NchMOS Area 3.61mm 2 R on A8.1mΩmm 2 I D (A) R on =4.25mΩ 5V V G =3V 3.5V V D (V) I D (A) R on =12.4mΩ 5V PchMOS Area 3mm 2 R on A 30.5mΩmm 2 V D (V)

123 Evaluation PCB Board

124 20A operation Vin=5V Vout=1.083V fsw=980khz Efficiency (%) Output Current (A)

125

126

127

128 (1) (2) (1) LSI SiC GaN DCDC & Inverter (2)

129 + V in V M Ts M + - driver D comparator + - t v c (t) saw-tooth waveform generator L C e(t) error amplifier and compensator H - + v out + - R Hv out (t) V ref Analog controller + V in M DPWM d[n] D Compensator d[n]=f{d[n-1], d[n-2],..,e[n],e[n-1]..} + - driver L C e[n] H A/D + v out + - Hv out (t) R Hv out [n] V ref [n]

130 CMOS

131

132

133 V g + L + C _ V o f s = 1MHz OUT SENSE Digital controller IC V ref

134

135

136 Q1, Q2 OFF (dead-time) (1) (2) Dead-time Q2 Body Diode ON dead-time Duty Dead Time

137 Measured efficiency and duty-cycle pulse

138

139

140

141 Q = CΔV

142

143

(Microsoft PowerPoint - \203E\203B\203\223\203N\210\244\222m.ppt)

$(Microsoft PowerPoint - \203E\203B\203\223\203N\210\244\222m.ppt)$ IGBT 発展の経緯と限界特性中川明夫中川コンサルティング事務所 1 パワーデバイス応用分野の変遷 1997 2005 HVDC Transmission HVDC Transmission IGBT 2 パワーデバイス発展の経緯 ( 東芝の例 ) Power rating (VA) 100M 10M 1M 100K 1 st wave 10K 1960 500A2500V 80A400V 150A1000V