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1 LatticeECP/EC LatticeXP LatticeEC TM LatticeECP TM LatticeXP TM isplever EBR PFU LatticeECP/EC LatticeXP sysmem RAM(EBR) PFU RAM RAM RAM ROM EBR LUT PFU RAM RAM ROM FIFO EBR RAM PFU RAM 2 isplever IPexpress TM IPexpress 1 IPexpress LatticeECP/EC LatticeXP LatticeECP/EC LatticeXP I/O (PIC) PFU PFF sysmem RAM(EBR) PFU RAM ROM PFF (RAM) (EBR) PFU (RAM) EBR RAM EBR RAM (Row) (Column) RAM PFU PFU/PFF EBR 1 2 LatticeECP/EC/XP 8-1 Memory UG
2 8-1 LatticeEC 8-2 LatticeECP LatticeECP/EC/XP 8-2 Memory UG
3 8-3 LatticeXP IPexpress IPexpress LUT 1 IPexpress LatticeEC LatticeECP LatticeXP ( ) Tools > IPexpress LatticeEC/ECP LatticeXP 8-4 IPexpress LatticeECP/EC/XP 8-3 Memory UG
4 8-4 IPexpress (Module Tree) 8-4 EBR Module > Memory_Modules > Distributed_RAM PFU Module > Memory_Modules > EBR_Components 512 x 16 EBR RAM EBR_Components RAM_DP IPexpress RAM(RAM_DP) LatticeECP/EC/XP 8-4 Memory UG
5 Macro Type Version Module_Name IPexpress Project Path File Name Design Entry, Verilog VHDL VHDL Schematic/VHDL Verilog-HDL Schematic/Verilog-HDL Customize RAM ( 8-6) (Configuration) 8-6 RAM(RAM_DP) Configuration 512x16 RAM (True) RAM RAM EBR RAM Enable Output Registers Read Data Port LatticeECP/EC/XP 8-5 Memory UG
6 (Reset Mode) GSR Global Set Reset Enabled Disabled EBR RAM RAM ROM 16 Hex Addresses Hex Generate Import LPC to isplever project *.lpc Verilog-HDL/VHDL (EBR ) RAM(RAM_DQ) EBR RAM RAM_DQ LatticeECP/EC LatticeXP EBR IPexpress EDIF Verilog-HDL VHDL IPexpress EBR IPexpress GUI EBR EBR 1 EBR 1 EBR EBR LatticeECP/EC LatticeXP RAM_DQ 8-8 LatticeECP/EC/XP 8-6 Memory UG
7 8-8 LatticeECP/EC LatticeXP RAM RAM_DQ RAM 8-1 IPexpress EBR RAM_DQ 8-1 EBR EBR Clock CLK ClockEn CE Active High Address AD[x:0] Data DI[y:0] Q DO[y:0] WE WE Active High Reset RST Active High CS[2:0] (RST) RAM EBR CS EBR 3 CS MSB 8 8 EBR PFU (EBR ) EBR 9,216 RAM 8-2 LatticeECP/EC/XP 8-7 Memory UG
![DO[y:0] WE WE Active High Reset RST Active High CS[2:0] (RST) RAM EBR CS](/docs-images/42/23022669/images/page_7.jpg "EBR 3 CS MSB 8 8 EBR PFU (EBR ) EBR 9,216 RAM 8-2 LatticeECP/EC/XP 8-7")
8 8-2 LatticeECP/EC 9K [MSB:LSB] 8K x 1 DI DO AD[12:0] 4K x 2 DI[1:0] DO[1:0] AD[11:0] 2K x 4 DI[3:0] DO[3:0] AD[10:0] 1K x 9 DI[8:0] DO[8:0] AD[9:0] 512 x 18 DI[17:0] DO[17:0] AD[8:0] 256 x 36 DI[35:0] DO[35:0] AD[7:0] 8-3 (RAM_DQ) IPexpress GUI A 8-3 LatticeECP/EC RAM IPexpress DATA_WIDTH 1, 2, 4, 9, 18, 36 1 YES REGMODE ( ) NOREG, OUTREG NOREG YES RESETMODE ASYNC, SYNC ASYNC YES CSDECODE 000, 001, 010, 011, 100, 101, 110, 111 WRITEMODE / NORMAL, WRITETHROUGH, READBEFOREWRITE 000 NO NORMAL GSR / ENABLE, DISABLE ENABLED YES RAM RAM_DQ NORMAL READ BEFORE WRITE WRITE THROUGH Q RAM RAM YES LatticeECP/EC/XP 8-8 Memory UG
9 8-9 RAM NORMAL 8-10 RAM NORMAL LatticeECP/EC/XP 8-9 Memory UG
10 8-11 RAM READ BEFORE WRITE 8-12 RAM READ BEFORE WRITE LatticeECP/EC/XP 8-10 Memory UG
11 8-13 RAM WRITE THROUGH 8-14 RAM WRITE THROUGH LatticeECP/EC/XP 8-11 Memory UG
12 (True) RAM(RAM_DP_TRUE) EBR True-Dual Port RAM RAM_DP_TRUE LatticeECP/EC LatticeXP EBR IPexpress EDIF Verilog-HDL VHDL IPexpress RAM_DP_TRUE EBR 1 EBR 1 EBR EBR 8-16 LatticeECP/EC LatticeXP RAM RAM_DP_TRUE LatticeECP/EC/XP 8-12 Memory UG
13 LatticeECP/EC LatticeXP (RAM_DP_TRUE) 8-16 RAM 8-4 IPexpress EBR RAM_DP_TRUE 8-4 EBR EBR ClockA, ClockB CLKA, CLKB PortA/PortB Rising Clock Edge ClockEnA, ClockEnB CEA, CEB CLKA/CLKB AddressA, AddressB ADA[x:0], ADB[x:0] A/ B DataA, DataB DIA[y:0], DIB[y:0] A/ B QA, QB DOA[y:0], DOB[y:0] A/ B Active High WEA, WEB WEA, WEB A/ B Active High ResetA, ResetB RSTA, RSTB A/ B Active High CSA[2:0], CSB[2:0] (RST) RAM EBR CS EBR 3 CS MSB 8 8 EBR PFU (EBR ) EBR 9,216 RAM LatticeECP/EC LatticeXP 9K A B A B A [MSB:LSB] B [MSB:LSB] 8K x 1 DIA DIB DOA DOB ADA[12:0] ADB[12:0] 4K x 2 DIA[1:0] DIB[1:0] DOA[1:0] DOB[1:0] ADA[11:0] ADB[11:0] 2K x 4 DIA[3:0] DIB[3:0] DOA[3:0] DOB[3:0] ADA[10:0] ADB[10:0] 1K x 9 DIA[8:0] DIB[8:0] DOA[8:0] DOB[8:0] ADA[9:0] ADB[9:0] 512 x 18 DIA[17:0] DIB[17:0] DOA[17:0] DOB[17:0] ADA[8:0] ADB[8:0] 8-6 Memory(RAM_DP_TRUE) IPexpress GUI A LatticeECP/EC/XP 8-13 Memory UG
![CSA[2:0], CSB[2:0] (RST) RAM EBR CS EBR 3 CS MSB 8 8 EBR PFU (EBR ) EBR 9,216 RAM 8-5 8-5 LatticeECP/EC LatticeXP 9K A B A B A [MSB:LSB] B [MSB:LSB] 8K x 1 DIA DIB DOA DOB ADA[12:0] ADB[12:0] 4K x 2](/docs-images/42/23022669/images/page_13.jpg "DIA[1:0] DIB[1:0] DOA[1:0] DOB[1:0] ADA[11:0] ADB[11:0] 2K x 4 DIA[3:0] DIB[3:0] DOA[3:0] DOB[3:0] ADA[10:0] ADB[10:0] 1K x 9 DIA[8:0] DIB[8:0] DOA[8:0] DOB[8:0] ADA[9:0] ADB[9:0] 512 x 18 DIA[17:0]")
14 8-6 LatticeECP/EC LatticeXP RAM IPexpress DATA_WIDTH_A A 1, 2, 4, 9, 18 1 YES DATA_WIDTH_B B 1, 2, 4, 9, 18 1 YES REGMODE_A REGMODE_B ( ) A ( ) B NOREG, OUTREG NOREG YES NOREG, OUTREG NOREG YES RESETMODE ASYNC, SYNC ASYNC YES CSDECODE_A CSDECODE_B A B 000, 001, 010, 011, 100, 101, 110, , 001, 010, 011, 100, 101, 110, 111 WRITEMODE_A Read / Write A NORMAL, WRITETHROUGH, READBEFOREWRITE WRITEMODE_B Read / Write B NORMAL, WRITETHROUGH, READBEFOREWRITE 000 NO 000 NO NORMAL NORMAL GSR / ENABLE, DISABLE ENABLED YES RAM True Dual Port RAM RAM_DP_TRUE Q x9 x18 WRITE Appendix A RAM RAM YES YES LatticeECP/EC/XP 8-14 Memory UG
15 8-17 RAM NORMAL LatticeECP/EC/XP 8-15 Memory UG
16 8-18 RAM NORMAL LatticeECP/EC/XP 8-16 Memory UG
17 8-19 RAM READ BEFORE WRITE LatticeECP/EC/XP 8-17 Memory UG
18 8-20 RAM READ BEFORE WRITE LatticeECP/EC/XP 8-18 Memory UG
19 8-21 RAM WRITE THROUGH LatticeECP/EC/XP 8-19 Memory UG
20 8-22 RAM WRITE THROUGH LatticeECP/EC/XP 8-20 Memory UG
21 RAM(RAM_DP) EBR LatticeECP/EC LatticeXP EBR RAM RAM_DP IPexpress EDIF Verilog-HDL VHDL IPexpress EBR EBR 1 EBR 1 EBR EBR LatticeECP/EC LatticeXP LatticeECP/EC LatticeXP RAM RAM_DP RAM 8-7 LatticeECP/EC/XP 8-21 Memory UG
22 EBR RAM_DP 8-7 EBR EBR RdAddress ADR[x:0] WrAddress ADW[x:0] RdClock CLKR WrClock CLKW RdClockEn CER WrClockEn CEW Q DO[y:0] Data DI[y:0] Active High Active High WE WE Active High Reset RST Active High CS[2:0] (RST) RAM EBR CS EBR 3 CS MSB 8 8 EBR PFU (EBR ) EBR 9,216 RAM LatticeECP/EC LatticeXP 9K A B A B A [MSB:LSB] B [MSB:LSB] 8K x 1 DIA DIB DOA DOB RAD[12:0] WAD[12:0] 4K x 2 DIA[1:0] DIB[1:0] DOA[1:0] DOB[1:0] RAD[11:0] WAD[11:0] 2K x 4 DIA[3:0] DIB[3:0] DOA[3:0] DOB[3:0] RAD[10:0] WAD[10:0] 1K x 9 DIA[8:0] DIB[8:0] DOA[8:0] DOB[8:0] RAD[9:0] WAD[9:0] 512 x 18 DIA[17:0] DIB[17:0] DOA[17:0] DOB[17:0] RAD[8:0] WAD[8:0] 256 x 36 DIA[35:0] DIB[35:0] DOA[35:0] DOB[35:0] RAD[7:0] WAD[7:0] 8-9 (RAM_DP) IPexpress GUI A LatticeECP/EC/XP 8-22 Memory UG
23 8-9 LatticeECP/EC LatticeXP RAM IPexpress DATA_WIDTH_W Write 1, 2, 4, 9, 18, 36 1 YES DATA_WIDTH_R Read 1, 2, 4, 9, 18, 36 1 YES REGMODE ( ) NOREG, OUTREG NOREG YES RESETMODE ASYNC, SYNC ASYNC YES CSDECODE_W Write 000, 001, 010, 011, 100, 101, 110, NO CSDECODE_R Read 000, 001, 010, 011, 100, 101, 110, NO GSR / ENABLE, DISABLE ENABLED YES RAM RAM_DP RAM 8-25 RAM LatticeECP/EC/XP 8-23 Memory UG
24 8-26 RAM (ROM) EBR LatticeECP/EC LatticeXP EBR ROM IPexpress EDIF Verilog-HDL VHDL ROM IPexpress 8-27 EBR EBR 1 EBR 1 EBR EBR 8-27 IPexpress ROM LatticeECP/EC LatticeXP ROM 8-28 ROM LatticeECP/EC/XP 8-24 Memory UG
25 ROM 8-10 IPexpress ROM 8-28 LatticeECP/EC LatticeXP ROM 8-10 EBR ROM EBR Address AD[x:0] OutClock CLK OutClockEn CE Active High Reset RST Active High CS[2:0] (RST) RAM EBR CS EBR 3 CS MSB 8 8 EBR PFU (EBR ) IPexpress ROM ROM *.mem 16 Hex Addresses Hex(ORCA) (ROM) ROM LatticeECP/EC/XP 8-25 Memory UG
26 8-29 ROM 8-30 ROM (FIFO FIFO_DC) EBR LatticeECP/EC LatticeXP EBR FIFO FIFO_DC FIFO / FIFO_DC( Dual Clock FIFO) IPexpress EDIF Verilog-HDL VHDL 8-31 IPexpress FIFO LatticeECP/EC/XP 8-26 Memory UG
27 8-32 IPexpress FIFO_DC IPexpress FIFO FIFO_DC LatticeECP/EC LatticeXP FIFO FIFO FIFO_DC (RAM_DP )RAM EBR FIFO EBR FIFO FIFO FIFO_DC EBR FIFO/FIFO_DC Clock (CLK) (FIFO) RdClock (CLKR) (FIFO_DC) WrClock (CLKW) (FIFO_DC) WrEn (WE) Active High RdEn (RE) Active High Reset (RST) Active High Data (DI) Q (DO) Full (FF) Full Active High Almost Full (AF) Almost Full Active High Empty (EF) Empty Active High Almost Emplty (AE) Almost Empty Active High (RST) FIFO/FIFO_DC LatticeECP/EC LatticeXP FIFO/FIFO_DC 8-12 LatticeECP/EC/XP 8-27 Memory UG
28 8-12 LatticeECP/EC LatticeXP FIFO/FIFO_DC FIFO 8K x 1 DI DO 4K x 2 DI[1:0] DO[1:0] 2K x 4 DI[3:0] DO[3:0] 1K x 9 DI[8:0] DO[8:0] 512 x 18 DI[17:0] DO[17:0] 256 x 36 DI[35:0] DO[35:0] FIFO FIFO FIFO_DC 4 Empty Almost Empty Almost Full Full Almost Empty Almost Full FIFO FIFO FF Full 2N AFF Almost Full 1 (FF-1) 14 AEF Almost Empty 1 (FF-1) 14 EF Empty 0 5 (Empty Almost Empty Almost Full Full) 8-13 Empty Almost Empty Full Almost Full Empty( Full) Almost Empty( Almost Full) Low Almost Empty High Almost Empty Almost Full 512 FIFO Almost Full 500 IPexpress 500 Empty Almost Empty Full Almost Full FIFO FIFO RAM(EBR) (RAM_DQ) (RAM_DP) (RAM_DP_TRUE) FIFO RAM FIFO FIFO ( ) ( ) RdEn FIFO (FIFO) FIFO FIFO FIFO RAM LatticeECP/EC/XP 8-28 Memory UG
29 FPGA FIFO Reset Clock WrEn RdEn Data Q Full Flag Almost Full Flag Empty Flag Almost Empty Flag FIFO 8-33 FIFO 8-33 ( ) FIFO FIFO WrEn High Empty Almost Empty High Full Almost Full Low FIFO Empty (Low ) FIFO Almost Empty 3 ( 3) 3 Almost Empty LatticeECP/EC/XP 8-29 Memory UG
30 FIFO FIFO Almost Full Full 8-34 FIFO N' 8-34 ( ) FIFO Almost Full FIFO 2 N-2 Almost Full FIFO Full FIFO (Full High) Data_X FIFO 8-35 RdEn High Full Almost Full LatticeECP/EC/XP 8-30 Memory UG
31 8-35 ( ) FIFO FIFO Almost Empty Empty 8-36 ( ) FIFO LatticeECP/EC/XP 8-31 Memory UG
32 FIFO 1 RdEn RdEn FIFO FIFO 1 'Q' 8-37 FIFO LatticeECP/EC/XP 8-32 Memory UG
33 8-38 FIFO 8-39 FIFO LatticeECP/EC/XP 8-33 Memory UG
34 8-40 FIFO RdEn FIFO 1 RdEn High RdEn 8-41 RdEn FIFO LatticeECP/EC/XP 8-34 Memory UG
35 FIFO FIFO_DC FIFO_DC FIFO RAM FPGA FIFO_DC Reset RPReset WrClock RdClock WrEn RdEn Data Q Full Flag Almost Full Flag Empty Flag Almost Empty Flag FIFO_DC FIFO_DC FIFO RAM FPGA 2 FIFO FIFO_DC WrClock WrEn Empty Almost Empty RdClock Full Almost Full FIFO_DC WrClock FIFO_DC 8-42 FIFO_DC LatticeECP/EC/XP 8-35 Memory UG
36 8-42 FIFO_DC FIFO_DC WrEn High Empty Almost Empty High Full Almost Full Low FIFO_DC Empty (Low ) FIFO_DC Almost Empty 3 ( 3) 3 Almost Empty FIFO_DC FIFO_DC Almost Full Full 8-43 FIFO_DC N' LatticeECP/EC/XP 8-36 Memory UG
37 8-43 FIFO_DC Almost Full FIFO_DC 2 'N-2' Almost Full FIFO_DC Full FIFO_DC (Full High) Data_X FIFO_DC 8-44 RdEn High Full Almost Full 2 LatticeECP/EC/XP 8-37 Memory UG
38 8-44 FIFO_DC FIFO_DC Almost Empty Empty 8-45 FIFO_DC LatticeECP/EC/XP 8-38 Memory UG
39 FIFO_DC 1 RdEn RdEn FIFO_DC FIFO_DC Q' FIFO_DC LatticeECP/EC/XP 8-39 Memory UG
40 8-47 FIFO_DC 8-48 FIFO_DC LatticeECP/EC/XP 8-40 Memory UG
41 8-49 FIFO_DC RdEn FIFO_DC 1 RdEn High RdEn LatticeECP/EC/XP 8-41 Memory UG
42 8-50 RdEn FIFO_DC LatticeECP/EC/XP 8-42 Memory UG
43 RAM(Distributed_SPRAM) PFU PFU RAM PFU 4 LUT( ) LUT 8-51 IPexpress RAM 8-51 IPexpress RAM PFU 4 LUT Clock ClockEn Reset PFU LatticeECP/EC LatticeXP RAM LatticeECP/EC LatticeXP RAM (Sync_Single-Port_RAM) (RdClock) (RdClockEn) IPexpress 8-14 IPexpress RAM(Distributed _SPRAM) LatticeECP/EC/XP 8-43 Memory UG
44 8-14 PFU RAM EBR Clock CK ClockEn - Active High Reset - Active High WE WRE Active High Address AD[3:0] Data DI[1:0] Q DO[1:0] 8-53 PFU RAM 8-54 PFU RAM LatticeECP/EC/XP 8-44 Memory UG
45 RAM(Distributed_DPRAM) PFU PFU RAM PFU 4 LUT LUT 8-55 IPexpress RAM 8-55 IPexpress RAM PFU 4 LUT Clocks Clock Enables Reset PFU LatticeECP/EC RAM 8-56 (RdClock) (RdClockEn) 8-15 IPexpress 8-56 LatticeEC/ECP LatticeXP PFU RAM LatticeECP/EC/XP 8-45 Memory UG
46 8-15 PFU RAM EBR WrAddress WAD[23:0] RdAddress RAD[3:0] RdClock RdClockEn High WrClock WCK WrClockEn High WE WRE High Data DI[1:0] Q RDO[1:0] RAM(Distributed_DPRAM) PFU RAM LatticeECP/EC/XP 8-46 Memory UG
47 8-58 PFU RAM ROM(Distributed_ROM) PFU PFU ROM PFU 4 LUT LUT 8-59 IPexpress RAM 8-59 IPexpress ROM PFU 4 LUT LatticeECP/EC LatticeXP RAM 8-60 Out Clock(OutClock) Out Clock Enable(OutClockEn) LatticeECP/EC/XP 8-47 Memory UG
48 IPexpress 8-60 LatticeECP/EC PFU ROM(Sync_ROM) 8-16 IPexpress 8-16 PFU ROM EBR Address AD[3:0] OutClock Rising Clock Edge OutClockEn Active High Reset Active High Q DO ROM(Distributed_ROM) PFU ROM LatticeECP/EC/XP 8-48 Memory UG
49 8-62 PFU ROM EBR ROM RAM 0 1 ASCII IPexpress (Hex) (Addressed Hex) *.mem(<file_name>.mem) ( ) ( ) ROM RAM EBR x LatticeECP/EC/XP 8-49 Memory UG
50 x16 A001 0B CE A A4 16 (ORCA) 16 memfile : 16 -A0 : 03 F3 3E 4F -B2 : 3B 9F A0 03 A1 F3 A2 3E A3 4F B2 3B B3 9F addr_width data_width 0 IPexpress : LATTICE (North America) (Outside North America) [email protected] : LatticeECP/EC/XP 8-50 Memory UG
51 A. DATA_WIDTH RAM FIFO DATA_WIDTH RAM REGMODE REGMODE RAM FIFO REGMODE NOREG OUTREG RESETMODE RESETMODE RAM RESETMODE 2 SYNC ASYNC SYNC ASYNC CSDECODE CSDECODE( ) RAM EBR CS EBR EBR CS MSB CS 3 8 CSDECODE ; 000", 001", 010", 011", 100", 101", 110", 111" CSDECODE CS[2:0] RAM CSDECODE_W CSDECODE_R CSDECODE_A CSDECODE_B RAM A B WRITEMODE WRITEMODE RAM NORMAL WRITETHROUGH READBEFOREWRITE NORMAL WRITETHROUGH READBEFOREWRITE x9 x18 x36 WRITEMODE_A WRITEMODE_B RAM RAM A B Hi Low LatticeECP/EC/XP 8-51 Memory UG
52 GSR GSR / RAM / LatticeECP/EC/XP 8-52 Memory UG
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