PIC16C7X日本語データシート

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1 PIC16C7X PIC16C7X A/D CMOS 1996 Microchip Technology Inc. DS30390B-J00 - page 1

2 PIC16C7X DS30390B-J00 - page Microchip Technology Inc. PIC16C710 RA2/AN2 RA3/AN3/V REF RA4/T0CKI MCLR/VPP V SS V SS RB0/INT RB1 RB2 RB3 RA1/AN1 RA0/AN0 OSC1/CLKIN OSC2/CLKOUT V DD RB7 RB6 RB5 RB V DD SSOP RA2/AN2 RA3/AN3/V REF RA4/T0CKI MCLR/VPP V SS RB0/INT RB1 RB2 RB3 RA1/AN1 RA0/AN0 OSC1/CLKIN OSC2/CLKOUT V DD RB7 RB6 RB5 RB PIC16C710 PDIP, SOIC, Windowed CERDIP PIC16C711 RA2/AN2 RA3/AN3/V REF RA4/T0CKI MCLR/VPP V SS V SS RB0/INT RB1 RB2 RB3 RA1/AN1 RA0/AN0 OSC1/CLKIN OSC2/CLKOUT V DD RB7 RB6 RB5 RB V DD SSOP RA2/AN2 RA3/AN3/V REF RA4/T0CKI MCLR/VPP V SS RB0/INT RB1 RB2 RB3 RA1/AN1 RA0/AN0 OSC1/CLKIN OSC2/CLKOUT V DD RB7 RB6 RB5 RB PIC16C711 PDIP, SOIC, Windowed CERDIP RA2/AN2 RA3/AN3/V REF RA4/T0CKI MCLR/VPP V SS RB0/INT RB1 RB2 RB3 RA1/AN1 RA0/AN0 OSC1/CLKIN OSC2/CLKOUT V DD RB7 RB6 RB5 RB PIC16C71 PDIP, SOIC, Windowed CERDIP PIC16C72 MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/V REF RA4/T0CKI RA5/AN4/SS V SS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT V DD V SS RC7 RC6 RC5/SDO RC4/SDI/SDA SDIP, SOIC, Windowed Side Brazed Ceramic PIC16C72 MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/V REF RA4/T0CKI RA5/AN4/SS V SS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT V DD V SS RC7 RC6 RC5/SDO RC4/SDI/SDA SSOP

3 PIC16C7X 1996 Microchip Technology Inc. DS30390B-J00 - page 3 PIC16C73 MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/V REF RA4/T0CKI RA5/AN4/SS V SS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT V DD V SS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA PIC16C73A SDIP, SOIC, Windowed Side Brazed Ceramic NC RC0/T1OSO/T1CK OSC2/CLKOUT OSC1/CLKIN V SS V DD RE2/CS/AN7 RE1/WR/AN6 RE0/RD/AN5 RA5/AN4/SS RA4/T0CKI RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 V SS V DD RB0/INT RB1 RB2 RB3 RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1 RC1/T1OSI/CCP2 NC RA3/AN3/VREF RA2/AN2 RA1/AN1 RA0/AN0 MCLR/VPP RB7 RB6 RB5 RB4 NC NC PIC16C74 MQFP RB3 RB2 RB1 RB0/INT V DD V SS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT RA4/T0CKI RA5/AN4/SS RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 V DD V SS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI NC RA3/AN3/VREF RA2/AN2 RA1/AN1 RA0/AN0 MCLR/VPP NC RB7 RB6 RB5 RB4 NC NC RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1 RC1/T1OSI PIC16C74 /CCP2 NC RC0/T1OSO/T1CK OSC2/CLKOUT OSC1/CLKIN V SS V DD RE2/CS/AN7 RE1/WR/AN6 RE0/RD/AN5 RA5/AN4/SS RA4/T0CKI RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 V SS V DD RB0/INT RB1 RB2 RB3 RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1 RC1/T1OSI/CCP2 NC RA3/AN3/VREF RA2/AN2 RA1/AN1 RA0/AN0 MCLR/VPP RB7 RB6 RB5 RB4 NC NC PDIP, Windowed CERDIP MQFP PLCC RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT V DD V SS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/V REF RA4/T0CKI RA5/AN4/SS RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 V DD V SS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RD0/PSP0 RD1/PSP PIC16C74 PIC16C74A PIC16C74A PIC16C74A TQFP

4 PIC16C7X DS30390B-J00 - page Microchip Technology Inc.

5 PIC16C7X 1996 Microchip Technology Inc. DS30390B-J00-page 5

6 DS30390B-J00-page Microchip Technology Inc. PIC16C7X

7 PIC16C7X MicrochipPICSTART TM PRO MATE TM PIC16C7X Microchip Microchip 1996 Microchip Technology Inc. DS30390B-J00 - page 7

8 PIC16C7X DS30390B-J00 - page Microchip Technology Inc.

9 PIC16C7X 1996 Microchip Technology Inc. DS30390B-J00 - page - 9

10 PIC16C7X Device PIC16C710 PIC16C71 PIC16C711 Program Memory 512 x 14 1K x 14 1K x 14 Data Memory (RAM) 36 x 8 36 x 8 68 x 8 Program Bus EPROM Program Memory Program Counter 8 Level Stack (13-bit) Data Bus RAM File Registers RAM Addr (1) 9 8 PORTA PORTB RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/V REF RA4/T0CKI Instruction reg Direct Addr 7 Addr MUX 8 FSR reg Indirect Addr RB0/INT RB7:RB1 8 STATUS reg OSC1/CLKIN OSC2/CLKOUT Instruction Decode & Control Timing Generation Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset (2) 8 3 MUX ALU W reg Timer0 MCLR V DD, V SS A/D Note 1: Higher order bits are from the STATUS register. 2: Brown-out Reset is not available on the PIC16C71. DS30390B-J00 - page Microchip Technology Inc.

11 PIC16C7X Program Bus EPROM Program Memory 2K x Program Counter 8 Level Stack (13-bit) (1) RAM Addr Data Bus RAM File Registers 128 x PORTA PORTB RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/V REF RA4/T0CKI RA5/AN4/SS Instruction reg Direct Addr 7 Addr MUX 8 FSR reg Indirect Addr RB0/INT RB7:RB1 OSC1/CLKIN OSC2/CLKOUT Instruction Decode & Control Timing Generation 8 Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset 8 3 STATUS reg MUX ALU W reg PORTC RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6 RC7 MCLR V DD, V SS Timer0 Timer1 Timer2 A/D Synchronous Serial Port CCP1 Note 1: Higher order bits are from the STATUS register Microchip Technology Inc. DS30390B-J00 - page - 11

12 PIC16C7X Program Bus EPROM Program Memory 4K x Program Counter 8 Level Stack (13-bit) (1) RAM Addr Data Bus RAM File Registers 192 x PORTA PORTB RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/V REF RA4/T0CKI RA5/AN4/SS Instruction reg Direct Addr 7 Addr MUX 8 FSR reg Indirect Addr RB0/INT RB7:RB1 OSC1/CLKIN OSC2/CLKOUT Instruction Decode & Control Timing Generation 8 Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out (2) Reset 8 3 STATUS reg MUX ALU W reg PORTC RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT MCLR V DD, V SS Timer0 Timer1 Timer2 A/D CCP1 CCP2 Synchronous Serial Port USART Note 1: 2: Higher order bits are from the STATUS register. Brown-out Reset is not available on the PIC16C73. DS30390B-J00 - page Microchip Technology Inc.

13 PIC16C7X Program Bus EPROM Program Memory 4K x Program Counter 8 Level Stack (13-bit) Data Bus RAM File Registers 192 x 8 RAM Addr (1) 9 8 PORTA PORTB RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/V REF RA4/T0CKI RA5/AN4/SS Instruction reg Direct Addr 7 Addr MUX 8 Indirect Addr RB0/INT FSR reg RB7:RB1 OSC1/CLKIN OSC2/CLKOUT Instruction Decode & Control Timing Generation 8 Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out (2) Reset 8 3 STATUS reg MUX ALU W reg PORTC PORTD RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT RD7/PSP7:RD0/PSP0 MCLR V DD, V SS Parallel Slave Port PORTE RE0/RD/AN5 RE1/WR/AN6 Timer0 Timer1 Timer2 A/D RE2/CS/AN7 CCP1 CCP2 Synchronous Serial Port USART Note 1: 2: Higher order bits are from the STATUS register. Brown-out Reset is not available on the PIC16C Microchip Technology Inc. DS30390B-J00 - page - 13

14 PIC16C7X DS30390B-J00 - page Microchip Technology Inc.

15 PIC16C7X 1996 Microchip Technology Inc. DS30390B-J00 - page - 15

16 PIC16C7X DS30390B-J00 - page Microchip Technology Inc.

17 PIC16C7X 1996 Microchip Technology Inc. DS30390B-J00 - page - 17

18 PIC16C7X DS30390B-J00 - page Microchip Technology Inc.

19 PIC16C7X 1996 Microchip Technology Inc. DS30390B-J00 - page - 19

20 PIC16C7X Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Q3 Q4 Internal phase clock PC PC PC+1 PC+2 OSC2/CLKOUT (RC mode) Fetch INST (PC) Execute INST (PC-1) Fetch INST (PC+1) Execute INST (PC) Fetch INST (PC+2) Execute INST (PC+1) 1. MOVLW 55h Fetch1 Execute1 2. MOVWF PORTB Fetch2 Execute2 3. CALL SUB_1 Fetch3 Execute3 4. BSF PORTA,BIT3 Fetch4 Flush Fetch SUB_1 Execute SUB_1 DS30390B-J00 - page Microchip Technology Inc.

21 PIC16C7X CALL, RETURN RETFIE, RETLW PC<12:0> 13 Stack Level 1 Stack Level 8 Reset Vector Interrupt Vector On-chip Program Memory 0000h 0004h 0005h 03FFh 0200h 1FFFh CALL, RETURN RETFIE, RETLW PC<12:0> 13 Stack Level 1 Stack Level 8 Reset Vector 0000h Interrupt Vector On-chip Program Memory 0004h 0005h 01FFh 0200h 1FFFh 1996 Microchip Technology Inc. DS30390B-J00 - page 21

22 PIC16C7X CALL, RETURN RETFIE, RETLW PC<12:0> 13 Stack Level 1 CALL, RETURN RETFIE, RETLW PC<12:0> 13 Stack Level 1 Stack Level 8 Stack Level 8 Reset Vector 0000h Reset Vector 0000h Interrupt Vector On-chip Program Memory 0004h 0005h 07FFh 0800h Interrupt Vector On-chip Program Memory (Page 0) On-chip Program Memory (Page 1) 0004h 0005h 07FFh 0800h 0FFFh 1000h 1FFFh 1FFFh DS30390B-J00 - page Microchip Technology Inc.

23 PIC16C7X File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 2Fh 30h INDF (1) TMR0 PCL STATUS FSR PORTA PORTB ADCON0 ADRES PCLATH INTCON General Purpose Register (1) INDF OPTION PCL STATUS FSR TRISA TRISB PCON (2) ADCON1 ADRES PCLATH INTCON General Purpose Register Mapped in Bank 0 (3) File Address 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch AFh B0h File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 4Fh 50h INDF (1) TMR0 PCL STATUS FSR PORTA PORTB ADCON0 ADRES PCLATH INTCON General Purpose Register INDF (1) OPTION PCL STATUS FSR TRISA TRISB PCON ADCON1 ADRES PCLATH INTCON General Purpose Register Mapped (2) in Bank 0 File Address 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch CFh D0h 7Fh Bank 0 Bank 1 FFh 7Fh Bank 0 Bank 1 FFh Unimplemented data memory locations, read as '0'. Note 1: Not a physical register. 2: The PCON register is not implemented on the PIC16C71. 3: These locations are unimplemented in Bank 1. Any access to these locations will access the corresponding Bank 0 register. Unimplemented data memory locations, read as '0'. Note 1: Not a physical register. 2: These locations are unimplemented in Bank 1. Any access to these locations will access the corresponding Bank 0 register Microchip Technology Inc. DS30390B-J00 - page 23

24 PIC16C7X File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h INDF (1) TMR0 PCL STATUS FSR PORTA PORTB PORTC PCLATH INTCON PIR1 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON ADRES ADCON0 General Purpose Register INDF (1) OPTION PCL STATUS FSR TRISA TRISB TRISC PCLATH INTCON PIE1 PCON PR2 SSPADD SSPSTAT ADCON1 General Purpose Register File Address 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h BFh C0h File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h INDF (1) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD (2) PORTE (2) PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRES ADCON0 General Purpose Register INDF (1) OPTION PCL STATUS FSR TRISA TRISB TRISC TRISD (2) TRISE (2) PCLATH INTCON PIE1 PIE2 PCON PR2 SSPADD SSPSTAT TXSTA SPBRG ADCON1 General Purpose Register File Address 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h 7Fh Bank 0 Bank 1 FFh 7Fh FFh Bank 0 Bank 1 Unimplemented data memory locations, read as '0'. Note 1: Not a physical register. Unimplemented data memory locations, read as '0'. Note 1: Not a physical register. 2: These registers are not physically implemented on the PIC16C73/73A, read as '0'. DS30390B-J00 - page Microchip Technology Inc.

25 PIC16C7X 1996 Microchip Technology Inc. DS30390B-J00 - page 25

26 PIC16C7X DS30390B-J00 - page Microchip Technology Inc.

27 PIC16C7X 1996 Microchip Technology Inc. DS30390B-J00 - page 27

28 PIC16C7X DS30390B-J00 - page Microchip Technology Inc.

29 PIC16C7X 1996 Microchip Technology Inc. DS30390B-J00 - page 29

30 PIC16C7X R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x IRP RP1 RP0 TO PD Z DC C bit7 bit0 DS30390B-J00 - page Microchip Technology Inc.

31 PIC16C7X R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit7 bit Microchip Technology Inc. DS30390B-J00 - page 31

32 PIC16C7X R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE ADIE T0IE INTE RBIE T0IF INTF RBIF bit7 bit0 DS30390B-J00 - page Microchip Technology Inc.

33 PIC16C7X R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE PEIE T0IE INTE RBIE T0IF INTF RBIF bit7 bit Microchip Technology Inc. DS30390B-J00 - page 33

34 PIC16C7X U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 bit7 - ADIE - - SSPIE CCP1IE TMR2IE TMR1IE bit0 DS30390B-J00 - page Microchip Technology Inc.

35 PIC16C7X R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIE (1) bit7 ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE bit Microchip Technology Inc. DS30390B-J00 - page 35

36 PIC16C7X U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 - ADIF - - SSPIF CCP1IF TMR2IF TMR1IF bit7 bit0 DS30390B-J00 - page Microchip Technology Inc.

37 PIC16C7X R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIF (1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF bit7 bit Microchip Technology Inc. DS30390B-J00 - page 37

38 PIC16C7X U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W CCP2IE bit7 bit0 DS30390B-J00 - page Microchip Technology Inc.

39 PIC16C7X U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W CCP2IF bit7 bit Microchip Technology Inc. DS30390B-J00 - page 39

40 PIC16C7X U-0 U-0 U-0 U-0 U-0 U-0 R/W-q R/W-q POR BOR (1) bit7 bit0 DS30390B-J00 - page Microchip Technology Inc.

41 PIC16C7X PC PC PCH PCH PCLATH<4:0> 8 PCLATH 7 PCL PCL Instruction with PCL as Destination ALU result GOTO, CALL 2 PCLATH<4:3> PCLATH 11 Opcode <10:0> 1996 Microchip Technology Inc. DS30390B-J00 - page 41

42 PIC16C7X ORG 0x500 BSF PCLATH,3 ;Select page1(800h-fffh) CALL SUB1_P1 ;Call subroutine in : ;page1 (800h-FFFh) : : ORG 0x900 SUB1_P1 : ;called subroutine : ;page1 (800h-FFFh) : RETURN ;return to Call subroutine ;in page 0 (000h-7FFh) movlw 0x20 ;initialize pointer movwf FSR ;to RAM NEXT clrf INDF ;clear INDF register incf FSR,F ;inc pointer btfss FSR,4 ;all done? goto NEXT ;no clear next CONTINUE : ;yes continue Direct Addressing Indirect Addressing (1) RP1 RP0 6 from opcode 0 IRP (1) 7 FSR register 0 bank select location select 00h bank select 00h location select Data Memory not used 7Fh Bank 0 Bank 1 Bank 2 Bank 3 7Fh For register file map detail see Figure 4-5, Figure 4-6, Figure 4-7, and Figure 4-8. Note 1: The RP1 and IRP bits are reserved, always maintain these bits clear. DS30390B-J00 - page Microchip Technology Inc.

43 PIC16C7X CLRF PORTA ; Initialize PORTA by ; setting output ; data latches BSF STATUS, RP0 ; Select Bank 1 MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISA ; Set RA<3:0> as inputs ; RA<5:4> as outputs ; TRISA<7:6> are always ; read as `0. Data bus WR PORT D Q CK Q Data Latch VDD P D Q N I/O pin WR TRIS CK Q TRIS Latch RD TRIS Q D Analog input mode TTL input buffer EN RD PORT To A/D Converter 1996 Microchip Technology Inc. DS30390B-J00 - page 43

44 PIC16C7X Data Bus D Q WR PORT CK Q Data Latch N V SS RA4/T0CKI pin D Q WR TRIS CK Q TRIS Latch Schmitt Trigger input buffer RD TRIS Q D EN EN RD PORT TMR0 clock input Note: I/O pin has protection diodes to V SS only. DS30390B-J00 - page Microchip Technology Inc.

45 PIC16C7X CLRF PORTB ; Initialize PORTB by ; setting output ; data latches BSF STATUS, RP0 ; Select Bank 1 MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISB ; Set RB<3:0> as inputs ; RB<5:4> as outputs ; RB<7:6> as inputs RBPU (2) Data bus WR Port WR TRIS Data Latch D Q CK TRIS Latch D Q CK RD TRIS TTL Input Buffer VDD P weak pull-up I/O pin (1) RBPU(2) Data bus WR PORT WR TRIS Data Latch D CK Q TRIS Latch D CK Q TTL Input Buffer VDD weak pull-up ST Buffer I/O pin(1) Q D RB0/INT RD Port Schmitt Trigger Buffer EN RD Port Note 1: I/O pins have diode protection to V DD and V SS. 2: TRISB = '1' enables weak pull-up if RBPU = '0' (OPTION<7>). Set RBIF RD TRIS RD Port Latch Q D EN Q D From other RB7:RB4 pins EN RB7:RB6 in serial programming mode RD Port 1996 Microchip Technology Inc. DS30390B-J00 - page 45

46 PIC16C7X DS30390B-J00 - page Microchip Technology Inc.

47 PIC16C7X CLRF PORTC ; Initialize PORTC by ; setting output ; data latches BSF STATUS, RP0 ; Select Bank 1 MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISC ; Set RC<3:0> as inputs ; RC<5:4> as outputs ; RC<7:6> as inputs PORT/PERIPHERAL Select (1) Peripheral Data-out Data Bus D Q 0 1 V DD P WR PORT CK Q Data Latch D Q I/O pin WR TRIS CK Q N TRIS Latch V SS Peripheral OE (2) RD TRIS Schmitt Trigger Peripheral input RD PORT Q D EN EN Note 1: Port/Peripheral select signal selects between port data and peripheral output. 2: Peripheral OE (output enable) is only activated if peripheral select is active. 3: I/O pins have diode protection to V DD and V SS. RD PORT 1996 Microchip Technology Inc. DS30390B-J00 - page 47

48 PIC16C7X DS30390B-J00 - page Microchip Technology Inc.

49 PIC16C7X Data Bus D Q WR PORT CK Q I/O pin Data Latch D Q WR TRIS CK Q TRIS Latch Schmitt Trigger input buffer RD TRIS Q D EN EN RD PORT Note: I/O pins has protection diodes to V DD and V SS Microchip Technology Inc. DS30390B-J00 - page 49

50 PIC16C7X DS30390B-J00 - page Microchip Technology Inc.

51 PIC16C7X R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 IBF OBF IBOV PSPMODE - TRISE2 TRISE1 TRISE0 bit7 bit Microchip Technology Inc. DS30390B-J00 - page 51

52 PIC16C7X Data Bus D Q WR PORT CK Q I/O pin Data Latch D Q WR TRIS CK Q TRIS Latch Schmitt Trigger input buffer RD TRIS Q D EN EN RD PORT DS30390B-J00 - page Microchip Technology Inc.

53 PIC16C7X ;Initial PORT settings: PORTB<7:4> Inputs ; PORTB<3:0> Outputs ;PORTB<7:6> have external pull-ups and are ;not connected to other circuitry ; ; PORT latch PORT pins ; BCF PORTB, 7 ; 01pp ppp 11pp ppp BCF PORTB, 6 ; 10pp ppp 11pp ppp BSF STATUS, RP0 ; BCF TRISB, 7 ; 10pp ppp 11pp ppp BCF TRISB, 6 ; 10pp ppp 10pp ppp ; ;Note that the user may have expected the ;pin values to be 00pp ppp. The 2nd BCF ;caused RB7 to be latched as the pin value ;(high). PC Instruction fetched RB7:RB0 Instruction executed Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC PC + 1 PC + 2 PC + 3 MOVWF PORTB write to PORTB MOVWF PORTB,W MOVWF PORTB write to PORTB NOP Port pin sampled here TPD MOVWF PORTB,W NOP NOP 1996 Microchip Technology Inc. DS30390B-J00 - page 53

54 PIC16C7X Data bus Q D RDx pin WR Port CK EN D Q RD Port EN EN TTL One bit of PORTD Set interrupt flag PSPIF (PIR1<7>) Read TTL RD Chip Select Write CS WR Note: I/O pins has protection diodes to V DD and V SS. DS30390B-J00 - page Microchip Technology Inc.

55 PIC16C7X 1996 Microchip Technology Inc. DS30390B-J00 - page 55

56 PIC16C7X NOTES: DS30390B-J00 - page Microchip Technology Inc.

57 PIC16C7X 1996 Microchip Technology Inc. DS30390B-J00 - page 57

58 PIC16C7X NOTES: DS30390B-J00 - page Microchip Technology Inc.

59 PIC16C7X Data bus F OSC /4 0 PSout 8 1 Sync with 1 Internal TMR0 clocks RA4/T0CKI Programmable 0 PSout pin Prescaler T0SE (2 cycle delay) 3 Set interrupt PS2, PS1, PS0 PSA flag bit T0IF T0CS on overflow Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION<5:0>). 2: The prescaler is shared with Watchdog Timer (refer to Figure 7-6 for detailed block diagram). PC (Program Counter) Q1 Q2 Q3 PC-1 Q4 Q1 Q2 Q3 PC Q4 Q1 Q2 Q3 PC+1 Q4 Q1 Q2 Q3 PC+2 Q4 Q1 Q2 Q3 PC+3 Q4 Q1 Q2 Q3 PC+4 Q4 Q1 Q2 Q3 PC+5 Q4 Q1 Q2 Q3 PC+6 Q4 Instruction Fetch MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W TMR0 T0 T0+1 T0+2 NT0 NT0 NT0 NT0+1 NT0+2 T Instruction Executed Write TMR0 executed Read TMR0 reads NT0 Read TMR0 reads NT0 Read TMR0 reads NT0 Read TMR0 reads NT0 + 1 Read TMR0 reads NT Microchip Technology Inc. DS30390B-J00 - page 59

60 PIC16C7X PC (Program Counter) Q1 Q2 Q3 PC-1 Q4 Q1 Q2 Q3 PC Q4 Q1 Q2 Q3 PC+1 Q4 Q1 Q2 Q3 PC+2 Q4 Q1 Q2 Q3 PC+3 Q4 Q1 Q2 Q3 PC+4 Q4 Q1 Q2 Q3 PC+5 Q4 Q1 Q2 Q3 PC+6 Q4 Instruction Fetch MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W TMR0 T0 T0+1 NT0 NT0+1 PC Instruction Execute Write TMR0 executed Read TMR0 reads NT0 Read TMR0 reads NT0 Read TMR0 reads NT0 Read TMR0 reads NT0 Read TMR0 reads NT0 + 1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT (3) Timer0 T0IF bit (INTCON<2>) FEh 1 FFh 1 00h 01h 02h GIE bit (INTCON<7>) INSTRUCTION FLOW PC PC PC +1 PC h 0005h Instruction fetched Inst (PC) Inst (PC+1) Inst (0004h) Inst (0005h) Instruction executed Inst (PC-1) Inst (PC) Dummy cycle Dummy cycle Inst (0004h) Note 1: Interrupt flag bit T0IF is sampled here (every Q1). 2: Interrupt latency = 4Tcy where Tcy = instruction cycle time. 3: CLKOUT is available only in RC oscillator mode. DS30390B-J00 - page Microchip Technology Inc.

61 PIC16C7X External Clock Input or Prescaler output (2) External Clock/Prescaler Output after sampling Q1 (3) Q2 Q3 (1) Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Small pulse misses sampling Increment Timer0 (Q4) Timer0 T0 T0 + 1 T0 + 2 Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc). Therefore, the error in measuring the interval between two edges on Timer0 input = ± 4Tosc max. 2: External clock if no prescaler selected, Prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs Microchip Technology Inc. DS30390B-J00 - page 61

62 PIC16C7X CLKOUT (=Fosc/4) Data Bus RA4/T0CKI pin 0 1 M U X 1 0 M U X SYNC 2 Cycles TMR0 reg 8 T0SE T0CS PSA Set flag bit T0IF on Overflow Watchdog Timer 0 1 M U X 8-bit Prescaler 8 PSA 8 - to - 1MUX PS2:PS0 WDT Enable bit 0 M U X 1 PSA WDT Time-out Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION<5:0>). DS30390B-J00 - page Microchip Technology Inc.

63 PIC16C7X CLRWDT ;Clear WDT and ;prescaler BSF STATUS, RP0 ;Bank 1 MOVLW b xxxx0xxx ;Select TMR0, new ;prescale value and MOVWF OPTION ;clock source BCF STATUS, RP0 ;Bank 0 BCF STATUS, RP0 ;Bank 0 CLRF TMR0 ;Clear TMR0 & Prescaler BSF STATUS, RP0 ;Bank 1 CLRWDT ;Clears WDT MOVLW b xxxx1xxx ;Select new prescale MOVWF OPTION ;value & WDT BCF STATUS, RP0 ;Bank Microchip Technology Inc. DS30390B-J00 - page 63

64 PIC16C7X NOTES: DS30390B-J00 - page Microchip Technology Inc.

65 PIC16C7X U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit7 bit Microchip Technology Inc. DS30390B-J00 - page 65

66 PIC16C7X Set flag bit TMR1IF on Overflow RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 (2) TMR1H T1OSC TMR1 TMR1L (3) T1OSCEN OSC/4 Enable Internal Oscillator (1) Clock TMR1ON on/off T1SYNC 1 Prescaler 1, 2, 4, T1CKPS1:T1CKPS0 TMR1CS 0 1 Synchronized clock input Synchronize det SLEEP input Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. 2: The CCP2 module is not implemented in the PIC16C72. 3: For the PIC16C73 and PIC16C74, the Schmitt Trigger is not implemented in external clock mode. DS30390B-J00 - page Microchip Technology Inc.

67 PIC16C7X MOVF TMR1H, W ;Read high byte MOVWF TMPH ; MOVF TMR1L, W ;Read low byte MOVWF TMPL ; MOVF TMR1H, W ;Read high byte SUBWF TMPH, W ;Sub 1st read ; with 2nd read BTFSC STATUS,Z ;Is result = 0 GOTO CONTINUE ;Good 16-bit read ; ; TMR1L may have rolled over between the read ; of the high and low bytes. Reading the high ; and low bytes now will read a good value. ; MOVF TMR1H, W ;Read high byte MOVWF TMPH ; MOVF TMR1L, W ;Read low byte MOVWF TMPL ; ; Re-enable the Interrupt (if required) CONTINUE ;Continue with ;your code Osc Type Freq C1 C2 LP 32 khz (1) 15 pf 15 pf 100 khz 15 pf 15 pf 200 khz 0-15 pf 0-15 pf 1 V DD 4.5VC1 = C2 30pF Crystals Tested: khz Epson C-001R32.768K-A ± 20 PPM 100 khz Epson C KC-P ± 20 PPM 200 khz STD XTL khz ± 20 PPM 1996 Microchip Technology Inc. DS30390B-J00 - page 67

68 PIC16C7X DS30390B-J00 - page Microchip Technology Inc.

69 PIC16C7X Sets flag bit TMR2IF TMR2 output (1) Reset TMR2 reg Prescaler 1:1, 1:4, 1:16 OSC/4 Postscaler 1:1 to 1:16 EQ Comparator 2 4 PR2 reg Note 1: TMR2 register output can be software selected by the SSP Module as a baud clock Microchip Technology Inc. DS30390B-J00 - page 69

70 PIC16C7X U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 - TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit7 bit0 DS30390B-J00 - page Microchip Technology Inc.

71 PIC16C7X 1996 Microchip Technology Inc. DS30390B-J00 - page 71

72 PIC16C7X U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W CCPxX CCPxY CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit7 bit0 DS30390B-J00 - page Microchip Technology Inc.

73 PIC16C7X CLRF CCP1CON ;Turn CCP module off MOVLW NEW_CAPT_PS ;Load the W reg with ; the new prescaler ; mode value and CCP ON MOVWF CCP1CON ;Load CCP1CON with this ; value RC2/CCP1 Pin Prescaler 1, 4, 16 and edge detect Q s Set flag bit CCP1IF (PIR1<2>) CCP1CON<3:0> Capture Enable CCPR1H TMR1H CCPR1L TMR1L Q RC2/CCP1 Pin TRISC<2> Output Enable Special Event (1) S R Trigger Output Logic CCP1CON<3:0> Mode Select Set flag bit CCP1IF (PIR1<2>) match CCPR1H Comparator TMR1H CCPR1L TMR1L Note 1: For CCP1 (if enabled), reset Timer1. For CCP2 (if enabled), reset Timer1, and set bit GO/ DONE (ADCON0<2>), which starts an A/D conversion Microchip Technology Inc. DS30390B-J00 - page 73

74 PIC16C7X Duty cycle registers CCPRxL CCPRxH (Slave) Comparator TMR2 Comparator PR2 (Note 1) Clear Timer, CCP1 pin and latch Duty Cycle CCPxCON<5:4> R S Q TRISC<y> RCy/CCPx Pin Note 1: 8-bit timer is concatenated with 2-bit internal Q clock or 2-bits of the prescaler to create 10-bit time-base. DS30390B-J00 - page Microchip Technology Inc.

75 PIC16C7X 1996 Microchip Technology Inc. DS30390B-J00 - page 75

76 PIC16C7X DS30390B-J00 - page Microchip Technology Inc.

77 PIC16C7X U-0 U-0 R-0 R-0 R-0 R-0 R-0 R D/A P S R/W UA BF R = W= bit7 bit0 U = - n = 1996 Microchip Technology Inc. DS30390B-J00 - page 77

78 PIC16C7X R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit7 bit0 R = W= U = - n = DS30390B-J00 - page Microchip Technology Inc.

79 PIC16C7X BSF STATUS,RP0 ;Specify Bank 1 LOOP BTFSS SSPSTAT,BF ;Has data been ;received ;(transmit ;complete)? GOTO LOOP ;No BCF STATUS,RP0 ;Specify Bank 0 MOVF SSPBUF,W ;W reg = contents ; of SSPBUF MOVWF RXDATA ;Save in user RAM MOVF TXDATA,W ;W reg = contents ; of TXDATA MOVWF SSPBUF ;New data to xmit SDI SDO SS SCK Read SS bit0 SSPBUF reg Control Enable Edge Select SSPSR reg 2 Clock Select SSPM3:SSPM0 Edge Select 4 Write shift clock Internal data bus TMR2 output 2 Prescaler 4, 16, 64 Data from TX/RX in SSPSR TRISC<3> T CY 1996 Microchip Technology Inc. DS30390B-J00 - page 79

80 PIC16C7X SPI Master (SSPM3:SSPM0 = 00xxb) SPI Slave (SSPM3:SSPM0 = 010xb ) SDO SDI Serial Input Buffer (SSPBUF) Serial Input Buffer (SSPBUF) Shift Register (SSPSR) SDI SDO Shift Register (SSPSR) MSb LSb MSb LSb SCK Serial Clock SCK PROCESSOR 1 PROCESSOR 2 DS30390B-J00 - page Microchip Technology Inc.

81 PIC16C7X SCK (CKP = 0) SCK (CKP = 1) SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDI SSPIF Interrupt flag bit7 bit0 SS SCK (CKP = 0) SCK (CKP = 1) SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDI bit7 bit0 SSPIF 1996 Microchip Technology Inc. DS30390B-J00 - page 81

82 PIC16C7X DS30390B-J00 - page Microchip Technology Inc.

83 SDA SCL S Start Condition Change of Data Allowed PIC16C7X Change of Data Allowed P Stop Condition 1996 Microchip Technology Inc. DS30390B-J00 - page 83

84 PIC16C7X MSb LSb S R/W ACK S R/W ACK Start Condition Read/Write pulse Acknowledge slave address Sent by Slave Data Output by Transmitter Data Output by Receiver SCL from Master S Start Condition 1 2 not acknowledge acknowledge 8 9 Clock Pulse for Acknowledgment S A9 A8 R/W ACK S R/W ACK - Start Condition - Read/Write Pulse - Acknowledge A7 A6 A5 A4 A3 A2 A1 A0 ACK sent by slave = 0 for write SDA SCL S Start Condition MSB 1 2 acknowledgment signal from receiver 7 Address R/W ACK 8 9 byte complete interrupt with receiver Wait State clock line held low while interrupts are serviced 1 2 Data acknowledgment signal from receiver ACK P Stop Condition DS30390B-J00 - page Microchip Technology Inc.

85 PIC16C7X For 7-bit address: S Slave Address R/W A Data A Data A/A P '0' (write) data transferred (n bytes - acknowledge) A master transmitter addresses a slave receiver with a 7-bit address. The transfer direction is not changed. From master to slave From slave to master A = acknowledge (SDA low) A = not acknowledge (SDA high) S = Start Condition P = Stop Condition For 10-bit address: S Slave Address R/W A1 Slave Address First 7 bits Second byte A2 (write) Data A Data A/A P A master transmitter addresses a slave receiver with a 10-bit address. For 7-bit address: S Slave Address R/W A Data A Data A '1' (read) P data transferred (n bytes - acknowledge) A master reads a slave immediately after the first byte. From master to slave From slave to master A = acknowledge (SDA low) A = not acknowledge (SDA high) S = Start Condition P = Stop Condition (read or write) (n bytes + acknowledge) For 10-bit address: S Slave Address R/W A1 Slave Address First 7 bits Second byte A2 (write) SrSlave Address R/W First 7 bits A3 Data A Data A P (read) A master transmitter addresses a slave receiver with a 10-bit address. S Slave Address R/W A Data A/A Sr Slave Address R/W A Data A/A P (read) Sr = repeated Start Condition (write) Direction of transfer may change at this point Transfer direction of data and acknowledgment bits depends on R/W bits. Combined format: SrSlave Address R/W First 7 bits (write) A Slave Address Second byte A Data A Data A/A Sr Slave Address R/W A Data First 7 bits (read) A Data A P Combined format - A master addresses a slave with a 10-bit address, then transmits data to this slave and reads data from this slave. From master to slave From slave to master A = acknowledge (SDA low) A = not acknowledge (SDA high) S = Start Condition P = Stop Condition 1996 Microchip Technology Inc. DS30390B-J00 - page 85

86 PIC16C7X DATA 1 transmitter 1 loses arbitration DATA 1 SDA wait state start counting HIGH period DATA 2 SDA SCL CLK 1 CLK 2 counter reset SCL DS30390B-J00 - page Microchip Technology Inc.

87 PIC16C7X RC3/SCK/SCL RC4/ SDI/ SDA Read shift clock MSb SSPBUF reg SSPSR reg Match detect SSPADD reg Start and Stop bit detect LSb Write Internal data bus Addr Match Set, Reset S, P bits (SSPSTAT reg) 1996 Microchip Technology Inc. DS30390B-J00 - page 87

88 PIC16C7X DS30390B-J00 - page Microchip Technology Inc.

89 PIC16C7X SDA A7 Receiving Address A6 A5 A4 A3 A2 R/W=0 ACK A1 D7 D6 Receiving Data D5 D4 D3 D2 D1 ACK D0 D7 D6 Receiving Data D5 D4 D3 D2 D1 ACK D0 SCL S P SSPIF (PIR1<3>) BF (SSPSTAT<0>) SSPOV (SSPCON<6>) Cleared in software SSPBUF register is read Bit SSPOV is set because the SSPBUF register is still full. ACK is not sent. Bus Master terminates transfer 1996 Microchip Technology Inc. DS30390B-J00 - page 89

90 PIC16C7X SDA A7 A6 Receiving Address A5 A4 A3 A2 R/W = 1 A1 ACK D7 D6 D5 D4 Transmitting Data D3 D2 D1 D0 ACK SCL S SSPIF (PIR1<3>) 1 2 Data in sampled SCL held low while CPU responds to SSPIF P BF (SSPSTAT<0>) cleared in software SSPBUF is written in software From SSP interrupt service routine CKP (SSPCON<4>) Set bit after writing to SSPBUF DS30390B-J00 - page Microchip Technology Inc.

91 PIC16C7X 1996 Microchip Technology Inc. DS30390B-J00 - page 91

92 PIC16C7X IDLE_MODE (7-bit): if (Addr_match ) { Set interrupt; if (R/W = 1) { Send ACK = 0; set XMIT_MODE; } else if (R/W = 0) set RCV_MODE; } RCV_MODE: if ((SSPBUF=Full) OR (SSPOV = 1)) { Set SSPOV; Do not acknowledge; } else { transfer SSPSR SSPBUF; send ACK = 0; } Receive 8-bits in SSPSR; Set interrupt; XMIT_MODE: While ((SSPBUF = Empty) AND (CKP=0)) Hold SCL Low; Send byte; Set interrupt; if ( ACK Received = 1) { End of transmission; Go back to IDLE_MODE; } else if ( ACK Received = 0) Go back to XMIT_MODE; IDLE_MODE (10-Bit): If (High_byte_addr_match AND (R/W = 0)) { PRIOR_ADDR_MATCH = FALSE; Set interrupt; if ((SSPBUF = Full) OR ((SSPOV = 1)) { Set SSPOV; Do not acknowledge; } else { Set UA = 1; Send ACK = 0; While (SSPADD not updated) Hold SCL low; Clear UA = 0; Receive Low_addr_byte; Set interrupt; Set UA = 1; If (Low_byte_addr_match) { PRIOR_ADDR_MATCH = TRUE; Send ACK = 0; while (SSPADD not updated) Hold SCL low; Clear UA = 0; Set RCV_MODE; } } } else if (High_byte_addr_match AND (R/W = 1) { if (PRIOR_ADDR_MATCH) { send ACK = 0; set XMIT_MODE; } else PRIOR_ADDR_MATCH = FALSE; } DS30390B-J00 - page Microchip Technology Inc.

93 PIC16C7X bit 7: bit 6 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN SYNC - BRGH TRMT TX9D bit7 bit0 bit 5 bit 4 bit 3 bit 2 bit 1 bit Microchip Technology Inc. DS30390B-J00 - page 93

94 PIC16C7X R/W-0 R/W-0 R/W-0 R/W-0 U-0 R-0 R-0 R-x SPEN RX9 SREN CREN - FERR OERR RX9D bit7 bit0 bit 7: bit 6: bit 5: bit 4: bit 3: bit 2: bit 1: bit 0: DS30390B-J00 - page Microchip Technology Inc.

95 PIC16C7X Desired Baud rate = Fosc / (64 (X + 1)) 9600 = /(64 (X + 1)) X = ë25.042û = 25 Calculated Baud Rate = / (64 (25 + 1)) = 9615 Error = (Calculated Baud Rate - Desired Baud Rate) Desired Baud Rate = ( ) / 9600 = 0.16% x =, - = 1996 Microchip Technology Inc. DS30390B-J00 - page 95

96 PIC16C7X DS30390B-J00 - page Microchip Technology Inc.

97 PIC16C7X 1996 Microchip Technology Inc. DS30390B-J00 - page 97

98 PIC16C7X RX (RC7/RX/DT pin) baud CLK Start bit Baud CLK for all but start bit Bit0 x16 CLK Samples RX pin Start Bit bit0 bit1 baud clk First falling edge after RX pin goes low Second rising edge x4 clk Q2, Q4 clk Samples Samples Samples RX pin Start Bit bit0 baud clk x4 clk Q2, Q4 clk First falling edge after RX pin goes low Second rising edge 1 2 Baud clk for all but start bit 3 4 Samples DS30390B-J00 - page Microchip Technology Inc.

99 PIC16C7X Data Bus TXIE Interrupt TXIF MSb (8) TXREG register 8 TSR register LSb 0 Pin Buffer and Control RC6/TX/CK pin TXEN Baud Rate CLK TRMT SPEN SPBRG Baud Rate Generator TX9D TX Microchip Technology Inc. DS30390B-J00 - page 99

100 PIC16C7X Write to TXREG BRG output (shift clock) Word 1 RC6/TX/CK (pin) TXIF bit (Transmit buffer reg. empty flag) Start Bit Bit 0 Bit 1 WORD 1 Bit 7/8 Stop Bit TRMT bit (Transmit shift reg. empty flag) WORD 1 Transmit Shift Reg Write to TXREG BRG output (shift clock) Word 1 Word 2 RC6/TX/CK (pin) TXIF bit (interrupt reg. flag) Start Bit Bit 0 Bit 1 WORD 1 Bit 7/8 Stop Bit Start Bit WORD 2 Bit 0 TRMT bit (Transmit shift reg. empty flag) WORD 1 Transmit Shift Reg. WORD 2 Transmit Shift Reg. Note: This timing diagram shows two consecutive transmissions. DS30390B-J00 - page Microchip Technology Inc.

101 PIC16C7X x64 Baud Rate CLK CREN OERR FERR SPBRG Baud Rate Generator 64 or 16 MSb Stop (8) 7 RSR register 1 0 LSb Start RC7/RX/DT Pin Buffer and Control Data Recovery RX9 SPEN RX9D RCREG register FIFO 8 Interrupt RCIF RCIE Data Bus RX (pin) Rcv shift reg Rcv buffer reg Read Rcv buffer reg RCREG Start bit bit0 bit1 bit7/8 Stop bit Start bit WORD 1 RCREG bit0 bit7/8 WORD 2 RCREG Stop bit Start bit bit7/8 Stop bit RCIF (interrupt flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set Microchip Technology Inc. DS30390B-J00 - page 101

102 PIC16C7X DS30390B-J00 - page Microchip Technology Inc.

103 PIC16C7X 1996 Microchip Technology Inc. DS30390B-J00 - page 103

104 PIC16C7X Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 RC7/RX/DT pin RC6/TX/CK pin Bit 0 Bit 1 WORD 1 Bit 2 Bit 7 Bit 0 Bit 1 WORD 2 Bit 7 Write to TXREG reg TXIF bit (Interrupt flag) Write word1 Write word2 TRMT bit TRMT TXEN bit '1' '1' Note: Sync master mode; SPBRG = '0'. Continuous transmission of two 8-bit words RC7/RX/DT pin bit0 bit1 bit2 bit6 bit7 RC6/TX/CK pin Write to TXREG reg TXIF bit TRMT bit DS30390B-J00 - page Microchip Technology Inc.

105 PIC16C7X 1996 Microchip Technology Inc. DS30390B-J00 - page 105

106 PIC16C7X Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 DT pin bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 CK pin Write to SREN bit SREN bit CREN bit '0' '0' RCIF bit (interrupt) Read RXREG Note: Timing diagram demonstrates SYNC master mode with SREN = '1' and BRG = '0'. DS30390B-J00 - page Microchip Technology Inc.

107 PIC16C7X 1996 Microchip Technology Inc. DS30390B-J00 - page 107

108 PIC16C7X DS30390B-J00 - page Microchip Technology Inc.

109 PIC16C7X R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCS1 ADCS0 - (1) CHS1 CHS0 GO/DONE ADIF ADON bit7 bit Microchip Technology Inc. DS30390B-J00-page 109

110 PIC16C7X R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE - ADON bit7 bit0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W PCFG1 PCFG0 bit7 bit0 bit 7-2: bit 1-0: PCFG1:PCFG0: PCFG1:PCFG0 RA1 & RA0 RA2 RA3 VREF 00 A A A VDD 01 A A VREF RA3 10 A D D VDD 11 D D D VDD A = D = DS30390B-J00-page Microchip Technology Inc.

111 PIC16C7X U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W PCFG2 PCFG1 PCFG0 bit7 bit0 bit 7-3: bit 2-0: PCFG2:PCFG0: PCFG2:PCFG0 RA0 RA1 RA2 RA5 RA3 RE0 RE1 RE2 VREF 000 A A A A A A A A VDD 001 A A A A VREF A A A RA3 010 A A A A A D D D VDD 011 A A A A VREF D D D RA3 100 A A D D A D D D VDD 101 A A D D VREF D D D RA3 11x D D D D D D D D - A = D = 1996 Microchip Technology Inc. DS30390B-J00-page 111

112 PIC16C7X CHS1:CHS0 VIN (Input voltage) RA3/AN3/VREF RA2/AN2 A/D Converter RA1/AN1 RA0/AN0 VREF VDD 00 or 10 or 11 (Reference voltage) PCFG1:PCFG0 01 DS30390B-J00-page Microchip Technology Inc.

113 PIC16C7X CHS2:CHS0 VIN (Input voltage) RE2/AN7(1) RE1/AN6(1) RE0/AN5(1) RA5/AN4 RA3/AN3/VREF RA2/AN2 A/D Converter RA1/AN1 RA0/AN0 VREF VDD 000 or 010 or 100 (Reference 001 or voltage) 011 or 101 PCFG2:PCFG Microchip Technology Inc. DS30390B-J00-page 113

114 PIC16C7X Vhold = (Vref - (Vref/512)) x (1 - e (-Tc/CHOLD(RIC + R SS + RS)) ) Tc = -(51.2 pf)(1 kw + Rss + Rs) ln(1/511) Rs = 10 kω 1/2 LSb error Vdd = 5V Rss = 7 kω Temp (system max.) = 50 C Vhold = t = 0 TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient TACQ = 5 µs + Tc + [(Temp - 25 )(0.05 ms/ )] Tc = -Chold (RIC + Rss + Rs) ln(1/512) pf (1 kω + 7 kω + 10 kω) ln(0.0020) pf (18 kω) ln(0.0020) µs ( ) µs TACQ = 5 µs µs + [(50-25 )(0.05 µs/ )] µs µs µs Rs VDD VT=0.6V RIC 1k Sampling Switch SS Rss VA CPIN 5nF VT=0.6V I leakage 500 na CHOLD = DAC capacitance = 51.2pF VSS 6V 5V VDD 4V 3V 2V Sampling Switch DS30390B-J00-page Microchip Technology Inc.

115 PIC16C7X 1996 Microchip Technology Inc. DS30390B-J00-page 115

116 PIC16C7X BSF STATUS,RP0 ; Select Page 1 CLRF ADCON1 ; Configure A/D inputs BCF STATUS,RP0 ; Select Page 0 MOVLW 0xC1 ; RC Clock, A/D is on, Channel 0 is selected MOVWF ADCON0 ; BSF INTCON,ADIE ; Enable A/D Interrupt BSF INTCON,GIE ; Enable all interrupts ; ; Ensure that the required sampling time for the selected input channel has elapsed. ; Then the conversion may be started. ; BSF ADCON0,GO ; Start A/D Conversion : ; The ADIF bit will be set and the GO/DONE bit : ; is cleared upon completion of the A/D Conversion. BSF STATUS,RP0 ; Select Page 1 CLRF ADCON1 ; Configure A/D inputs BSF PIE1,ADIE ; Enable A/D interrupts BCF STATUS,RP0 ; Select Page 0 MOVLW 0xC1 ; RC Clock, A/D is on, Channel 0 is selected MOVWF ADCON0 ; BCF PIR1,ADIF ; Clear A/D interrupt flag bit BSF INTCON,PEIE ; Enable peripheral interrupts BSF INTCON,GIE ; Enable all interrupts ; ; Ensure that the required sampling time for the selected input channel has elapsed. ; Then the conversion may be started. ; BSF ADCON0,GO ; Start A/D Conversion : ; The ADIF bit will be set and the GO/DONE bit : ; is cleared upon completion of the A/D Conversion. DS30390B-J00-page Microchip Technology Inc.

117 PIC16C7X = 2Tad + N TAD + (8 - N)(2Tosc) : N = Freq. (MHz) (1) 4-bit 8-bit TAD µs 1.6 µs µs 2.0 µs TOSC ns 50 ns ns 62.5 ns 2Tad + N TAD + (8 - N)(2Tosc) µs 16 µs µs 20 µs 1996 Microchip Technology Inc. DS30390B-J00-page 117

118 PIC16C7X DS30390B-J00-page Microchip Technology Inc.

119 PIC16C7X FFh Digital code output FBh 04h 03h 02h 01h 00h 0.5LSb 1LSb 2LSb 3LSb 4LSb Analog input voltage 255LSb 256LSb (full scale) ADON =0 ADON =0? Acquire Selected Channel GO = 0? Yes No A/D Clock = RC? Yes Start of A/D Conversion Delayed 1 Instruction Cycle SLEEP Yes Instruction? Finish Conversion GO = 0 ADIF = 1 No No Device in SLEEP? Yes Abort Conversion GO = 0 ADIF = 0 Finish Conversion GO = 0 ADIF = 1 Wake-up Yes From Sleep? Wait 2 TAD No No Finish Conversion GO = 0 ADIF = 1 SLEEP Power-down A/D Wait 2 TAD Stay in Sleep Power-down A/D Wait 2 TAD 1996 Microchip Technology Inc. DS30390B-J00-page 119

120 PIC16C7X DS30390B-J00-page Microchip Technology Inc.

121 PIC16C7X CP0 PWRTE WDTE F0SC1 F0SC0 bit13 bit0 Register: Address CONFIG 2007h bit 13-5: bit 4: bit 3: bit 2: bit 1-0: 1996 Microchip Technology Inc. DS30390B-J00-page 121

122 PIC16C7X CP0 CP0 CP0 CP0 CP0 CP0 CP0 BODEN CP0 CP0 PWRTE WDTE F0SC1 F0SC0 Register: CONFIG bit13 bit0 Address 2007h bit 13-7: CP0: 5-4: bit 6: BODEN: bit 3: PWRTE: bit 2: WDTE: bit 1-0: FOSC1:FOSC0: PWRTEPWRT CP1 CP0 PWRTE WDTE F0SC1 F0SC0 bit13 bit0 Register: Address CONFIG 2007h bit 13-5: bit 4: bit 3: bit 2: bit 1-0: CP1:CP0: PWRTE: WDTE: FOSC1:FOSC0: DS30390B-J00-page Microchip Technology Inc.

123 PIC16C7X CP1 CP0 CP1 CP0 CP1 CP0 - BODEN CP1 CP0 PWRTE WDTE F0SC1 F0SC0 bit3 bit 13-8 CP1:CP0: 5-4: bit 7: : bit 6: BODEN: bit 3: PWRTE: bit 2: WDTE: bit 1-0: FOSC1:FOSC0: bit0 Register: CONFIG Address 2007h C1 C2 XTAL Clock from ext. system OSC2 RF Note1 OSC1 Open RF OSC1 OSC2 (2) (2) To internal logic SLEEP PIC16CXX To internal logic PIC16CXX 1996 Microchip Technology Inc. DS30390B-J00-page 123

124 PIC16C7X DS30390B-J00-page Microchip Technology Inc.

125 PIC16C7X 10k +5V 20pF 4.7k 74AS04 XTAL 20pF 74AS04 10k PIC16CXX CLKIN VDD Rext Cext Vss OSC1 Internal clock PIC16CXX 330k 74AS04 330k 74AS04 74AS04 To Other Devices PIC16CXX Fosc/4 OSC2/CLKOUT 0.1uF CLKIN XTAL 1996 Microchip Technology Inc. DS30390B-J00-page 125

126 PIC16C7X External Reset MCLR VDD WDT Module VDD rise detect Brown-out Reset (2) WDT SLEEP Time-out Reset Power-on Reset BODEN S OST/PWRT OSC1 OST 10-bit Ripple counter R Q Chip_Reset On-chip (1) RC OSC PWRT 10-bit Ripple counter Enable PWRT Enable OST DS30390B-J00-page Microchip Technology Inc.

127 PIC16C7X VDD BVDD Max. BVDD Min. Internal Reset 72ms VDD BVDD Max. BVDD Min. Internal Reset <72ms 72ms VDD BVDD Max. BVDD Min. Internal Reset 72ms 1996 Microchip Technology Inc. DS30390B-J00-page 127

128 PIC16C7X DS30390B-J00-page Microchip Technology Inc.

129 PIC16C7X 1996 Microchip Technology Inc. DS30390B-J00-page 129

130 PIC16C7X DS30390B-J00-page Microchip Technology Inc.

131 PIC16C7X VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET 1996 Microchip Technology Inc. DS30390B-J00-page 131

132 PIC16C7X VDD D R C R1 MCLR PIC16CXX VDD 33k 10k 40k VDD MCLR PIC16CXX VDD R1 R2 Q1 40k VDD MCLR PIC16CXX R V 1 DD = R 1 + R V DS30390B-J00-page Microchip Technology Inc.

133 PIC16C7X 1996 Microchip Technology Inc. DS30390B-J00 - page 133

134 PIC16C7X T0IF T0IE INTF INTE RBIF RBIE Wakeup (If in SLEEP mode) Interrupt to CPU ADIF ADIE GIE TMR1F TMR1E TMR2IF TMR2IE ADIF ADIE T0IE T0IF INTE INTF RBIE RBIF PEIE PEIF GIE Wakeup (If in SLEEP mode) Interrupt to CPU SSPIF SSPIE CCP1IF CCP1IE TMR1F TMR1E TMR2IF TMR2IE CCP1IF CCP1IE CCP2IF CCP2IE T0IE T0IF INTE INTF RBIE RBIF Wakeup (If in SLEEP mode) Interrupt to CPU RCIF RCIE ADIF ADIE TXIF TXIE PEIE PEIF GIE SSPIF SSPIE DS30390B-J00 - page Microchip Technology Inc.

135 PIC16C7X TMR1F TMR1E TMR2IF TMR2IE CCP1IF CCP1IE CCP2IF CCP2IE T0IE T0IF INTE INTF RBIE RBIF Wakeup (If in SLEEP mode) Interrupt to CPU ADIF ADIE TXIF TXIE PEIE PEIF GIE RCIF RCIE SSPIF SSPIE PSPIF PSPIE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT 3 INT pin 4 INTF flag (INTCON<1>) Interrupt Latency 2 GIE bit (INTCON<7>) INSTRUCTION FLOW PC PC PC+1 PC h 0005h Instruction fetched Inst(PC) Inst(PC+1) - Inst(0004h) Inst(0005h) Instruction executed Inst(PC-1) Inst(PC) Dummy Cycle Dummy Cycle Inst(0004h) 1996 Microchip Technology Inc. DS30390B-J00 - page 135

136 PIC16C7X MOVWF W_TEMP ; Copy W to TEMP register, could be bank one or zero SWAPF STATUS,W ; Swap status to be saved into W CLRF STATUS ; bank 0, regardless of current bank, Clears IRP,RP1,RP0 MOVWF STATUS_TEMP ; Save status to bank zero STATUS_TEMP register MOVF PCLATH, W ; Only required if using pages 1, 2 and/or 3 MOVWF PCLATH_TEMP ; Save PCLATH into W CLRF PCLATH ; Page zero, regardless of current page MOVF FSR, W ; Copy FSR to W MOVWF FSR_TEMP ; Copy FSR from W to FSR_TEMP : : (ISR) : MOVF FSR_TEMP, W ; Restore FSR MOVWF FSR ; Move W to FSR MOVF PCLATH_TEMP, W ; Restore PCLATH MOVWF PCLATH ; Move W into PCLATH SWAPF STATUS_TEMP,W ; Swap STATUS_TEMP register into W ; (sets bank to original state) MOVWF STATUS ; Move W into STATUS register SWAPF W_TEMP,F ; Swap W_TEMP SWAPF W_TEMP,W ; Swap W_TEMP into W DS30390B-J00 - page Microchip Technology Inc.

137 PIC16C7X From TMR0 Clock Source (Figure 7-6) WDT Timer 0 1 M U X Postscaler to - 1 MUX PS2:PS0 WDT Enable Bit PSA To TMR0 (Figure 7-6) 0 1 MUX PSA WDT Time-out 1996 Microchip Technology Inc. DS30390B-J00 - page 137

138 PIC16C7X DS30390B-J00 - page Microchip Technology Inc.

139 PIC16C7X Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT 3 TOST(2) INT pin INTF flag (INTCON<1>) Interrupt Latency (Note2) GIE bit (INTCON<7>) INSTRUCTION FLOW Processor in SLEEP PC PC PC+1 PC+2 PC+2 PC h 0005h Instruction fetched Inst(PC) = SLEEP Inst(PC+1) Inst(PC+2) Inst(0004h) Inst(0005h) Instruction executed Inst(PC-1) SLEEP Inst(PC+1) Dummy cycle Dummy cycle Inst(0004h) External Connection Signals +5V 0V VPP CLK Data I/O To Normal Connections To Normal Connections PIC16XX VDD VSS MCLR/VPP RB6 RB7 VDD 1996 Microchip Technology Inc. DS30390B-J00 - page 139

140 PIC16C7X DS30390B-J00 - page Microchip Technology Inc.

141 PIC16C7X OPCODE d f(file #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations OPCODE b(bit #) f(file #) b = 3-bit bit address f = 7-bit file register address Literal and control operations OPCODE k (LITERAL) k = 8-bit immediate value. Literal and control operations OPCODE k (LITERAL) k = 8-bit immediate value Microchip Technology Inc. DS30390B-J00 - page 141

142 PIC16C7X msb lsb ADDWF f, d Add W and f dfff ffff C, DC, Z 1, 2 ANDWF f, d AND W and f dfff ffff Z 1, 2 CLRF f Clear f fff ffff Z 2 CLRW - Clear W xxx xxxx Z COMF f, d Complement f dfff ffff Z 1, 2 DECF f, d Decrement f dfff ffff Z 1, 2 DECFSZ f, d Decrement f, Skip if 0 1 (2) dfff ffff 1, 2, 3 INCF f, d Increment f dfff ffff Z 1, 2 INCFSZ f, d Increment f, Skip if 0 1 (2) dfff ffff 1, 2, 3 IORWF f, d Inclusive OR W and f dfff ffff Z 1, 2 MOVF f, d Move f dfff ffff Z 1, 2 MOVWF f Move W to f fff ffff NOP - No Operation xx RLF f, d Rotate left f through carry dfff ffff C 1, 2 RRF f, d Rotate right f through carry dfff ffff C 1, 2 SUBWF f, d Subtract W from f dfff ffff C, DC, Z 1, 2 SWAPF f, d Swap halves f dfff ffff 1, 2 XORWF f, d Exclusive OR W and f dfff ffff Z 1, 2 BCF f, b Bit Clear f bb bfff ffff 1, 2 BSF f, b Bit Set f bb bfff ffff 1, 2 BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 3 BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 3 ADDLW k Add literal to W x kkkk kkkk C, DC, Z ANDLW k AND literal to W kkkk kkkk Z CALL k Call subroutine kkk kkkk kkkk CLRWDT - Clear watchdog timer TO, PD GOTO k Go to address kkk kkkk kkkk IORLW k Inclusive OR literal to W kkkk kkkk Z MOVLW k Move literal to W xx kkkk kkkk RETFIE - Return from interrupt RETLW k Return with literal in W xx kkkk kkkk RETURN - Return from subroutine SLEEP - Go into standby mode TO, PD SUBLW k Subtract W from literal x kkkk kkkk C, DC, Z XORLW k Excl. OR literal to W kkkk kkkk Z DS30390B-J00 - page Microchip Technology Inc.