DAシンポ2003_SLD研_発表原稿
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1 DA JEITA SLD - JEITA E D A S L D NEC Copyright JEITA, All rights reserved
2 SLD Copyright JEITA, All rights reserved 3
3 SLD JEITA EDA (JEITA) EDA System Level Design SLD Physical Design Methodology PDM EDS Fair Copyright JEITA, All rights reserved 4
4 SLD EDA Copyright JEITA, All rights reserved 5
5 SLD SLD /EDA Copyright JEITA, All rights reserved 6
6 Copyright JEITA, All rights reserved SLDL(Rosetta) SystemC SpecC UML SLD (ASP -DAC) WS ( HW SW
7 Copyright JEITA, All rights reserved 9 HW/SW RTL I P I P D B HW I P I/F I P I P SW I P D B [SLD-5,6] 1999/12~2001/3
8 WS 2000/11 1. / IP Copyright JEITA, All rights reserved 10
9 ~2002/3 I/F Accellera GSRC IMEC STARC / SYDIC Copyright JEITA, All rights reserved 11 VSIA [SLD-4]
10 WS 2000/11 (2003/7 1. / IP EDA PSL Accellera) EDA SystemC OSCI), SystemVerilog Accellera) EDA SystemC OSCISynthesisWG Copyright JEITA, All rights reserved 12
11 WS 2000/11 1. / IMEC, GSRC, STARC 2. T G IP TG I/F TG EDA Copyright JEITA, All rights reserved 13
12 / HW/SW Copyright JEITA, All rights reserved 14
13 / / Copyright JEITA, All rights reserved 15
14 [SLD-5,6] HW/SW D B I P I P I P D B SW I P I/F I P HW I P S L D Copyright JEITA, All rights reserved 16
15 [SLD-5,6] HW/SW HW/SW D B I P I P I P D B SW I P I/F I P HW I P S L D Copyright JEITA, All rights reserved 17
16 HWSW Copyright JEITA, All rights reserved 18
17 Copyright JEITA, All rights reserved 19 HW/SW I P I P D B HW I P I/F I P I P SW I P D B [SLD-5,6] HW/SW HW
18 Copyright JEITA, All rights reserved HW/SW HW/SW I P I P D B HW I P I/F I P I P SW I P D B [SLD-5,6] HW/SW
19 3.1 HW/SW HW/SW HW/SW HW/SW HW/SW OS HW/SW?? Copyright JEITA, All rights reserved 22
20 HW/SW HW/SW HW/SW HW/SW HW/SW HW/SW HW/SW Copyright JEITA, All rights reserved 23
21 HW/SW HW/SW [ Co-sim 1-7 ] Copyright JEITA, All rights reserved 24
22 HW/SW SW HW Host Native Target Code + ISS Target Code + Cycle Accurate ISS Target Code + Processor RTL Model Abstract Function Layer Model Transaction Layer Model Transfer Layer Model RTL Model Copyright JEITA, All rights reserved 25
23 HW/SW Copyright JEITA, All rights reserved 26
24 HW/SW :99 AI : 304 HW/SW ( ) Copyright JEITA, All rights reserved 27
25 ( AI ) Copyright JEITA, All rights reserved 28
26 HW/SW HW/SW HW/SW Copyright JEITA, All rights reserved 29
27 Copyright JEITA, All rights reserved HW/SW I P I P D B HW I P I/F I P I P SW I P D B [SLD-5,6]
28 3.2 C C RTL EDA 6 Copyright JEITA, All rights reserved 31
29 RT RT UnTimed Function for( i=0; i<7; i++){ a = b * c; d = e * f; g = a + d; } Cycle Accurate for( i=0; i<7; i++){ a = b * c; clock(); d = e * f; clock(); g = a + d; clock(); } RT ( clk) current_state <= next_state; or ) case( current_state) s1 : i=0; a = b * c; i=i+1; flag=(i <7); next_state = s2; s2 : if( flag==1){ d = e * f; next_state = s3; } else{ next_state = s1; }. Copyright JEITA, All rights reserved 32
30 RTL C Copyright JEITA, All rights reserved 33
31 Copyright JEITA, All rights reserved 34
32 Copyright JEITA, All rights reserved 35
33 Copyright JEITA, All rights reserved 36
34 func1(); for( i =0; i < 10; i++ ){ a[i] = b[i] *c[i]; } for( i =0; i < 10; i++ ){ d[i] = e[i] *f[i]; } func2(); for C RTL func2() for VerilogHDLforkjoin Copyright JEITA, All rights reserved 37
35 for( i=0; i < 10; i++){ en1 = func1(i); en2 = func2(i); func3(en1); func4(en2); } func3() func4() RTL func3() func4() Copyright JEITA, All rights reserved 38
36 for( i =0; i <10; i++ ){ a = x * i; b = y * i; c[i] = b*2; } for( i=0; i < 10; i++ ){ func1(); func2(); func3(); } Copyright JEITA, All rights reserved 39
37 for( i=0; i < 10; i++){ en1 = func1(i); en2 = func2(i); func3(en1); func4(en2); } for( i =0; i < 10; i++ ){ a[i] = b[i] *c[i]; } for( i =0; i < 10; i++ ){ d[i] = e[i] *f[i]; } Copyright JEITA, All rights reserved 40
38 C Copyright JEITA, All rights reserved 41
39 Copyright JEITA, All rights reserved HW/SW I P I P D B HW I P I/F I P I P SW I P D B [SLD-5,6] HW
40 3.3 ( 70% ) RT Copyright JEITA, All rights reserved 43
41 [HV 2] [HV 3] HDL / Copyright JEITA, All rights reserved 44
42 PSL) w r_n ena_nhigh / / psl assert always wr_n); //p s l P S L ; Vendor PSL: Property Specification Language ( Sugar) [HV 5] Copyright JEITA, All rights reserved 45
43 ( ) Copyright JEITA, All rights reserved 46
44 IP Copyright JEITA, All rights reserved 47
45 OVA: OpenVera Assertion, OVL: Open Verification Library, PSL: Property Specification Language, SVA: SystemVerilog Assert ion Copyright JEITA, All rights reserved 48
46 Accellera SystemVerilog (Accellera) SystemVerilog3.1 HDVL (Hardware Design and Verification Language) DAC 03 [HV 5] [HV 8] SystemVerilog3.1powerful assertion testbench creation direct C I/F high level abstraction Unified assertions SystemVerilog3.0PSL OVA PSL (Accellera) 2003/1Language Reference ManualPSL SystemVerilog 3.1 Assertion e (IEEE P1647) Verisity 2003/6IEEE ( ) () Copyright JEITA, All rights reserved 49
47 / I P AccelleraSystemVerilog Assertion 3.1 PSL RTL ( ) Copyright JEITA, All rights reserved 51
48 Copyright JEITA, All rights reserved 53 HW/SW I P I P D B HW I P I/F I P I P SW I P D B [SLD-5,6] HW/SW HW/SW HW
49 /EDA / HW/SW HW RTL Copyright JEITA, All rights reserved 54
50 Copyright JEITA, All rights reserved 55
51 Copyright JEITA, All rights reserved 56 SLD HW/SW I P I P D B HW I P I/F I P I P SW I P D B
52 (MoC: Model of Computation) F S M MoC MoC Copyright JEITA, All rights reserved 57
53 MoC KPN P2 Philips SPADE P1 P4 P5 P3 P1 F I F O Copyright JEITA, All rights reserved 58
54 KPN untimed FIFO Copyright JEITA, All rights reserved 59
55 MoC KPN MPEG2 Pieter van der Wolf An MPEG-2 Decoder Case Study as a Driver for a System Level Design Methodology Copyright JEITA, All rights reserved 60
56 MoC Model of Computation Timed MoC Untimed MoC FSM Continuous Time Discrete Event Synchronous Reactive Tagged Signal Model Petri N e t Finite State Machine Discrete Time Synchronous Message Passing Asynchronous Message Passing Multi-Thread Graph Mescal Concurrency Representation Hierarchical Concurrent FSM Abstract CFSM Kahn Process Networks Communicating Sequential Processes Calculus of Communicating Systems Extended CFSM Dataflow Heterochronous DF MoC Co-design FSM Boolean DF Cyclo-Static DF MoC MoC Synchronous DF Homogeneous SDF Copyright JEITA, All rights reserved 64
57 MoC Copyright JEITA, All rights reserved 67
58 MoC KPN DF SDF CSP CFSMs ACFSMs ECFSMs MCR MTG HCFSM FIFO FIFO FIFO FIFO ( F I F O ) FIFO CFSMs : 1 ACFSMs : ECFSMs : FIFO FIFO FIFO FIFO Copyright JEITA, All rights reserved 72
59 Copyright JEITA, All rights reserved 74 MoC HCFSM MTG MCR : : CFSMs ACFSMs ECFSMs CSP SDF DF KPN
60 MoC SLD MoC Copyright JEITA, All rights reserved 76
61 Copyright JEITA, All rights reserved 77 ESTEREL VEM HCFSM MTG CoWare MTG MTG MCR MCR MCR ESTERELVHDL CFSMs ACFSMs ECFSMs CSP CSP DF SDF firing rule KPN K PN DF FIFO KPN
62 KPN DF SDF CSP CFSMs ACFSMs ECFSMs MCR MTG HCFSM CSP CSP CFSM MCR MTG MTG Copyright JEITA, All rights reserved 78
63 KPN/DF MoC SDF DSP CSP CFSMs/ACFSMs/ECFSMs MCR MTG MoC HCFSM Copyright JEITA, All rights reserved 81
64 10MoC / MoC MoC/ MoC /EDA / MoC MoC MoC Copyright JEITA, All rights reserved 82
65 Copyright JEITA, All rights reserved 83
66 SoC SoC SoC 1 / R T L / 1 /2 2 /3 1 /3 1/10 Copyright JEITA, All rights reserved 84
67 L. Benini & G. De Micheli, System-level power optimization: Techniques and Tools, ISLPED99 A) HW/SW partitioning Avalanche B) Instruction -level power optimization DAC 2000 No.18.3 DAC 2000 No.21.1 C) Control-d a t a-flow transformation HW CDFG D) Memory optimization techniques ATOMIUM Copyright JEITA, All rights reserved 85
68 E) Interface power optimization I C C A D D. 1 CODES F) Variable -voltage techniques G) Dynamic power management H ) Approximate signal processing AE Copyright JEITA, All rights reserved 86
69 I. II. III. IV. HW CMOS P= i V dd2 f clk ASIC Copyright JEITA, All rights reserved 87
70 ( H W CPU Copyright JEITA, All rights reserved 88
71 HW SW C CPU Copyright JEITA, All rights reserved 89
72 ( H W CPU A T O M I U M Copyright JEITA, All rights reserved 90
73 Copyright JEITA, All rights reserved 91 ATOMIUM ATOMIUM/Analysis ATOMIUM/Analysis C C ATOMIUM/SBO ATOMIUM/SBO ATOMIUM/MC ATOMIUM/MC ATOMIUM/RACE ATOMIUM/RACE ATOMIUM tools Analysis/SBO/MC/RACE :ATOMIUM 1.2.3(20034 IMEC DEMOAnalysis ATOMIUM tools Analysis/SBO/MC/RACE :ATOMIUM 1.2.3(20034 IMEC DEMOAnalysis imec be/design/multimedia/atomium
74 ATOMIUM MPEG4 40k +120k C ATOMIUM Analysis 3 0 % GSM auto-correlation Medical Imaging MPEG4 motion-compensation ATOMIUM MC5 % 4 0 % Voice -Coding 2k C ATOMIUM MC 71KB 5 5 K B i m e c be/design/multimedia/ atomium Copyright JEITA, All rights reserved 92
75 1 SW H W 1 HW 2 HW HW/SW 2 Copyright JEITA, All rights reserved 93
76 HW/SW Avalanche ( H W CPU HW ORINOCO Power Buster- D Platune Copyright JEITA, All rights reserved 94
77 ORINOCO ChipVision C/C++ VHDL C/C++ VHDL ORINOCO DALE * > + ORINOCO RIO ORINOCO BEACH Presskit Press_Presentation.ppt -Presentation_2_02.pdf ORINOCO yes ok? R T L yes ok? no no Copyright JEITA, All rights reserved 95
78 ORINOCO Copyright JEITA, All rights reserved 96
79 Platune cs ucr edu/~dalton/ cs ucr edu/~vahid/pubs/tcad02_platune_draft pdf MIPS CPU I$ Bus CPU D$ Bus I-Cache D-Cache $ MEM Bus Memory Bridge Peripheral Bus UART DMA DCT CODEC Power S W Power/Performance Model ~ K inst/sec, GateSim>2000x Power GateSim< 10% Copyright JEITA, All rights reserved 97
80 AvalanchePlatune J.Henkel, Yanbing Li. Avalanche: An Environment for Design Space Exploration and Optimization of Low-Power Embedded Systems. IEEE trans on VLSI Vol10. No.4, pp AUGUST 2002 QPT ISS Dinero Platune - ASIC VARCHSYN CYBER CSIM HW Copyright JEITA, All rights reserved 98
81 1 CPU HW/SW 2 CPU HW/SW 3 CPU HW/SW Copyright JEITA, All rights reserved 99
82 1 HW/SW CPU C P U CPU Platune CPU MIPS) HW/SW I/F RTL Platune HW Copyright JEITA, All rights reserved 100
83 2 HW/SW 1 HW HW HW SW HW HW SW HW SW O RINOCO 2 Copyright JEITA, All rights reserved 101
84 3 CPU CPU CPU XX CPU Platune Copyright JEITA, All rights reserved 102
85 DAC ICCAD CODES SLD ATOMIUM C HW Copyright JEITA, All rights reserved 103
86 AvalanchePlatune CPU CPU Platune HW/SW HW/SW HW ORINOCO HW Platune CPU CPU Copyright JEITA, All rights reserved 104
87 EDA DB Copyright JEITA, All rights reserved 105
88 MoC MoC) RTL) MoC Copyright JEITA, All rights reserved 107
89 MoC) RTL) HW/SW HW Copyright JEITA, All rights reserved 108
90 (1) (2) (3) (4) MoC (5) (6) (7) Copyright JEITA, All rights reserved 110
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