Unconventional HDL Programming (20090425 version) 1
1 Introduction HDL HDL Hadware Description Language printf printf (C ) HDL 1 HDL HDL HDL HDL HDL HDL 1 2
2 2.1 VHDL 1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.std_logic_unsigned.all; 4 5 entity rshift_5 is 6 port ( Listing 1: VHDL 7 i : in std_logic_vector(9 downto 0); 8 o : out std_logic_vector(9 downto 0) 9 ); 10 end rshift_5; 11 12 architecture rtl of rshift_5 is 13 begin 14 o <= "00000"&i(9 downto 5); 15 end rtl; HDL VHDL 1 5 bit rshift_5 i o 14 VHDL i o VHDL 7 VHDL i 10 8 o 10 10 (9 downto 0) 9 0 (C 0 ) std_logic_vector 3
14 i o <= VHDL i o <= o 10 10 i(9 downto 5) 10 i 9 5 o i 5 bit o 4 0 i 9 5 o 0 14 "00000" 0 0 5 5 0 VHDL 10 o n o(n) 14 1 o(9) <= 0 ; 2 o(8) <= 0 ; 3 o(7) <= 0 ; 4 o(6) <= 0 ; 5 o(5) <= 0 ; 6 o(4) <= i(9); 7 o(3) <= i(8); 8 o(2) <= i(7); 9 o(1) <= i(6); 10 o(0) <= i(5); Listing 2: VHDL 1 14 1 14 o i 5 bit 2.2 HDL 4
HDL HDL 2.2.1 GHDL HDL GHDL GHDL VHDL CPU Linux CPU x86 64 Linux distribution Debian Lenny Ubuntu 8.04 LTS distribution GHDL GHDL Listing 3: GHDL Ubuntu 8.04 LTS 1 # aptitude install ghdl gtkwave gtkwave http://ghdl.free.fr/ build Ada Windows/Mac OS X GHDL 2.2.2 GHDL GHDL VHDL analyze elaborate analyze -a elaborate -e top.vhd VHDL analyze elaborate Listing 4: analyze elaborate 1 % ghdl -a --ieee=synopsys top.vhd 2 % ghdl -e --ieee=synopsys top 3 %./top 4 % ghdl --gen -makefile --ieee=synopsys top > Makefile analyze elaborate top 3 4 Makefile Makefile make analyze elaborate 5
2.2.3 1 ( rshift.vhd ) 4 Listing 5: rshift.vhd 1 % ghdl -a --ieee=synopsys rshift.vhd 2 % ghdl -e --ieee=synopsys rhisft_5 3 %./rshift_5 1 rshift.vhd main VHDL main main 5 rshift 5 ( ) main rshift 5 1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.std_logic_arith.all; 4 5 entity top is 6 end top; 7 8 architecture rtl of top is 9 10 component rshift_5 11 port ( Listing 6: top 12 i : in std_logic_vector(9 downto 0); 13 o : out std_logic_vector(9 downto 0) 14 ); 15 end component; 16 17 signal input : std_logic_vector(9 downto 0); 18 signal output : std_logic_vector(9 downto 0); 19 20 begin 21 DUT : rshift_5 port map (i = > input, o = > output); 22 input <= "0000100000"; 23 end rtl; 6
top 5-6 entity rshift_5 component( ) 17-18 input output 21 rshift_5 rshift_5 21 DUT VHDL VHDL : rshift_5 port map (i => input, o => output) rshift_5 i o 17-18 i => input o => output <= => main VHDL FPGA ASIC main FPGA ASIC FPGA ASIC ( PCI-Express ) main 2.2.4 6 top.vhd rshift.vhd Listing 7: 1 % ghdl -a --ieee=synopsys rshift.vhd 2 % ghdl -a --ieee=synopsys rshift.vhd 3 % ghdl -e --ieee=synopsys top 4 %./top 7
analyze entity ( 6 5-6 ) elaborate top VHDL <= assertion GHDL 1 %./top --vcd=sim.vcd Listing 8: --vcd= sim.vcd top.vhd rshift.vhd VHDL VHDL 6 17-18 signal input output sim.vcd Value Change Dump(VCD) VCD GHDL gtkwaeve gtkwave sim.vcd VCD VCD rshift_5 rshift_5 5 bit 6 0000100000 5 bit 0000000001 output 0000000001 8
sim.vcd timestamp 1 $date 2 Sun Apr 26 00:00:00 2009 3 $end 4 $version 5 GHDL v0 6 $end 7 $timescale 8 1 fs 9 $end 10 $var reg 10! input[9:0] $end 11 $var reg 10 output[9:0] $end 12 $scope module dut $end 13 $var reg 10 # i[9:0] $end 14 $var reg 10 $ o[9:0] $end 15 $upscope $end 16 $enddefinitions $end 17 #0 18 b0000100000! 19 b0000000001 20 b0000100000 # 21 b0000000001 $ Listing 9: sim.vcd VCD web $var $var (10! ) #0 input 10! 18 b0000100000 b 6 22 output b0000000001 (5 bit ) rshift_5 b0000100000 rshift_5 9
10 bit 1024 VCD VHDL VCD 2.3 VHDL VHDL 1024 5 bit VHDL 2 64 ( 4 10 19 ) ( ) CPU IEEE 754 ( IEEE 754 ) 16 bit HDL HDL 1. 2. HDL 3. HDL 10
HDL HDL HDL HDL HDL 2 C C 64 bit bit 3 to be continued... 4 version 2009/04/25 first draft (C) 2 HDL 11