卒業研究報告.PDF

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1 3 2 9

2 . 2. MOS 2. MOS LED i

3 4. 8bitCPU HDL 4.3. ALU 2 ALU ii

4 . 3 MOS MOS IC 8bitCPU 2. MOS 2. MOS MOS FET MOS FET 2. W L Tox Leff sub 2. MOS FET

5 MOS FET N MOS FET NMOS P MOS FET PMOS N NMOS P PMOS NMOS P PMOS N Al Poly-Si NMOS 0V 5V 0V P Vth 2.2 NMOS a Id Vgs Vds 2.2 2

6 a Id W Vds ( ) LTox 2 ox Id = Vgs-Vth Vds - 2 Vgs Vds Tox ox Vgs Vds 2 Vds Vgs-Vth Id a Vds > Vgs-Vth Id W ox Id = ( Vgs-Vth) 2 LT ox Id Vd 2.3 Tox Cs Cd Cs Vg-Vs-Vth Cd Vg-Vd-Vth Vs 0V Vg Vth Vd Cd Cd Cs Vd = Vg-Vth Vg Vs Vd + n + n p 2.3 3

7 Vd Vd Id 2.2 PMOS NMOS NMOS NMOS m Si s Ef Ec Ev Ei Metal SiO2 Si m s Ec Ef Ei Ef Ev 2.4 4

8 Metal SiO2 Si E a dox dsi Q b x E c x -dox -xo 0 xs dsi q Na dsi d ox si V d q Na d 2 si 2 si -dox -xo 0 xs dsi x 2.5 5

9 (Va) Q 2.5 a SiO2 Si b Si P dox SiO2 dsi Si Na SiO2 SiO2 Si E E Eox SiO2 Esi Si Q E= Q m E = ox ox Qm Si Qsi q Na dsi E ox= 2. ox 2.5 c E x xo -dox 0 xs 0 dsi SiO2 xo Si xs Esi Qsi E si = si q Na (dsi-x s) = 2.2 si x = 0 Eox Esi ox si SiO2 Vox Si Vsi -x 0 o ox ox ox 0 -xo V = - E dx = E dx q Na d 0 si = dx -x o ox 6

10 q Na d si = xo o ox x= d ox q Na d V ox= ox si 2.3 d ox 2.4 qna(d -x ) xs xs si o Vsi = - Edx si = - d dx si dsi xs q Na (dsi-x si ) = dx dsi xi qna = 2 si 2 si 2 (dsi x- x) qna = (d si - x s) 2 2 dsi xs q Na 2 2 = ( dsi- dsi x+ s x) s xs = 0 q Na dsi Vsi = dsi si si d 2.3 x = x = 0 (d,0) 2 2 x = 0 si 7

11 2.6 m s Ec Ef Ei Ef Ev dox dsi m s m< s 2.6 Vox Vsi s m 2.4 Ef Vox Vsi Va φ - φ = Va s m Va = φ φ 2.7 m s Va Si 2.7 = - V - y + Eg + 2 m s ox s p m- s +V ox+ ys- Eg - p = V ox+ y s= - m s + Eg + p) 2 8

12 s+ Eg + p) Si 2 V ox+ y s= - m+ s 2.9 ys 2.6 Vsi Metal SiO2 Si Vox s s m ys /2Eg Ec Ef p Ei Ef Ev dox dsi dsi Si ys Vg 2.8 m- s+v ox+ ys- Eg - p = Vg V + y = Vg - + ox s m s V + y = Vg - Va 2. ox s 9

13 2. Ei Ef P N y= 2φ 2.2 s p Vth dm V + 2 φ = V - Va ox p th d ox V th= Q + 2 φp + Va ox 2.2 q Na dm 2φ p = dm 2 si 2.3 d m = 4 si φ qna p Q Q = - q Na d = 4 q Na 2.4 m φp si 2.3 Vth d V = 4 φ q Na + φ - - E+ φ ox th p si m s g p ox 2 0

14 3. 3. LED 3.2 IC multisim multisim IC LED LED

15 LED 3.2 start stop reset LED multisim start stop clear S0 S S2 S3 S4 S

16 LED_a LED_d LED_b LED_g LED_e LED_c LED_f 3.4 LED S0 S2 S S0 LED S LED S2 LED S3 LED e start stop S0 S5 LED LED stop LED start stop reset stop LED S6 reset S6 LED LED 3.5 LED LED 3

17 start stop reset LED LED start stop reset st_sp zero C0 C C2 3 st_sp C2 zero C0 C0 Start C0 C2 C2 st_sp st_sp stop C2 st_sp S0 S5 stop C2 C0 st_sp 0 S0 S5 start C0 C2 S0 S5 C0 stop reset C0 C C zero LED LED LED C start C2 4

18 start stop reset start= start=0 start=0 stop=0 start= C C0 C2 reset= stop= reset=0 st_sp st_sp= S0 S S2 S3 S4 S5 st_sp=0 zero LED 3.5 LED C0 C C D D D 3. 5

19 D-FF Qs2 Qs stop start reset Qs2+ Ds2 Qs+ Ds 0 0 C0 0 (C2) (C)

20 Ds2 reset 0 start, stop Qs2,Qs Ds2 = Qs start + Qs start reset Ds reset 0 start, stop Qs2,Qs Ds = start stop reset + Qs stop 7

21 start stop NOT AND3 OR2 Ds SET D Q ~Q RESET D_FF AND2 st_sp NOT AND2 reset NOT Ds2 SET zero AND3 OR2 D Q ~Q RESET D_FF AND2 g_led clock AND2 AND2 OR2 g_led 2 NOT 3.8 g_led g_led2 3.9 LED LED2 start reset stop 6 C0 start reset g_led start LED start reset start start reset g_led2 reset LED2 LED LED2 LED LED2 stop start stop reset start stop reset start 3.9 LED 2 8

22 s0 s D D_FF Qc Qb Qa st_sp Qc+ (Dc) Qb+ (Db) Qa+(Da)

23 Da Db Qa,st_sp Qa,st_sp Qc,Qb Qc,Qb Da = Qc st_sp + Qa st_sp Db = Qb st_sp + Qa st_sp Dc Qa,st_sp Qc,Qb Dc = Qb st_sp + Qc st_sp 20

24 st_s SET D Qa NOT AND2 AND2 OR2 D Q ~Q RESET D_FF Qa SET D Qb AND2 AND2 OR2 D Q ~Q RESET D_FF Qb AND2 AND2 OR2 SET D Q D ~Q RESET D_FF Qc Qc cloc LED a f b e c d LED 2

25 Qc Qb Qa a b c d e f g b,e c,d g Qc,Qb 00 Qa 0 Qc,Qb 00 Qa 0 Qc,Qb 00 Qa be = Qb Qc cd = Qc + Qa g = Qc Qc + Qc Qb + Qb Qa a,f Qc af = Qc 22

26 AND2 a,f Qa b,e Qa AND3 Qb Qb OR2 AND2 c,d Qc Qc OR2 AND2 OR2 AND2 g AND2 zero NOT start stop reset SR D D

27 5V sw Key = Space kohm kohm kohm R R R D Q ~Q start start D_FF sw2 Key = Space D Q ~Q D_FF stop stop sw3 Key = Space D Q ~Q reset reset D_FF clock CMOS 20 25Hz CR LED 3.5 C R CR R2 inv3 A B R2 R inv3 U inv2 U2 A inv U3 Vout.0ohm NOT NOT NOT C C.0pF B 3.5 b R.0ohm R2 a 24

28 V Vdd A t V Vdd+Vinv Vdd Vinv 0 Vinv-Vdd t0 t t2 t T 3.7 B C A 0V inv 5V R a C B Vinv inv3 inv2 A 5V inv 0V C B Vinv+Vdd 25

29 3.7 t0 R b B Vinv inv3 A 0V C B Vinv-Vdd 3.7 t A 0V inv3 5V R a B Vinv 3.7 t2 t t2 inv3 PMOS NMOS t t2 t -t/cr Vinv = (Vdd + Vinv)e Vinv t ln( ) = Vdd + Vinv CR Vinv t = CR ln( ) Vdd + Vinv t2 Vdd + (Vinv - 2Vdd) Vinv = - 2Vdd - Vinv e - t2/cr e = - t2/cr t2 Vdd -Vinv = ln( ) CR 2Vdd - Vinv Vdd -Vinv t2 = - CRln( ) 2Vdd - Vinv Vinv T = t + t2 Vdd -Vinv Vinv T = - CRln( ) CR ln( ) 2Vdd - Vinv Vdd + Vinv (Vdd -Vinv) T = - CR ln[vinv ] (2Vdd - Vinv)(Vdd + Vinv) Vdd = 5V Vinv = /2Vdd T 2.2CR 26

f = 20Hz T = 0.05s R = 22 k C =.0 F 3.8 multisim 3.9 3.

30 f = 20Hz T = 0.05s R = 22 k C =.0 F 3.8 multisim LED start stop reset Qa Qb Qc 3.2 LED

31 Qa Qb Qc cd g af be 3.2 LED A 3.23 B 28

32 Vdd 0V 3.22 Vdd Vinv 0V

33 C.0 F R 22k f = 20.8Hz /2Vdd 50% 24.5Hz 25.0Hz 42% % inv3 PMOS NMOS t t2 NMOS PMOS CMOS CMOS Vinv-Vdd 2.5V IC IC muitisim IC 2 30

34 4. 8bitCPU 4. CPU 8bit CPU 4. HDL FPGA CPU CPU VHDL RTL FPGA 3

35 4.2 CPU CPU FPGA 4.2. CPU CPU 5 HALT LD ST SCF RCF MOV BR AND OR XOR COMP ADD ADC SUB SUC CPU 32

36 NF ZF CF VF SCF 0 RCF MOV BR BR no yes CF =

37 AND OR XOR COMP ADD ADC SUB SUC AND OR XOR COMP A B ADD ADC SUB SUC COMP 8bit bit 9bit bit A B ADD A B 8bit 9bit bit 8bit bit 8bit A 7 0 A 0 B ADD B ADC SUC ADC SUC 4.4 A B 0 A B 0 ADC SUC 8bit COMP SUB 4.5 A > B A = B A < B 3 A > B 34

38 0 A = B 0 A < B SUB A < B COMP bit 0 8bit 7 0 A 0 B COMP 0 A > B A = B 0 A < B

39 36 operand a b c IR PC MDR opcode operand 5 IR PC MDR opcode opcode operand IR PC MDR operand opcode opcode operand memory memory memory next opcode

40 4.6 a c IR PC MDR IR PC MDR PC 5 a PC IR b PC PC 6 MDR PC c MDR IR PC MDR MAR a 0 IR PC PC MAR PC b MAR c

41 38 3 displacement IX 4.8 a 25 IR PC MAR operand opcode opcode operand memory IR PC 0 2 opcode operand 2 MAR operand 20 opcode memory memory IR PC opcode 0 2 opcode operand MAR 4.7 a b c

42 IR PC PC MDR b IX MDR c IX a IR PC MDR opcode memory opcode displacement IX 50 memory IR opcode opcode displacement b PC MDR 7 IX 50 memory IR opcode opcode displacement c PC MDR displacement 50 IX

43 4 MAR memory IR opcode 3 opcode a PC next opcode MAR operand memory IR opcode 3 opcode 32 next opcode b PC MAR operand 38 data a 3 IR PC MAR b MAR 38 MAR 40

44 bit 2 6bit bit opcode 4bit 4.0 4bit 4bit 4. 4bit 4bit 8bit 5 always CF = on carry NF = on negative ZF = on zero VF = on over flow 2 PC opcode 4bit 4bit operand 8bit 4. 4

45 opcode 4bit 2bit 2bit 4.2 4bit 2bit opcode 4bit 2bit 2bit operand displacement 8bit

46 2 4bit 4 2bit IR IX MDR PC MAR ACC 2 ACC2 Flag 8bit CF ZF NF VF 4 4bit ACC ACC2 Flag 43

47 HALT LD ST SCF RCF MOV BR AND OR XOR COMP ADD ADC SUB SUC 44

48 IR PC MDR ACC ACC2 IX MAR ACC ACC2 IX MAR IR PC MDR 45

49 Always on carry on zero on overflow on negative 46

50 CPU ck reset test start 4 memr memw 8bit address bus 0 8bit (external data bus) ck reset external data bus 8bit CPU test address bus 8bit start memr memw register ALU address control 47

51 register control ALU address register IR ACC ACC2 IX MDR PC MAR control ALU address Flag

52 4.7 ALU ALU bus internal databus 2 ALU ALU databus buffer address bus internal data bus data bus buffer register IR ACC ACC2 IX MDR PC MAR external data bus control ALU address address bus Flag ALU bus test signal 2 ALU ALU multiplexer ALU 2 ALU ALU 2 test signal 2 test output ALU test signal ALU test output multiplexer 49

53 internal data bus data bus buffer register IR ACC ACC2 IX MDR PC MAR external data bus control test signal 2 Flag ALU-multiplexer ALU address test output address bus test signal ALU bus multiplexer ALU ACC ACC2 IX MAR IR MDR PC MAR PC inc mux MAR ALU mux ALU 0V 0V ALU ALU 0 OR 50

54 internal data bus ALU-bus mux mux2 IR ACC ACC2 IR MDR PC inc MAR internal data bus data bus buffer mux mux2 IR ACC ACC2 IX MDR PC inc MAR external data bus ALU- multiplexer Flag ALU test output ALU bus multiplexer

55 PC IX MDR MAR adder address multiplexer address bus internal data bus data bus buffer mux IR ACC ACC2 IX MDR PC inc mux2 MAR external data bus ALU- multiplexer adder address multiplexer address bus Flag ALU test output ALU bus multiplexer

56 4.2 PC IX MDR MAR address mutiplexer register IR control ALU_multiplexer, address multiprexer Flag ALU memory, databus IR Flag ALU ALU

57 internal data bus data bus buffer mux IR ACC ACC2 IX MDR PC inc mux2 MAR external data bus control ALU- multiplexer adder addressmultiplexer address bus Flag ALU ALU bus test output multiplexer memr memw

58 memr memw data address PC MAR IR register a_mux dbb MDR Flag LOW LOW ACC ACC2 MAR IX LOW HI a_mux : address multiprexer dbb : data bussbuffer 55

59 T0 T T2 T3 T4 T5 memr memw data address HALT a a+ PC a a+ IR HALT a_mux PC dbb 4.25 PC a_mux PC a T IR dbb 0 PC T2 IR

60 T0 T T2 T3 T4 T5 memr memw data LOAD operand address a a+ a+2 PC a a+ a+2 IR LOAD register (ACC 2, IX,MAR) a_mux PC operand dbb MDR operand a a PC a_mux PC T IR T2 a_mux PC a+ T3 MDR T4 ACC ACC2 IX MAR 57

61 T0 T T2 T3 T4 T5 T6 memr memw data LOAD operand data address a a+ operand a+2 PC MAR a a+ a+2 operand IR LOAD Register (ACC 2, IX,MAR) a_mux PC MAR data PC dbb MDR data a a PC a_mux PC T IR T2 a_mux PC a+ T3 MAR a_mux MAR MAR T5 MDR T6 ACC ACC2 IX MAR 58

62 T0 T T2 T3 T4 T5 T6 memr memw data LOAD dis data address a a+ dis +IX a+2 PC a a+ a+2 IR LOAD Register (ACC 2, IX,MAR) a_mux PC dis +IX data PC dbb MDR dis data a a PC a_mux PC T IR T2 dis a_mux PC a+ T3 MDR a_mux T5 MDR T6 ACC ACC2 IX MAR 59

63 T0 T T2 T3 T4 T5 memr memw data LOAD data address a a+ operand a+ PC a a+ MAR operand IR LOAD Register (ACC 2, IX,MAR) data a_mux PC MAR PC dbb MDR data a a PC a_mux PC T IR T2 a_mux MAR MAR T4 MDR T5 ACC ACC2 IX MAR 60

64 T0 T T2 T3 T4 T5 memr memw data ST operand data address a a+ operand a+2 PC a a+ a+2 MAR operand IR ST Register (ACC 2, IX,MAR) data a_mux PC MAR PC dbb a a PC a_mux PC T IR T2 T3 MAR a_mux MAR MAR T4 ACC ACC2 IX MAR T5 0 dbb 6

65 T0 T T2 T3 T4 T5 memr memw data ST dis data address a a+ dis +IX a+2 PC a a+ a+2 IR ST Register (ACC 2, IX,MAR) data a_mux PC dis +IX PC dbb MDR dis a a PC a_mux PC T IR T2 T3 MDR a_mux T4 ACC ACC2 IX MAR T5 0 dbb 62

66 T0 T T2 T3 T4 T5 memr memw data ST data address a a+ operand a+ PC a a+ MAR operand IR ST Register (ACC 2, IX,MAR) data a_mux PC MAR PC dbb a a PC a_mux PC T IR T2 a_mux MAR MAR ACC ACC2 IX MAR T4 0 dbb 63

67 T0 T T2 T3 T4 T5 memr memw data address MOV a a+ PC IR register (ACC 2, IX,MAR) a_mux dbb a a+ MOV data data2 PC data a a PC a_mux PC T IR T2 ALU data2 T3 64

68 T0 T T2 T3 T4 T5 memr memw data address SCF/RCF a a+ PC IR a a+ SCF/RCF a_mux PC dbb Flag CF=, a a PC a_mux PC T IR T2 0 T3 65

69 T0 T T2 T3 T4 T5 memr memw data BR operand address a a+ operand PC a a+ operand IR BR a_mux PC dbb a a PC a_mux PC T IR T2 T3 PC 66

70 T0 T T2 T3 T4 T5 memr memw data BR address a a+ a+2 PC a a+ a+2 IR BR a_mux dbb PC a a PC a_mux PC T IR T2 PC 67

71 T0 T T2 T3 T4 T5 memr memw data opcode operand address a a+ a+2 PC a a+ a+2 IR register (ACC2) opcode result a_mux PC dbb MDR operand a a PC a_mux PC T IR T2 PC a+ T3 MDR T3 T4 result ACC2 68

72 T0 T T2 T3 T4 T5 T6 memr memw data opcode operand data address a a+ operand a+2 PC a a+ a+2 MAR oprand IR opcode Register (ACC2) result a_mux PC MAR PC dbb MDR data a a PC a_mux PC T IR T2 PC a+ T3 MAR a_mux MAR MAR T5 MDR T5 T6 result ACC2 69

73 T0 T T2 T3 T4 T5 T6 memr memw data opcode dis data address a a+ dis +IX a+2 PC a a+ a+2 IR opcode Register (ACC2) result a_mux PC dis +IX PC dbb MDR dis data a a PC a_mux PC T IR T2 dis PC a+ T3 MDR a_mux IX T5 MDR T5 T6 result ACC2 70

74 T0 T T2 T3 T4 T5 memr memw data opcode data address a a+ operand a+ PC a a+ MAR operand IR Register (ACC2) opcode result a_mux PC MAR PC dbb MDR data a a PC a_mux PC T IR T2 MAR a_mux MAR T4 MDR T4 T5 result ACC2 7

75 CPU PC=PC+ PC address MAR address IX+MDR address mem IR mem MDR mem MAR mem PC reg mem MDR reg ALU ACC2 MDR ALU reg ALU reg reg ALU CF,0 Flag set satisfied HALT PC PC MAR IX MDR IR IR MAR PC MDR ALU ACC2 MDR ALU ALU ALU CF 0 CF 0 72

76 3 T0 T T2 T3 T4 T5 T6 HALT HALT LOAD imm ab ix PC address PC=PC+ mem MDR mem MAR MAR address mem MDR IX+MDR address MDR reg address mem address mem mem MDR MDR reg reg-i MAR address address mem mem MDR MDR reg ST ab ix PC address PC=PC+ mem IR PC address PC=PC+ mem MAR MAR address mem MDR IX+MDR address address mem address mem reg mem reg-i MAR address address mem reg mem MOV reg ALU ALU reg SCF,RCF BR BR2 CF,0 PC address satisfied Flag set mem PC PC=PC+ AND OR NOT... SUC imm ab ix reg-i PC address PC=PC+ MAR address mem MDR MDR ALU reg mem MAR MAR address mem MDR IX+MDR address address mem ALU ACC2 address mem address mem mem MDR mem MDR MDR reg ALU ALU ACC2 ALU ACC

77 4.2.9 CPU 4.42 PC address PC=PC+ mem IR HALT PC address satisfied reg ALU CF,0 PC address PC=PC+ MAR address mem PC PC=PC+ ALU reg Flag set mem MDR mem MDR mem MAR MAR address mem MDR IX+MDR address MDR reg ALU address mem mem MDR mem MDR MDR reg ALU reg mem MDR reg ALU ACC IR HDL

78 start = 0 idle start = read mem_ir HALT BR BR2 MOV SCF RCF LD ST OP (LSO) reg_i BR_ BR2_2 MOV2 SCF2 RCF2 imm ab ix ads_mem mem_reg reg_mem ALU_reg HALT idle start 75

79 4.3 HDL 4.3. HDL HDL ALU ALU ALU ALU cont 2 test IR ACC ACC2 IX MDR PC MAR cont cont2 test ALU- multiplexer out out2 test_o [7:0] [2:0] 4.44 ALU 76

80 77 ALU out2 ALU out test_o test out2 cont2 out cont MAR mar PC pc MDR mdr IX ix test_o ACC2 acc2 ACC acc IR ir 0 MAR 0 PC 00 MDR 0 IX 00 ACC2 00 ACC 000 IR test cont,2 00 MDR 0 GND 0 MAR 00 IX 00 ACC2 000 ACC 4.8 ALU 4.9

81 2 ALU ALU alu_cont alu_in alu_in2 alu_cont carry_in ALU alu_out alu_out2 [7:0] [3:0] [2:0] 4.45 ALU 78

82 4.0 ALU alu_in alu_in2 alu_cont carry_in alu_out alu_out2 ALU ALU ALU 4. AND OR XOR COMP ADD ADC SUB SUC alu_cont

83 flag_s a_mux PC MAR mux mux2 pc_s mar_s alu_c alu_mux_c alu_mux_c2 [7:0] ir flag ck reset start control ir_c acc_c acc2_c mdr_c mdr_s ix_c pc_c pc_s mar_c mar_s flag_c flag_s [3:0] a_mux dbb [2:0] [:0] memr memw

84 8 reset memw memr dbb a_mux MAR ALU mar_s Flag LOW flag_c Flag flag_s PC LOW pc_c PC PC pc_s MAR LOW mar_c IX LOW ix_c MDR LOW mdr_c ACC2 LOW acc2_c ACC LOW acc_c IR LOW ir_c ALU alu_mux_c2 ALU alu_mux_c ALU alu_c start ck Flag flag IR ir 4.2 ALU

85 4.3 PC MAR SCF RCF -- flag_s PC 00 0 MAR 0 MDR+IX -- a_mux pc_s mar_s data bus 0 ALU bus 0 PC data bus pc_s 0 PC PC mar_s 0 ALU MAR 82

86 pc mar mdr ix ads_mode ADDREESS [7:0] addreess_out [:0] pc mar mdr ix ads_mode address_out PC MAR MDR IX 83

87 5 PC PC pc_data_in ck reset PC pc_en pc_sel [7:0] pc_data_out 4.48 PC 4.5 PC pc_data_in pc_en pc_sel pc_data_out PC PC 84

88 6 MAR MAR mar_data_in mar_alu_in ck reset MAR mar_en mar_sel mar_data_out [7:0] 4.49 MAR 4.6 MAR mar_alu_in mar_data_in mar_en mar_sel mar_data_out ALU ALU MAR 85

89 7 Flag Flag ck reset flag_in_cf flag_in_zf flag_in_vf flag_in_nf Flag flag_out_cf flag_out_zf flag_out_vf flag_out_nf [:0] flag_en flag_sel 4.50 Flag 4.7 Flag flag_en flag_sel flag_in_cf flag_in_zf flag_in_vf flag_in_nf flag_out_cf flag_out_zf flag_out_vf flag_out_nf ALU 86

90 4.8 flag_sel ALU 00 flag_sel CF 0 CF 0 8 IR ACC ACC2 MDR IR ACC ACC2 MDR VHDL ir_data_in acc_data_in acc2_data_in ix_data_in mdr_data_in ck reset ir_en acc_en acc2_en ix_en mdr_en IR ACC ACC2 IX MDR ir_data_out acc_data_out acc2_data_out ix_data_out mdr_data_out [7:0]

91 4.9 ir_en acc_en acc2_en ix_en mdr_en ir_data_in acc_data_in acc2_data_in ix_data_in mdr_data_in ir_data_out acc_data_out acc2_data_out ix_data_out mdr_data_out ALU VHDL ALU 2 ALU PC 6 MAR 7 Flag 8 IR 9 VHDL ALU -- ALU_MULTIPLEXER library ieee; use ieee.std_logic_64.all; entity ALU_mux is port ( ir_o : in std_logic_vector(7 downto 0); acc_o: in std_logic_vector(7 downto 0); acc2_o: in std_logic_vector(7 downto 0); ix_o: in std_logic_vector(7 downto 0); mdr_o: in std_logic_vector(7 downto 0); pc_o: in std_logic_vector(7 downto 0); mar_o: in std_logic_vector(7 downto 0); cont : in std_logic_vector(2 downto 0); cont2 : in std_logic_vector(2 downto 0); 88

92 alu_mux_o : out std_logic_vector(7 downto 0); alu_mux_o2 : out std_logic_vector(7 downto 0); test_sel : in std_logic_vector(2 downto 0); test_o : out std_logic_vector(7 downto 0) ); end ALU_mux; architecture BEHAVIOR of ALU_mux is begin process(cont,cont2,test_sel,ir_o,acc_o,acc2_o,ix_o,mdr_o, pc_o,mar_o) begin case cont is when "000" => alu_mux_o <= acc_o; when "00" => alu_mux_o <= acc2_o; when "00" => alu_mux_o <= ix_o; when "0" => alu_mux_o <= mar_o; when "00" => alu_mux_o <= mdr_o; when "0" => alu_mux_o <= " "; when others => alu_mux_o <= "XXXXXXXX"; end case; end process; process(cont,cont2,test_sel,ir_o,acc_o,acc2_o,ix_o,mdr_o, pc_o,mar_o) begin case cont2 is when "000" => alu_mux_o2 <= acc_o; when "00" => alu_mux_o2 <= acc2_o; when "00" => alu_mux_o2 <= ix_o; when "0" => alu_mux_o2 <= mar_o; when "00" => alu_mux_o2 <= mdr_o; when "0" => alu_mux_o2 <= " "; when others => alu_mux_o2 <= "XXXXXXXX"; end case; end process; process (cont,cont2,test_sel,ir_o,acc_o,acc2_o,ix_o,mdr_o, 89

93 pc_o,mar_o) begin case test_sel is when "000" => test_o <= ir_o; when "00" => test_o <= acc_o; when "00" => test_o <= acc2_o; when "0" => test_o <= ix_o; when "00" => test_o <= mdr_o; when "0" => test_o <= pc_o; when "0" => test_o <= mar_o; when others => test_o <= "XXXXXXXX"; end case; end process; end BEHAVIOR ; 2 ALU -- ALU library ieee; use ieee.std_logic_64.all; use ieee.std_logic_unsigned.all; entity ALU is port (alu_in :in std_logic_vector(7 downto 0); alu_in2 :in std_logic_vector(7 downto 0); alu_cont :in std_logic_vector(2 downto 0); alu_cin : in std_logic; ); alu_out :out std_logic_vector(7 downto 0); cf : out std_logic; zf : out std_logic; vf : out std_logic; nf : out std_logic 90

94 end ALU; architecture BEHAVIOR of ALU is signal tmp : std_logic_vector(8 downto 0); begin alu_out <= tmp(7 downto 0); process(alu_cont,alu_in,alu_in2,alu_cin,alu_out) begin case alu_cont is --AND when "000" => tmp <= ('0' & alu_in) AND('0' & alu_in2) ; vf <= '0'; -- OR when "00" => tmp <= ('0' & alu_in) OR ('0' & alu_in2) ; vf <= '0'; -- XOR when "00" => tmp <= ('0' & alu_in) XOR ('0' & alu_in2) ; vf <= '0'; -- COMP when "0" => tmp <= ('0' & alu_in) - ('0' & alu_in2); if tmp(8) = '' then nf <= ''; else nf <= '0'; -- ADD when "00" => tmp <= ('0' & alu_in) + ('0' & alu_in2); if tmp(8) = '' then vf <= ''; else vf <= '0'; 9

95 -- ADC when "0" => tmp <= ('0' & alu_in) +('0' & alu_in2) + (" " & alu_cin); if tmp(8) = '' then cf <= '' ; else cf <= '0'; -- SUB when "0" => tmp <= ('0' & alu_in) - ('0' & alu_in2); if tmp(8) = '' then vf <= ''; else vf <= '0'; -- SUC when others => tmp <= ('0' & alu_in) - ('0' & alu_in2) -(" " & alu_cin); if tmp(8) = '' then cf <= ''; else cf <= '0'; end case; end process; -- all zero process(alu_cont,alu_in,alu_in2,alu_out) begin if tmp = " " then zf <= ''; else zf <= '0'; end process; end BEHAVIOR; 92

96 3 -- CONTROL library ieee; use ieee.std_logic_64.all; entity CONT is port ( ck: in std_logic; reset: in std_logic; start: in std_logic; opcode: in std_logic_vector(3 downto 0); ads_mode: in std_logic_vector(3 downto 0); cf,zf,vf,nf: in std_logic; alu_c: out std_logic_vector(2 downto 0); alu_mux_c: out std_logic_vector(2 downto 0); alu_mux_c2: out std_logic_vector(2 downto 0); ir_c: out std_logic; acc_c: out std_logic; acc2_c: out std_logic; ix_c: out std_logic; pc_c: out std_logic; pc_s: out std_logic; mar_c: out std_logic; mar_s: out std_logic; mdr_c: out std_logic; ads_mux: out std_logic_vector( downto 0); dbb_c: out std_logic; flag_c: out std_logic; flag_s: out std_logic_vector( downto 0); memr: out std_logic; memw: out std_logic ); end CONT; architecture RTL of CONT is type state is (idle,read,dec,halt,br,br_,br2,br2_2,mov,srcf,lso, 93

97 MOV2,SRCF2,imm,ab,ix,ads_mem,reg_i, ALU_reg,mem_reg,reg_mem ); signal current_state, next_state : state; begin process(ck,reset) begin if(reset = '0') then current_state <= idle; elsif(ck'event and ck = '') then current_state <= next_state; end process; process(ck,reset,opcode,ads_mode,start,current_state) begin case current_state is when idle => if(start = '0')then next_state <= read; else next_state <= idle; when read => next_state <= dec; when dec => if (opcode = "0000") then -- halt next_state <= HALT ; elsif(opcode = "000") then -- load if (ads_mode( downto 0) = "" )then next_state <= reg_i; else next_state <= LSO; elsif(opcode = "000") then -- store if (ads_mode( downto 0) = "" )then next_state <= reg_i; 94

98 elsif (ads_mode( downto 0) = "00")then next_state <= idle; else next_state <= LSO; elsif(opcode = "00") then -- move next_state <= MOV; elsif(opcode = "00") then -- set carry flag next_state <= SRCF; elsif(opcode = "000") then -- reset carry flag next_state <= SRCF; elsif(opcode = "00") then -- branch if (ads_mode = "0000")then -- (always) next_state <= BR; elsif (ads_mode = "000")then --(on carry) if (cf = '')then next_state <= BR2; else next_state <= BR; elsif (ads_mode = "000")then -- (on zero flag) if (zf = '')then next_state <= BR2; else next_state <= BR; elsif (ads_mode = "000")then -- (on overflow flag) if (vf = '')then next_state <= BR2; else next_state <= BR; elsif (ads_mode = "000")then -- (on negative flag) if (nf = '')then next_state <= BR2; else 95

99 next_state <= BR; elsif(opcode = "0") then -- and if (ads_mode( downto 0) = "" )then next_state <= reg_i; else next_state <= LSO; elsif(opcode = "000") then -- or if (ads_mode( downto 0) = "" )then next_state <= reg_i; else next_state <= LSO; elsif(opcode = "00") then -- xor if (ads_mode( downto 0) = "" )then next_state <= reg_i; else next_state <= LSO; elsif(opcode = "00") then -- cmpare if (ads_mode( downto 0) = "" )then next_state <= reg_i; else next_state <= LSO; elsif(opcode = "0") then -- add if (ads_mode( downto 0) = "" )then next_state <= reg_i; else next_state <= LSO; elsif(opcode = "00") then -- adc if (ads_mode( downto 0) = "" )then next_state <= reg_i; 96

100 else next_state <= LSO; elsif(opcode = "0") then -- sub if (ads_mode( downto 0) = "" )then next_state <= reg_i; else next_state <= LSO; elsif(opcode = "0") then -- suc if (ads_mode( downto 0) = "" )then next_state <= reg_i; else next_state <= LSO; else next_state <= idle; when BR => next_state <= BR_; when BR2 => next_state <= BR2_2; when BR_ => next_state <= read; when BR2_2 => next_state <= read; when MOV => next_state <= MOV2; when MOV2 => next_state <= read; when SRCF => next_state <= SRCF2; when SRCF2 => next_state <= read; when HALT => next_state <= idle; when LSO => if (ads_mode( downto 0 ) = "00") then next_state <= imm; elsif (ads_mode( downto 0) = "0")then next_state <= ab; elsif (ads_mode( downto 0) = "0")then next_state <= ix; when imm => next_state <= alu_reg; 97

101 when alu_reg => next_state <= read; when ab => next_state <= ads_mem; when ix => next_state <= ads_mem; when ads_mem => if (opcode = "000")then next_state <= reg_mem; else next_state <= mem_reg; when mem_reg => next_state <= alu_reg; when alu_reg => next_state <= read; when reg_i => next_state <= ads_mem; when reg_mem => next_state <= read; when others => next_state <= idle; end case; end process; process(current_state) -- memr,memw,mdr_c begin if (current_state = read)then memr <= '0'; memw <= ''; mdr_c <= ''; elsif(current_state = LSO)then memr <= '0'; memw <= ''; mdr_c <= '0'; elsif(current_state = BR)then memr <= '0'; memw <= ''; mdr_c <= ''; elsif (current_state = ads_mem)then if (opcode = "000")then memr <= ''; memw <= '0'; mdr_c <= ''; else memr <= '0';memw <= ''; mdr_c <= '0'; else memr <= ''; memw <= ''; mdr_c <= ''; end process; process(current_state) -- ir_c begin 98

102 if (current_state = read )then ir_c <= '0'; else ir_c <= ''; end process; process(current_state) -- acc_c,acc2_c,ix_c,pc_c, mar_c begin if(current_state = idle)then acc_c <= ''; acc2_c <= '';ix_c <= ''; pc_c <= ''; mar_c <= ''; elsif (current_state = read)then acc_c <= ''; acc2_c <= '';ix_c <= ''; pc_c <= '0'; mar_c <= ''; elsif (current_state = imm )then if(opcode = "000")then acc_c <= '';acc2_c <= ''; ix_c <= ''; pc_c <= ''; mar_c <= ''; elsif (opcode = "000")then if (ads_mode(3 downto 2) = "00")then acc_c <= '0'; acc2_c <= '';ix_c <= ''; pc_c <= ''; mar_c <=''; elsif (ads_mode(3 downto 2) = "0")then acc_c <= ''; acc2_c <= '0';ix_c <= ''; pc_c <= ''; mar_c <=''; elsif (ads_mode(3 downto 2) = "0")then acc_c <= '';acc2_c <= ''; ix_c <= '0'; pc_c <= ''; mar_c <=''; else acc_c <= ''; acc2_c <= '';ix_c <= ''; pc_c <= ''; mar_c <='0'; else acc_c <= ''; acc2_c <= '0';ix_c <= ''; pc_c <= ''; mar_c <=''; elsif (current_state = mem_reg )then if(opcode = "000")then acc_c <= ''; acc2_c <= '';ix_c <= ''; pc_c <= ''; mar_c <=''; elsif(opcode = "000")then if (ads_mode(3 downto 2) = "00")then acc_c <= '0'; acc2_c <= '';ix_c <= ''; pc_c <= ''; mar_c <=''; elsif (ads_mode(3 downto 2) = "0")then acc_c <= ''; acc2_c <= '0';ix_c <= ''; pc_c <= ''; mar_c <=''; 99

103 elsif (ads_mode(3 downto 2) = "0")then acc_c <= ''; acc2_c <= ''; ix_c <= '0'; pc_c <= ''; mar_c <=''; else acc_c <= ''; acc2_c <= '';ix_c <= ''; pc_c <= ''; mar_c <='0'; else acc_c <= ''; acc2_c <= '0';ix_c <= ''; pc_c <= ''; mar_c <=''; elsif (current_state = LSO )then if(ads_mode( downto 0) = "0")then acc_c <= '';acc2_c <= ''; ix_c <= ''; pc_c <= '0'; mar_c <='0'; else acc_c <= '';acc2_c <= ''; ix_c <= ''; pc_c <= '0'; mar_c <=''; elsif (current_state = BR )then acc_c <= ''; acc2_c <= '';ix_c <= ''; pc_c <= '0'; mar_c <=''; elsif (current_state = BR2 )then acc_c <= ''; acc2_c <= '';ix_c <= ''; pc_c <= '0'; mar_c <=''; elsif (current_state = MOV)then if (ads_mode( downto 0) = "00")then acc_c <= '0'; acc2_c <= '';ix_c <= ''; pc_c <= ''; mar_c <= ''; elsif (ads_mode( downto 0) = "0")then acc_c <= ''; acc2_c <= '0';ix_c <= ''; pc_c <= ''; mar_c <= ''; elsif (ads_mode( downto 0) = "0")then acc_c <= '';acc2_c <= ''; ix_c <= '0'; pc_c <= ''; mar_c <= ''; elsif (ads_mode( downto 0) = "")then acc_c <= ''; acc2_c <= '';ix_c <= ''; pc_c <= ''; mar_c <= '0'; else acc_c <= '';acc2_c <= ''; ix_c <= ''; pc_c <= ''; mar_c <= ''; else acc_c <= ''; acc2_c <= '';ix_c <= ''; pc_c <= ''; mar_c <= ''; end process; process (current_state ) -- pc_s begin 00

104 if (current_state = read )then pc_s <= ''; elsif(current_state = LSO )then pc_s <= ''; elsif (current_state = BR2 )then pc_s <= ''; else pc_s <= '0'; end process; process(current_state) begin if(current_state = LSO)then mar_s <= ''; elsif(current_state = ab)then mar_s <= ''; else mar_s <= '0'; end process; -- mar_s process(current_state) -- address_mux begin if (current_state = ab)then ads_mux <= "0"; elsif(current_state = reg_i)then ads_mux <= "0"; elsif(current_state = ix)then ads_mux <= "0"; elsif(current_state = ALU_reg) then ads_mux <= "00"; elsif(current_state = reg_mem) then ads_mux <= "00"; elsif(current_state = idle) then ads_mux <= "00"; 0

105 end process; process(current_state) -- dbb_c begin if (current_state = ads_mem)then if(opcode = "000")then dbb_c <= ''; else dbb_c <= '0'; elsif(current_state = reg_mem)then if(opcode = "000")then dbb_c <= ''; else dbb_c <= '0'; else dbb_c <= '0'; end process; process(current_state) -- flag_c,flag_s begin if(current_state = SRCF)then if(opcode = "00")then flag_s <= "0"; flag_c <= '0'; elsif(opcode = "000")then flag_s <= "0"; flag_c <= '0'; else flag_c <= ''; elsif (current_state = mem_reg)then if (opcode > "00")then flag_s <= "00"; flag_c <= '0'; else 02

106 flag_s <= "00"; flag_c <= ''; elsif (current_state = imm)then if (opcode > "00")then flag_s <= "00"; flag_c <= '0'; else flag_s <= "00"; flag_c <= ''; else flag_s <= "00"; flag_c <= ''; end process; process (current_state) -- alu_mux_c,c2,alu_c begin if(opcode = "000")then -- load alu_mux_c <= "0"; alu_mux_c2 <= "00"; alu_c <= "00"; elsif(opcode = "000")then -- st if(ads_mode(3 downto 2) = "00") then alu_mux_c <= "0"; alu_mux_c2 <= "000"; alu_c <= "00"; elsif(ads_mode(3 downto 2) = "0") then alu_mux_c <= "0"; alu_mux_c2 <= "00"; alu_c <= "00"; elsif(ads_mode(3 downto 2) = "0") then alu_mux_c <= "0"; alu_mux_c2 <= "00"; alu_c <= "00"; elsif(ads_mode(3 downto 2) = "") then 03

107 alu_mux_c <= "0"; alu_mux_c2 <= "0"; alu_c <= "00"; elsif(opcode = "00")then -- MOV if(ads_mode(3 downto 2) = "00") then alu_mux_c <= "0"; alu_mux_c2 <= "000"; alu_c <= "00"; elsif(ads_mode(3 downto 2) = "0") then alu_mux_c <= "0"; alu_mux_c2 <= "00"; alu_c <= "00"; elsif(ads_mode(3 downto 2) = "0") then alu_mux_c <= "0"; alu_mux_c2 <= "00"; alu_c <= "00"; elsif(ads_mode(3 downto 2) = "") then alu_mux_c <= "0"; alu_mux_c2 <= "0"; alu_c <= "00"; elsif(opcode = "0")then -- and if(ads_mode(3 downto 2) = "00") then alu_mux_c <= "000"; alu_mux_c2 <= "00"; alu_c <= "000"; elsif(ads_mode(3 downto 2) = "0") then alu_mux_c <= "00"; alu_mux_c2 <= "00"; alu_c <= "000"; elsif(ads_mode(3 downto 2) = "0") then alu_mux_c <= "00"; alu_mux_c2 <= "00"; alu_c <= "000"; elsif(ads_mode(3 downto 2) = "") then 04

108 alu_mux_c <= "0"; alu_mux_c2 <= "00"; alu_c <= "000"; elsif(opcode = "000")then -- or if(ads_mode(3 downto 2) = "00") then alu_mux_c <= "000"; alu_mux_c2 <= "00"; alu_c <= "00"; elsif(ads_mode(3 downto 2) = "0") then alu_mux_c <= "00"; alu_mux_c2 <= "00"; alu_c <= "00"; elsif(ads_mode(3 downto 2) = "0") then alu_mux_c <= "00"; alu_mux_c2 <= "00"; alu_c <= "00"; elsif(ads_mode(3 downto 2) = "") then alu_mux_c <= "0"; alu_mux_c2 <= "00"; alu_c <= "00"; elsif(opcode = "00")then -- xor if(ads_mode(3 downto 2) = "00") then alu_mux_c <= "000"; alu_mux_c2 <= "00"; alu_c <= "00"; elsif(ads_mode(3 downto 2) = "0") then alu_mux_c <= "00"; alu_mux_c2 <= "00"; alu_c <= "00"; elsif(ads_mode(3 downto 2) = "0") then alu_mux_c <= "00"; alu_mux_c2 <= "00"; alu_c <= "00"; elsif(ads_mode(3 downto 2) = "") then 05

109 alu_mux_c <= "0"; alu_mux_c2 <= "00"; alu_c <= "00"; elsif(opcode = "00")then -- comp if(ads_mode(3 downto 2) = "00") then alu_mux_c <= "000"; alu_mux_c2 <= "00"; alu_c <= "0"; elsif(ads_mode(3 downto 2) = "0") then alu_mux_c <= "00"; alu_mux_c2 <= "00"; alu_c <= "0"; elsif(ads_mode(3 downto 2) = "0") then alu_mux_c <= "00"; alu_mux_c2 <= "00"; alu_c <= "0"; elsif(ads_mode(3 downto 2) = "") then alu_mux_c <= "0"; alu_mux_c2 <= "00"; alu_c <= "0"; elsif(opcode = "0")then if(ads_mode(3 downto 2) = "00") then -- add alu_mux_c <= "000"; alu_mux_c2 <= "00"; alu_c <= "00"; elsif(ads_mode(3 downto 2) = "0") then alu_mux_c <= "00"; alu_mux_c2 <= "00"; alu_c <= "00"; elsif(ads_mode(3 downto 2) = "0") then alu_mux_c <= "00"; alu_mux_c2 <= "00"; alu_c <= "00"; elsif(ads_mode(3 downto 2) = "") then 06

110 alu_mux_c <= "0"; alu_mux_c2 <= "00"; alu_c <= "00"; elsif(opcode = "00")then -- adc if(ads_mode(3 downto 2) = "00") then alu_mux_c <= "000"; alu_mux_c2 <= "00"; alu_c <= "0"; elsif(ads_mode(3 downto 2) = "0") then alu_mux_c <= "00"; alu_mux_c2 <= "00"; alu_c <= "0"; elsif(ads_mode(3 downto 2) = "0") then alu_mux_c <= "00"; alu_mux_c2 <= "00"; alu_c <= "0"; elsif(ads_mode(3 downto 2) = "") then alu_mux_c <= "0"; alu_mux_c2 <= "00"; alu_c <= "0"; elsif(opcode = "0")then -- sub if(ads_mode(3 downto 2) = "00") then alu_mux_c <= "000"; alu_mux_c2 <= "00"; alu_c <= "0"; elsif(ads_mode(3 downto 2) = "0") then alu_mux_c <= "00"; alu_mux_c2 <= "00"; alu_c <= "0"; elsif(ads_mode(3 downto 2) = "0") then alu_mux_c <= "00"; alu_mux_c2 <= "00"; alu_c <= "0"; elsif(ads_mode(3 downto 2) = "") then 07

111 alu_mux_c <= "0"; alu_mux_c2 <= "00"; alu_c <= "0"; elsif(opcode = "0")then if(ads_mode(3 downto 2) = "00") then alu_mux_c <= "000"; alu_mux_c2 <= "00"; alu_c <= ""; elsif(ads_mode(3 downto 2) = "0") then alu_mux_c <= "00"; alu_mux_c2 <= "00"; alu_c <= ""; elsif(ads_mode(3 downto 2) = "0") then alu_mux_c <= "00"; alu_mux_c2 <= "00"; alu_c <= ""; elsif(ads_mode(3 downto 2) = "") then alu_mux_c <= "0"; alu_mux_c2 <= "00"; alu_c <= ""; else alu_mux_c <= "XXX"; alu_mux_c2 <= "XXX"; alu_c <= "XXX"; end process; end RTL; -- suc 08

112 4 -- address library ieee; use ieee.std_logic_64.all; use ieee.std_logic_unsigned.all; entity ADDRESS is port ( ads_mode: in std_logic_vector( downto 0); pc: in std_logic_vector(7 downto 0); mar: in std_logic_vector(7 downto 0); mdr: in std_logic_vector(7 downto 0); ix: in std_logic_vector(7 downto 0); address_out: out std_logic_vector(7 downto 0) ); end ADDRESS; architecture BEHAVIOR of ADDRESS is begin process(ads_mode,pc,mar,mdr,ix) begin if (ads_mode = "00")then address_out <= pc; elsif(ads_mode = "0")then address_out <= mdr + ix; elsif(ads_mode = "0")then address_out <= mar; else address_out <= "XXXXXXXX" ; end process; end BEHAVIOR; 09

113 5 PC -- pc library ieee; use ieee.std_logic_64.all; use ieee.std_logic_unsigned.all; entity PC is port ( ); end PC; ck: in std_logic; reset: in std_logic; pc_en: in std_logic; pc_sel: in std_logic; pc_data_in: in std_logic_vector(7 downto 0); pc_data_out: buffer std_logic_vector(7 downto 0) architecture RTL of PC is signal tmp : std_logic_vector(7 downto 0); begin tmp <= pc_data_out + ; process(ck,reset) begin if ( reset = '0')then pc_data_out <= " "; else if ( ck'event and ck = '')then if ( pc_en = '0')then if (pc_sel = '0')then pc_data_out <= pc_data_in; else pc_data_out <= tmp; end process; 0

114 end RTL; 6 MAR -- MAR library ieee ; use ieee.std_logic_64.all; entity MAR is port ( ); end MAR; ck: in std_logic; reset: in std_logic; mar_sel: in std_logic; mar_en: in std_logic; mar_data_in: in std_logic_vector(7 downto 0); mar_alu_in: in std_logic_vector(7 downto 0); mar_data_out: out std_logic_vector(7 downto 0) architecture RTL of MAR is begin process(ck,reset) begin if ( reset = '0')then mar_data_out <= " "; else if ( ck'event and ck = '')then if ( mar_en = '0')then if (mar_sel = '0')then mar_data_out <= mar_alu_in; else mar_data_out <= mar_data_in; end process; end RTL;

115 7 Flag -- flag library ieee; use ieee.std_logic_64.all; entity FLAG is port ( ); end FLAG; ck: in std_logic; reset: in std_logic; flag_en: in std_logic; flag_sel: in std_logic_vector( downto 0); flag_in_cf: in std_logic; flag_in_zf: in std_logic; flag_in_vf: in std_logic; flag_in_nf: in std_logic; flag_out_cf: out std_logic; flag_out_zf: out std_logic; flag_out_vf: out std_logic; flag_out_nf: out std_logic architecture RTL of FLAG is begin process(ck,reset) begin if (reset = '0')then flag_out_cf <= '0'; flag_out_zf <= '0'; flag_out_vf <= '0'; flag_out_nf <= '0'; else if (ck'event and ck = '')then if (flag_sel = "00")then if (flag_en = '0') then flag_out_cf <= flag_in_cf; flag_out_zf <= flag_in_zf; 2

116 flag_out_vf <= flag_in_vf; flag_out_nf <= flag_in_nf; elsif (flag_sel = "0")then flag_out_cf <= ''; elsif (flag_sel = "0")then flag_out_cf <= '0'; end process; end RTL; 8 -- ir library ieee; use ieee.std_logic_64.all; entity IR is port ( ); end IR; ck: in std_logic; reset: in std_logic; ir_en: in std_logic; ir_data_in: in std_logic_vector(7 downto 0); ir_data_out: out std_logic_vector(7 downto 0) architecture RTL of IR is begin process(ck,reset) begin if ( reset = '0')then ir_data_out <= " "; else 3

117 if ( ck'event and ck = '')then if ( ir_en = '0')then ir_data_out <= ir_data_in; end process; end RTL; 9 -- K_CPU library ieee; use ieee.std_logic_64.all; use ieee.std_logic_unsigned.all; entity k_cpu is port ( ck: in std_logic; reset: in std_logic; start: in std_logic; test_cont: in std_logic; test_sel: in std_logic_vector(2 downto 0); data_in: in std_logic_vector(7 downto 0); dbb_cont: out std_logic; data_out: out std_logic_vector(7 downto 0); address_bus: out std_logic_vector(7 downto 0); memr: out std_logic; memw: out std_logic ); end k_cpu; architecture arch of k_cpu is component ALU_mux port ( 4

118 ir_o : in std_logic_vector(7 downto 0); acc_o: in std_logic_vector(7 downto 0); acc2_o: in std_logic_vector(7 downto 0); ix_o: in std_logic_vector(7 downto 0); mdr_o: in std_logic_vector(7 downto 0); pc_o: in std_logic_vector(7 downto 0); mar_o: in std_logic_vector(7 downto 0); cont : in std_logic_vector(2 downto 0); cont2 : in std_logic_vector(2 downto 0); alu_mux_o : out std_logic_vector(7 downto 0); alu_mux_o2 : out std_logic_vector(7 downto 0); test_sel : in std_logic_vector(2 downto 0); test_o : out std_logic_vector(7 downto 0) ); end component; component ALU port (alu_in :in std_logic_vector(7 downto 0); alu_in2 :in std_logic_vector(7 downto 0); alu_cont :in std_logic_vector(2 downto 0); alu_cin : in std_logic; alu_out :out std_logic_vector(7 downto 0); cf : out std_logic; zf : out std_logic; vf : out std_logic; nf : out std_logic ); end component; component CONT port ( ck: in std_logic; reset: in std_logic; start: in std_logic; opcode: in std_logic_vector(3 downto 0); ads_mode: in std_logic_vector(3 downto 0); cf,zf,vf,nf: in std_logic_vector(3 downto 0); alu_c: out std_logic_vector(2 downto 0); 5

119 alu_mux_c: out std_logic_vector(2 downto 0); alu_mux_c2: out std_logic_vector(2 downto 0); ir_c: out std_logic; acc_c: out std_logic; acc2_c: out std_logic; ix_c: out std_logic; pc_c: out std_logic; pc_s: out std_logic; mar_c: out std_logic; mar_s: out std_logic; mdr_c: out std_logic; ads_mux: out std_logic_vector( downto 0); dbb_c: out std_logic; flag_c: out std_logic; flag_s: out std_logic_vector( downto 0); memr: out std_logic; memw: out std_logic ); end component; component IR port ( ck: in std_logic; reset: in std_logic; ir_en: in std_logic; ir_data_in: in std_logic_vector(7 downto 0); ir_data_out: out std_logic_vector(7 downto 0) ); end component; component acc port ( ck: in std_logic; reset: in std_logic; acc_en: in std_logic; acc_data_in: in std_logic_vector(7 downto 0); acc_data_out: out std_logic_vector(7 downto 0) ); 6

120 end component; component acc2 port ( ck: in std_logic; reset: in std_logic; acc2_en: in std_logic; acc2_data_in: in std_logic_vector(7 downto 0); acc2_data_out: out std_logic_vector(7 downto 0) ); end component; component ix port ( ck: in std_logic; reset: in std_logic; ix_en: in std_logic; ix_data_in: in std_logic_vector(7 downto 0); ix_data_out: out std_logic_vector(7 downto 0) ); end component; component mdr port ( ck: in std_logic; reset: in std_logic; mdr_en: in std_logic; mdr_data_in: in std_logic_vector(7 downto 0); mdr_data_out: out std_logic_vector(7 downto 0) ); end component; component PC port ( ck: in std_logic; reset: in std_logic; pc_en: in std_logic; pc_sel: in std_logic; pc_data_in: in std_logic_vector(7 downto 0); pc_data_out: buffer std_logic_vector(7 downto 0) 7

121 ); end component; component MAR port ( ck: in std_logic; reset: in std_logic; mar_sel: in std_logic; mar_en: in std_logic; mar_data_in: in std_logic_vector(7 downto 0); mar_alu_in: in std_logic_vector(7 downto 0); mar_data_out: out std_logic_vector(7 downto 0) ); end component; component ADDRESS port ( ads_mode: in std_logic_vector( downto 0); pc: in std_logic_vector(7 downto 0); mar: in std_logic_vector(7 downto 0); mdr: in std_logic_vector(7 downto 0); ix: in std_logic_vector(7 downto 0); address_out: out std_logic_vector(7 downto 0) ); end component; component MUX port ( data_sel: in std_logic; test_output: in std_logic_vector(7 downto 0); alu_output: in std_logic_vector(7 downto 0); data_out: out std_logic_vector(7 downto 0) ); end component; component FLAG port ( ck: in std_logic; reset: in std_logic; 8

122 flag_en: in std_logic; flag_sel: in std_logic_vector( downto 0); flag_in_cf: in std_logic; flag_in_zf: in std_logic; flag_in_vf: in std_logic; flag_in_nf: in std_logic; flag_out_cf: out std_logic; flag_out_zf: out std_logic; flag_out_vf: out std_logic; flag_out_nf: out std_logic ); end component; signal ir_out,acc_out,acc2_out,ix_out,mdr_out, pc_out,mar_out : std_logic_vector (7 downto 0); signal alu_bus : std_logic_vector(7 downto 0); signal alu_in,alu_in2 : std_logic_vector(7 downto 0); signal alu_c: std_logic_vector(2 downto 0); signal alu_mux_c: std_logic_vector(2 downto 0); signal alu_mux_c2: std_logic_vector(2 downto 0); signal ir_c: std_logic; signal acc_c: std_logic; signal acc2_c: std_logic; signal ix_c: std_logic; signal pc_c: std_logic; signal pc_s: std_logic; signal mar_c: std_logic; signal mar_s: std_logic; signal mdr_c: std_logic; signal ads_mux: std_logic_vector( downto 0); signal flag_c: std_logic; signal flag_s: std_logic_vector( downto 0); signal test_output: std_logic_vector (7 downto 0); signal cf_o,zf_o,vf_o,nf_o: std_logic; signal cf_i,zf_i,vf_i,nf_i: std_logic; begin 9

123 U : ALU_mux port map (ir_out,acc_out,acc2_out,ix_out, mdr_out,pc_out,mar_out, alu_mux_c,alu_mux_c2, alu_in,alu_in2, test_sel, test_output); U2 : ALU port map (alu_in,alu_in2,alu_c,cf_o, alu_bus, cf_i,zf_i,vf_i,nf_i); U3 : CONT port map (ck,reset,start, ir_out(7 downto 4),ir_out(3 downto 0), cf_o,zf_o,vf_o,nf_o, alu_c,alu_mux_c,alu_mux_c2, ir_c,acc_c,acc2_c,ix_c,pc_c,pc_s,mar_c,mar_s, mdr_c,ads_mux,dbb_cont,flag_c,flag_s, memr,memw ); U4 : IR port map (ck,reset,ir_c,data_in,ir_out); U5 : ACC port map (ck,reset,acc_c,alu_bus,acc_out); U6 : ACC2 port map (ck,reset,acc2_c,alu_bus,acc2_out); U7 : IX port map (ck,reset,ix_c,alu_bus,ix_out); U8 : MDR port map (ck,reset,mdr_c,data_in,mdr_out); U9 : PC port map (ck,reset,pc_c,pc_s,data_in,pc_out); U0 : MAR port map (ck,reset,mar_s,mar_c,data_in,alu_bus,mar_out); U : ADDRESS port map (ads_mux,pc_out,mar_out, mdr_out,ix_out,address_bus); U2 : MUX port map (test_cont,test_output,alu_bus,data_out); U3 : FLAG port map(ck,reset, flag_c,flag_s, cf_i,zf_i,vf_i,nf_i, cf_o,zf_o,vf_o,nf_o); end arch; 20

124 4.3.3 CPU 4.52 a 3 4 b ACC 56H 80H 2H IX a b a CPU b memr IR 2 MDR 56H ACC 3 IR 4 MAR 80H 5 MDR 2H IX 2

125 ACC IR IX 2H 80H MDR IX 92H 2 3 memw ACC 4 IR MAR 80H 5 memw ACC 6 ACC 22

126 ACC 56H IX ACC2 IR 2 ACC IX 3 4 ACC ACC2 23

127 CF SCF 0 RCF SCF 2 flag_c CF flag_s CF 0 3 RCF 4 flag_c CF 0 flag_s CF 0 24

128 ACC 6H 3H ACC2 0H 2H 2 0H ACC2 3 4 ACC2 0H 2H ACC2 NF 5 NF 6 flag_c 25

129 CF CF IR 2 CF PC 3 ZF 4 ZF PC 26

130 CPU CPU test_cont 2 test_sel 00 ACC ACC 50H 3 test_sel 0 IX 52H test_sel 0 PC 09H test_sel 0 MDR 53H 27

131 4.4 CPU HDL 5. CPU 2 28

132 29

if clear = 1 then Q <= " "; elsif we = 1 then Q <= D; end rtl; regs.vhdl clk 0 1 rst clear we Write Enable we 1 we 0 if clk 1 Q if rst =

if clear = 1 then Q <= ; elsif we = 1 then Q <= D; end rtl; regs.vhdl clk 0 1 rst clear we Write Enable we 1 we 0 if clk 1 Q if rst = VHDL 2 1 VHDL 1 VHDL FPGA VHDL 2 HDL VHDL 2.1 D 1 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; regs.vhdl entity regs is clk, rst : in std_logic; clear : in std_logic; we