VBI VBI FM FM FM FM FM DARC DARC
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- ことこ やまのかみしゃ
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1 14 2 7
2 VBI VBI FM FM FM FM FM DARC DARC DARC parity i
3 ECC Difference ,XOR SB(20) SB(20) SB(20) ii
4 TRANSMITTER TRANSMITTER VHDL RECEIVER RECEIVER VHDL VHDL ERRORCNT iii
5 1 BS VHDL VHDL 5 DesignWave
6 [1],[2],[10],[11],[12] JR VBI2.1.3 BS CS Sky PerfecTV Sky PerfecPC VBI I Q
7 NHK 1989 A B VBI 2.1 3
8 VBI VBI 30 VBIVertical Blanking Interval 4
9 VBI VBI 2.3VBI 5
10 VBI 22 14H,15H,16H, 21H 277H,278H,279H,283H 17H 20H VITS VBI VBI VBI 10KB VBI
11 4 VBI E-NEWS TBS VBI 10KB VBI 4 40KB ADAMS:TV-Asahi Data and Multimedia ServiceTBS PC HTML VBI TV/ TV/ 7
12
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14 NHK BEST Burst and random Error System for Teletext BEST
15 2.2FM FM FM FM FM FM 1994 FM NHK FM JFN(Japan FM Network) J-WAVE FM802 Watch-me Kiss-FM KOBE Kiwi FM FM LR kHz carrier FMFrequency Modulation [*1] 38kHz [sub carrier] [*2] 76kHz DAta Radio Channel
16 Level control MSK[*3] 16kbps [*4] 8kbps 15 2 [*1] Amplitude Modulation Phase Modulation [*2] 5015kHz 38kHz±15kHz 2 [*3] AMFMPM ASKAmplitude Shift Keying FSKFrequency Shift KeyingPSKPhase Shift Keying MSK Minimum Shift Keying 0 1 FSK ±90 [*4] FM BESTBurst and random Error correction System for Teletext 12
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18 2.2.4 FM FM DARC DARC DARC DARCDAta Radio Channel kbit/sec DARC DARC DARC DARC / 14
19 176bit 32bit 16bit VICS 16bit JIS (SHIFT JIS ) 15
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21 3 [9] Design Wave (parity) parity (parity check) (parity bit) 17
22 PC 8bit 1bit byte 1 1bit
23
24 ( )
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30 Parity bit = D0 xor D1 xor D2 xor D3 xor D4 xor D5 xor D6 xor D7 = (D0 xor D1) xor (D2 xor D3) xor (D4 xor D5) xor (D6 xor D7) Parity bit XOR
31 3.4 XOR
32 D7,D6,D5,D4,D3,D2,D1,D0,Parity XOR 1 Error = D0 xor D1 xor D2 xor D3 xor D4 xor D5 xor D6 xor D7 xor P Error PParity bit Error 1 Error XOR Error
33 XOR Error
34 3.1 Error
35 Difference difference intersection difference A={1,2,3,4,6,12}, B={1,2,3,6,9,18} {1,2,3,4,6,12}{1,2,3,6,9,18}{4,12} 31
36 32
37 3.2.2 S =A1,A2,A3,A4,A5 5 1 S = { A1,A2,A3,A4,A5}S = { A2,A3,A4, A5, A1} S = {A3,A4,A5, A1,A2}S = {A4, A5, A1,A2,A3} S = {A5, A1 A2,A3,A4}S = { A1,A2,A3, A4, A5, }
38
39 XOR SBSent Bits XOR XOR = SB(9) xor SB(12) xor SB(13) xor SB(18) xor SB(20) = 0 xor 1 xor 1 xor 1 xor 1 =
40 SB(20) 3.4 SB(20) SB(20) SB(20) = SB(9) xor SB(12) xor SB(13) xor SB(18) xor SB(20) = 0 xor 1 xor 1 xor 1 xor 0 = = SB(1) xor SB(11) xor SB(14) xor SB(15) xor SB(20) = 0 xor 1 xor 1 xor 1 xor 0 =
41 = SB(4) xor SB(6) xor SB(16) xor SB(19) xor SB(20) = 0 xor 1 xor 1 xor 1 xor 0 = 1 1 = SB(0) xor SB(5) xor SB(7) xor SB(17) xor SB(20) = 0 xor 0 xor 0 xor 1 xor 0 = 1 1 = SB(2) xor SB(3) xor SB(8) xor SB(10) xor SB(20) = 1 xor 1 xor 0 xor 1 xor 0 = XOR SB(20) 37
42 = SB(9) xor SB(12) xor SB(13) xor SB(18) xor SB(20) = 0 xor 1 xor 1 xor 1 xor 1 = = SB(1) xor SB(11) xor SB(14) xor SB(15) xor SB(20) = 0 xor 1 xor 1 xor 1 xor 1 = 0 1 = SB(4) xor SB(6) xor SB(16) xor SB(19) xor SB(20) = 0 xor 1 xor 1 xor 1 xor 1 =
43 SB(20) 39
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46 U(x) 10 42
47 43
48 10 r0,r1,r2,r3,r4,r5,r6,r7, r8,r9 44
49 A 45
50
51 4 VHDL LeonardoSpectrum LS2001_1a_31 VHDL Design Wave
52 Transmitter RECEIVER ERRORCNT SB SBWE START START RBWE RBEC 48
53 RBEC START2 START START2 RB RBEC 8 49
54 4.2 TRANSMITTER TRANSMITTER 4.2.1TRANSMITTER TRANSMITTER TRANSMITTER 2.1. TV TV TRANSMITTER TRANSMITTER TRANSMITTER errsig 50
55 START 21 RECEIVER TRANSMITTER 51
56 Phase infbit IN intsb intsb infbit infbit 10 parity 0 1 errsig 33 0 parity(9) intsb2 intsb2 SB errsig SBWE START 21 START 52
57 4.2.4 ALTERA MAX+plus 10.1 BASELINE [2],[3],[4] TRANSMITTER VHDL TRANSMITTER
58 4.2.5VHDL library IEEE; use IEEE.STD_LOGIC_1164.all, IEEE.STD_LOGIC_unsigned.all; entity TRANSMITTER is Port (SBWE: out std_logic; SB : out std_logic; START : out std_logic; RESET : in std_logic; CLK : in std_logic ); end TRANSMITTER; architecture RTL of TRANSMITTER is signal phase : std_logic_vector (5 downto 0); -- phase counts from 0 to phase 0 to 20 : sync bits are transmitted -- phase 21 to 31 : information bits transmitted -- phase 32 to 41 : parity bits transmitted signal infbit : std_logic_vector (10 downto 0); -- 11bits information bits signal intstart : std_logic; -- internal start signal signal intsb,intsb2 : std_logic; -- internal sb signal signal parity : std_logic_vector (9 downto 0); parity bits signal errsig : std_logic; -- error signal signal errcnt : std_logic_vector (9 downto 0); -- error counter begin phase (0 to 41 counter) generation unit PHASE_CNT: process(clk,reset) 54
59 begin if (RESET='1') then phase <= "000000"; elsif rising_edge(clk) then if (phase="101001") then -- if phase=41 phase <= "000000"; else phase <= phase + 1; end if; end if; end process PHASE_CNT; bits information generation unit -- count down from by INF_GEN: process(clk, RESET) begin if (RESET='1') then infbit <= " "; elsif rising_edge(clk) then if (phase="010100") then -- if phase=20 infbit <= infbit - 1; end if; end if; end process INF_GEN; internal start (intstart) generation START_GEN: process(clk, RESET) begin if (RESET='1') then intstart <= '0'; elsif rising_edge(clk) then if (phase="010101") then -- if phase=21 intstart <= '1'; 55
60 else intstart <= '0'; end if; end if; end process START_GEN; internal sb signal (intsb) generation SB_GEN: process(clk, RESET) begin if (RESET='1') then intsb <= '0'; elsif rising_edge(clk) then case phase is when "000000"=> intsb <= '0'; -- 0 when "000001"=> intsb <= '0'; -- 1 when "000010"=> intsb <= '1'; -- 2 when "000011"=> intsb <= '1'; -- 3 when "000100"=> intsb <= '0'; -- 4 when "000101"=> intsb <= '1'; -- 5 when "000110"=> intsb <= '0'; -- 6 when "000111"=> intsb <= '1';-- 7 when "001000"=> intsb <= '1'; -- 8 when "001001"=> intsb <= '1'; -- 9 when "001010"=> intsb <= '1'; --10 when "001011"=> intsb <= '0'; --11 when "001100"=> intsb <= '1'; --12 when "001101"=> intsb <= '1'; --13 when "001110"=> intsb <= '1';--14 when "001111"=> intsb <= '0'; --15 when "010000"=> intsb <= '0'; --16 when "010001"=> intsb <= '0'; --17 when "010010"=> intsb <= '0'; --18 when "010011"=> intsb <= '0'; --19 when "010100"=> intsb <= '0'; --20 when "010101"=> intsb <= infbit(10);
61 when "010110"=> intsb <= infbit(9); --22 when "010111"=> intsb <= infbit(8); --23 when "011000"=> intsb <= infbit(7); --24 when "011001"=> intsb <= infbit(6); --25 when "011010"=> intsb <= infbit(5); --26 when "011011"=> intsb <= infbit(4); --27 when "011100"=> intsb <= infbit(3); --28 when "011101"=> intsb <= infbit(2); --29 when "011110"=> intsb <= infbit(1); --30 when "011111"=> intsb <= infbit(0); --31 when others => intsb <= 'X'; --others end case; end if; end process SB_GEN; parity calculation PARITY_CAL: process(clk, RESET) begin if (RESET='1') then parity <= " "; elsif rising_edge(clk) then if (phase="010101") then parity <= " "; elsif (phase>="010110" and phase<="100000") then parity(9) <= parity(8); parity(8) <= parity(7); parity(7) <= parity(6) xor intsb xor parity(9); parity(6) <= parity(5) xor intsb xor parity(9); parity(5) <= parity(4); parity(4) <= parity(3) xor intsb xor parity(9); parity(3) <= parity(2); parity(2) <= parity(1) xor intsb xor parity(9); parity(1) <= parity(0); 57
62 parity(0) <= intsb xor parity(9); else parity <= parity(8 downto 0) & parity(9); end if; end if; end process PARITY_CAL; error interval counter ERR_CNT: process (CLK, RESET) begin if (RESET='1') then errcnt <= " "; elsif rising_edge(clk) then if (errcnt = " ") then -- max=9 (0-9) errcnt <= " "; else errcnt <= errcnt +1; end if; end if; end process ERR_CNT; error signal generation ERROR_GEN: process (CLK, RESET) begin if (RESET='1') then errsig <= '0'; elsif rising_edge(clk) then if (errcnt=" ") then errsig <= '1';-- error happens every 10 else errsig <= '0'; end if; end if; end process ERROR_GEN; output signals
63 SBOUT: process (CLK, RESET) begin if (RESET='1') then intsb2 <= '0'; elsif rising_edge(clk) then if(phase >="100001" or phase="000000") then intsb2 <= parity(9); else intsb2 <= intsb; end if; end if; end process SBOUT; startout STARTOUT: process (CLK, RESET) begin if (RESET='1') then START <= '0'; elsif rising_edge(clk) then START <= intstart; end if; end process STARTOUT; SB <= intsb2; SBWE <= intsb2 xor errsig; end RTL; 59
64 LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; ENTITY testbench IS END testbench; ARCHITECTURE behavior OF testbench IS COMPONENT transmitter PORT( RESET : IN std_logic; CLK : IN std_logic; SBWE : OUT std_logic; SB : OUT std_logic; START : OUT std_logic ); END COMPONENT; SIGNAL cycle : integer := 0; SIGNAL SBWE : std_logic; SIGNAL SB : std_logic; SIGNAL START : std_logic; SIGNAL RESET : std_logic:= '1'; SIGNAL CLK : std_logic:= '0'; BEGIN uut: transmitter PORT MAP( SBWE => SBWE, SB => SB, START => START, RESET => RESET, CLK => CLK ); 60
65 process begin if (cycle < 300)then cycle <= cycle +1; wait for 10 ns; CLK <= not CLK; else wait; end if; end process; process begin RESET_LOOP: for N IN 0 to 3 loop wait until falling_edge(clk); end loop RESET_LOOP; RESET <= '0'; CAL_LOOP: for N in 0 to 500 loop wait until falling_edge(clk); end loop CAL_LOOP; end process; end architecture behavior; 4.4TRANSMITTER 61
66 4.2.6 LeonardoSpectrum LS2001_1a_ LeonardoSpectrum LS2001_1a_ TRANSMITTER UNIT
67 4.350 XOR Critical path #1, (unconstrained path) NAME GATE ARRIVAL LOAD A(36)/ up 0.08 ix69/x XR2T up 0.08 ix255/x XN3R up 0.14 ix75/x XN2R dn 0.08 ix91/x XN3R up 0.09 ix95/x XR3T up 0.21 ix97/x XR3T up 0.04 Y/ up 0.00 data arrival time 2.99 data required time not specified data required time not specified data arrival time unconstrained path ******************************************************* Cell: xor50inputs View: RTL Library: work ******************************************************* Cell Library References Total Area XN2R0 scl05u 3 x 5 15 gates XN3R0 scl05u 9 x 7 61 gates XR2T0 scl05u 12 x 5 59 gates XR3T0 scl05u 8 x 7 54 gates Number of ports : 51 Number of nets : 82 Number of instances : 32 Number of references to this view : 0 Total accumulated area : Number of gates :
68 64
69 65
70 4.5TRNSMITTER 66
71 4.3 RCEIVER RECEIVER 4.3.1RCEIVER RECEIVER RECEIVER 2.1. TV/ RECEIVER Ensig 1 RBWE START 1 42 N 41 2 Ensig 1 START2 RBEC START2 67
72 , IN TRANSMITTER SBWE= RBWE CLKCLOCK RESETRESET OUT RECEIVER RBWE START2 OUT START2 4.6RECEIVER 68
73 Phase EN ENsig ENsig RBWE 21 INPUT INPUT Esig Parity(9) ER_out S_erc_out S_erc_out 41 0 A1+A2 + A3 + A4 + A5 3 P_out ENsig 0 P_out ER_out 21 INPUT REG_Q(20) ER_out REG_Q(20) RBEC START2 START2 69
74 4.7 70
75 4.3.4 TRANSMITTER ALTERA MAX+plus 10.1 BASELINE
76 4.3.5VHDL library IEEE; use IEEE.STD_LOGIC_1164.all, IEEE.NUMERIC_STD.all; entity RECEIVER is Port ( START : in std_logic; RBWE : in std_logic; START2 : out std_logic; RBEC : out std_logic; RESET : in std_logic; CLK : in std_logic ); end RECEIVER; architecture RTL of RECEIVER is signal INPUT : std_logic; signal ENsig : std_logic; signal phase : unsigned (5 downto 0); signal intstart : std_logic; signal parity : unsigned (9 downto 0); signal REG_Q : unsigned (20 downto 0 ); signal P_out : std_logic; signal ER_out : std_logic; signal S_erc_out : std_logic; signal A1,A2,A3,A4,A5 : std_logic; begin -- RBWE input to the receiver -- ENABLE signal -- phase signals -- internal start signal parity bits -- 21bits sifht register signals -- output signal of majority circuit -- Error correction signal -- Input signal to the error check circuit -- parity check signals 72
77 phase (41 downto 0 counter) generation unit PHASE_CNT1: process(clk,reset) begin if (RESET='1') then phase <= "000000"; elsif rising_edge(clk) then if (START='1')then phase <= "101001"; elsif (phase= "000000")then phase <= "000000"; else phase <= phase -1; end if; end if; end process PHASE_CNT1; ENABLE signal1 generation EN1_GEN: process (START,phase) begin if (phase>="010110" and phase<="101001")then ENsig <='1'; else ENsig <='0'; end if; end process EN1_GEN; Controlled RBWE siganl RB_n: process(clk,ensig) begin if(ensig='1')then INPUT <= RBWE; 73
78 else INPUT <= '0'; end if; end process RB_n; bit SHIFT_REGISTER SFIT_R21: process(clk, RESET) begin if ( RESET = '1') then REG_Q <= ( others => '0'); elsif rising_edge(clk) then REG_Q(0) <= INPUT; REG_Q (20 downto 1) <= REG_Q (19 downto 0); end if; end process; Internal start2 (intstart) generation START_GEN: process(clk, RESET) begin if (RESET='1') then intstart <= '0'; elsif rising_edge(clk) then if (phase="010111") then intstart <= '1'; else intstart <= '0'; end if; end if; end process START_GEN; Input to the error_checker S_erc_out <= (INPUT and ENsig) xor parity(9) xor ER_out; 74
79 Parity_calculation PARITY_CAL: process(clk,reset,phase) begin if (RESET='1') then parity <= " "; elsif rising_edge(clk) then if (phase>="000000" and phase<="101001")then parity(9) <= parity(8); parity(8) <= parity(7); parity(7) <= parity(6) xor parity(9); parity(6) <= parity(5) xor parity(9); parity(5) <= parity(4); parity(4) <= parity(3) xor parity(9); parity(3) <= parity(2); parity(2) <= parity(1) xor parity(9); parity(1) <= parity(0); parity(0) <= S_erc_out; end if; end if; end process PARITY_CAL; Parity input to the parity_checker A1 <= parity(9); A2 <= parity(1); A3 <= parity(4) xor parity(6); A4 <= parity(0) xor parity(5) xor parity(7); A5 <= parity(2) xor parity(3) xor parity(8); Output from the majority circuit PROCESS (A1,A2,A3,A4,A5) BEGIN 75
80 if (A1='1' and A2='1' and A3='1')then P_out <= '1'; elsif (A4='1' and A5='1')then P_out <= A1 or A2 or A3; elsif (A1='1' and A2='1') then P_out <= A4 or A5; elsif (A3='1' and A5='1')then P_out <= A1 or A2; elsif (A3='1' and A4='1')then P_out <= A1 or A2; else P_out <= '0'; end if; end process; Output from signal of ERROR checker ER_out <= P_out and not ENsig; Output signal RBEC <= (REG_Q(20) xor ER_out); Startout STARTOUT2: process (CLK, RESET) begin if (RESET='1') then START2 <= '0'; elsif rising_edge(clk) then START2 <= intstart; end if; end process STARTOUT2; end RTL; 76
81 4.6RECEIVER 1/5 LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; ENTITY testbench IS END testbench; ARCHITECTURE behavior OF testbench IS COMPONENT receiver PORT( START : IN std_logic; RBWE : IN std_logic; RESET : IN std_logic; CLK : IN std_logic; START2 : OUT std_logic; RBEC : OUT std_logic ); END COMPONENT; SIGNAL cycle : integer := 0; SIGNAL START : std_logic; SIGNAL RBWE : std_logic; SIGNAL START2 : std_logic; SIGNAL RBEC : std_logic; SIGNAL RESET : std_logic:= '1'; SIGNAL CLK : std_logic:= '0'; BEGIN uut: receiver PORT MAP( START => START, RBWE => RBWE, START2 => START2, RBEC => RBEC, RESET => RESET, CLK => CLK ); 77
82 4.6RECEIVER 2/5 process begin if (cycle < 300)then cycle <= cycle +1; wait for 10 ns; CLK <= not CLK; else wait; end if; end process; process begin RESET_LOOP: for N IN 0 to 3 loop wait until falling_edge(clk); end loop RESET_LOOP; RESET <= '0'; CAL_LOOP: for N in 0 to 500 loop wait until falling_edge(clk); end loop CAL_LOOP; end process; process begin RBWE <= '0'; wait for 80 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '0'; wait for 20 ns; RBWE <= '0'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '0'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '0'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '1'; 78
83 4.6RECEIVER 3/5 wait for 20 ns; RBWE <= '0'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '0'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '0'; wait for 20 ns; RBWE <= '0'; wait for 20 ns; RBWE <= '0'; wait for 20 ns; RBWE <= '0'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '0'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '0'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '0'; wait for 20 ns; RBWE <= '0'; wait for 20 ns; RBWE <= '0'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '0'; wait for 20 ns; RBWE <= '0'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '0'; wait for 20 ns; RBWE <= '0'; 79
84 4.6RECEIVER 4/5 wait for 20 ns; RBWE <= '0'; wait for 20 ns; RBWE <= '0'; wait for 20 ns; RBWE <= '0'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '0'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '0'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '0'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '0'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '0'; wait for 20 ns; RBWE <= '0'; wait for 20 ns; RBWE <= '0'; wait for 20 ns; RBWE <= '0'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '0'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '0'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '1'; 80
85 4.6RECEIVER 5/5 wait for 20 ns; RBWE <= '0'; wait for 20 ns; RBWE <= '0'; wait for 20 ns; RBWE <= '0'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '0'; wait for 20 ns; RBWE <= '0'; wait for 20 ns; RBWE <= '0'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '0'; wait for 20 ns; RBWE <= '0'; wait for 20 ns; RBWE <= '1'; wait for 20 ns; RBWE <= '0'; wait; end process; process begin START <= '0'; wait for 520 ns; START <= '1'; wait for 20 ns; START <= '0'; wait for 820 ns; START <= '1'; wait for 20 ns; START <= '0'; wait; end process; end architecture behavior; 4.10RECEIVER 81
86 4.3.6 LeonardoSpectrum LS2001_1a_ XOR RECEIVER UNIT RECEIVER 1/3 Critical Path Report Critical path #1, (unconstrained path) NAME GATE ARRIVAL LOAD clock information not specified delay thru clock network 0.00 (ideal) reg_phase(1)/q FD1B dn 0.20 ix579/x NR2R up 0.19 ix47/x ND2N dn 0.27 ix576/x NR2R up 0.19 ix79/x ND2N dn
87 4.7RECEIVER 2/3 ix573/x NR2R up 0.16 ix571/x NR2R dn 0.17 ix11/x AN2T dn 0.11 reg_phase(0)/d FD1B dn 0.00 data arrival time 3.93 data required time not specified data required time not specified data arrival time unconstrained path ****************************************************** Cell: RECEIVER View: RTL Library: work ******************************************************* Cell Library References Total Area AN2T0 scl05u 5 x 5 24 gates AO1A0 scl05u 1 x 6 6 gates AO2L0 scl05u 2 x 8 15 gates AOA4I0 scl05u 1 x 8 8 gates AOA4I2 scl05u 1 x 8 8 gates FD1B0 scl05u 29 x gates FD1I0 scl05u 9 x gates FD1I1 scl05u 1 x gates IV1N0 scl05u 3 x 3 9 gates IV1NP scl05u 2 x 4 8 gates ND2N0 scl05u 5 x 5 23 gates NR2R0 scl05u 4 x 5 18 gates NR3R0 scl05u 1 x 6 6 gates NR4R1 scl05u 1 x 8 8 gates OAI1A0 scl05u 3 x 6 19 gates OAI3R2 scl05u 1 x 8 8 gates 83
88 4.7RECEIVER 3/3 XN2R0 scl05u 10 x 5 49 gates XN3R0 scl05u 3 x 7 20 gates Number of ports : 6 Number of nets : 89 Number of instances : 82 Number of references to this view : 0 Total accumulated area : Number of gates : RECEIVER 84
89 VHDL TRANSMITTER RECEINVER ERRORCNT 85
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97 VHDL FPGA DesignWave
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99 [8] Design Wave Magagin CQ [9] Design Wave Magagin CQ [10] NHK informationhttp:// [11] FM [12] ON-LINE Bit Bit Bit 95
if clear = 1 then Q <= " "; elsif we = 1 then Q <= D; end rtl; regs.vhdl clk 0 1 rst clear we Write Enable we 1 we 0 if clk 1 Q if rst =
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1 1 2 2 2-1 2 2-2 4 2-3 11 2-4 12 2-5 14 3 16 3-1 16 3-2 18 3-3 22 4 35 4-1 VHDL 35 4-2 VHDL 37 4-3 VHDL 37 4-3-1 37 4-3-2 42 i
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VHDL 1030192 15 2 10 1 1 2 2 2.1 2 2.2 5 2.3 11 2.3.1 12 2.3.2 12 2.4 12 2.4.1 12 2.4.2 13 2.5 13 2.5.1 13 2.5.2 14 2.6 15 2.6.1 15 2.6.2 16 3 IC 17 3.1 IC 17 3.2 T T L 17 3.3 C M O S 20 3.4 21 i 3.5 21
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1 1. 2 2. 3 isplever 4 5 6 7 8 9 VHDL 10 VHDL 4 Decode cnt = "1010" High Low DOUT CLK 25MHz 50MHz clk_inst Cnt[3:0] RST 2 4 1010 11 library ieee; library xp; use xp.components.all; use ieee.std_logic_1164.all;
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お客様各位 カタログ等資料中の旧社名の扱いについて 2010 年 4 月 1 日を以って NEC エレクトロニクス株式会社及び株式会社ルネサステクノロジが合併し 両社の全ての事業が当社に承継されております 従いまして 本資料中には旧社名での表記が残っておりますが 当社の資料として有効ですので ご理解の程宜しくお願い申し上げます ルネサスエレクトロニクスホームページ (http://www.renesas.com)
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F9222L_Datasheet.pdf
Introduction Fuji Smart power device M-POWER2 for Multi-oscillated current resonant type power supply Summary System: The ideal and Fuji s original system It includes many functions(soft-switching,stand-by).
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MachXO2 EFB(Embedded Function Block) 1 目次 1 このドキュメントの概要 3 2 EFB の構成 4 3 EFB とハードマクロの生成と注意事項 5 3.1 EFB Enables タブの設定... 5 3.2 I2C タブの設定... 6 3.3 SPI タブの設定... 7 3.4 Timer/Counter タブの設定... 9 4 Wishbone から
2017 (413812)
2017 (413812) Deep Learning ( NN) 2012 Google ASIC(Application Specific Integrated Circuit: IC) 10 ASIC Deep Learning TPU(Tensor Processing Unit) NN 12 20 30 Abstract Multi-layered neural network(nn) has
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dr-timing-furukawa4.pptx[読み取り専用]
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< kazuro.furukawa @ kek.jp > 1 2 Remote controlled automatic pattern arbitrator" Manual pattern generator" Recent typical operation. ~37Hz for KEKB LER (3.5GeV e+) ~12.5Hz for KEKB HER (8GeV e ) ~0.5Hz
MOTIF XF 取扱説明書
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LM2940
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ELCODIS.COM - ELECTRONIC COMPONENTS DISTRIBUTOR
IC : = 2 MHz Max 2 : : TSSOP-20 RJJ03D0873-0200 Rev.2.00 2008.07.01 VIN Vout + DC 5 V DC 5 V DC 5 V DC 5 V DC 5 V Vbias (DC 12 V) VCC OUT -A GND OUT -B CS RAMP R2A20121 RT SYNC SS FB (+) OUT -C DELAY -1
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Network Product Guide Network Monitoring System Network Product Guide Time stamp Write to disk Filter Convert Summarise Network Product Guide Network Monitoring System TDS2 TDS24 Network Analysis Report
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Ver.1.04 Reference Document For LCD Module Product No Documenet No 1B3GB02 SPC1B3GB02V104 Version Ver.1.04 REPRO ELECTRONICS CORPORATION Maruwa Building 2F,2-2-19 Sotokanda,Chiyoda-ku,Tokyo 1001-0021 Japan
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VLD Kazutoshi Kobayashi
VLD Kazutoshi Kobayashi (kobayasi@kuee.kyoto-u.ac.jp) 2005 8 26-29 1, Verilog-HDL, Verilog-HDL. Verilog-HDL,, FPGA,, HDL,. 1.1, 1. (a) (b) (c) FPGA (d). 2. 10,, Verilog-HDL, FPGA,. 1.2,,,, html. % netscape
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