VHDL

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1 VHDL 4 4

4 FIRIIR A/D D/A NOSCOS LSI FIR IIR

5 x a x a a ; ; H a H T j e T j e T j T a j T a T j T a e a H e H T j sin cos sin cos T j I T j R T a e H T a e H sin cos tan T j R T j I T j T j I T j R T j e H e H e H e H e H e H ] [ log db e H T j

6 3 nts,,,,, n n n Ts n nts nts n n n n n n Ts Ts Ts Ts Ts nts Ts nts nts nts H,,, Ts Ts Ts

7 H H H jts e Tscos Tse jts Tscos Ts Ts H Ts H Ts Ts Ts H d Ts d H d Ts Ts Ts jts Ts H d e d Ts Ts A A A Ts f Ts Tscos Ts H d H d d NTs f H,,, N f NTs NTs N d N j N Ts H f e,,, Ts 4

8 N f Af,,, N N f f,, N A N 5

9 a x N n b n n a n x H A H A a B N n B bn n A B b x b ; x x ; ; b 6

10 b 7

11 b b H b B b p p b p bn 8

12 H s H H s H 9

13 H j N c c c rad sec rad sec s j s j c H j N N s s j s s N N,, N N N

14 j s j s j s s s s j s j s s s H

15 ,,, cos N N s s s H N N N,,,, cos 3 N N s s s s H N N N N sec rad,,, cos N N s s s H N N N,,,, cos 3 N N s s s s H N N N N j B R j B I j H N e N N tan p A N p r A N r

16 r p N Ar Ap log N A A r p log r p A p p N p A r r N r p r p r H s 3

17 4

18 H 3, , Ts Ts 4 N j N d e,,, N Ts H f Ts 5

19 a 3..,,, Ts Ts Ts Ts

20 Ts cos Ts 4 6 7

21 FIR x x H H H H 8

22 Ts.4-4 Ts 96H f p 44H, f r 536H Ap 4dB, Ar 5dB A DT tan T p r Tstan 44 Ts 9788rad / s Tstan 536Ts 5539rad / s log N A A r p log r p [ p], [ r] [ p] [ r] a A r p [ p] r p [ r] N N 445 H s s /..3. N cos / / N s / 9

23 s G s s s s T s 4 log 9.6 s ana s G s H digital IIR b b a a a H b b a a a IIR n b n b b b

24 FIR IIR A tan H H R H H I R I

25 H H R H H R H I H H H H a l l b l jts e a l e jts b e l jlts H I H digital e jts H digital jts e.84e jts.458 e.4995 e jts jts jts e costs j sints costs j sin Ts.84cos Ts j sin Ts.458cosTs j sin Ts.4995cos Ts j sin Ts costs j.4568 sin Ts.84 cos Ts j.84 sin Ts.458cosTs j.458sin Ts.4995 cos Ts j.4995 sin Ts A costs.84 cos Ts.4568 sin Ts.84 sin Ts.458cosTs.4995 cos Ts.458sin Ts.4995 sin Ts tan.4568 sin Ts.84 sin Ts tan costs.84 cos Ts.458sin Ts.4995 sin Ts.458cosTs.4995 cos Ts

26 IIR FIR IIR N n b n n a FIR n 3

27 H H H H FIR 4

28 VHDL VHDL FIR IIR x nts x nts,, x nts, N nts x i nts i nts axnts x nts a N Ts nts xn Ts 5

29 6 FIR FIR a H x a x

30 7

31 8 bit, 6bit 8bit. n FIR

32 IIR IIR N b n n n a x FIR D IIR FIR IIR x n b n n a x N n FIR 9

33 3 VHDL IIR IIR FIR FIR n 8bit n x.5 IIR

34 VHDL FIR IIR FIR IIR FIR 8 IIR 65 FIR 8Ts IIR 65Ts FIR 3

35 FIR 8 H 96H H 7H 35H 3

36 IIR IIR r p A A r p log N log IIR r p 33

37 IIR 34

38 8 FIRIIR FIR IIR FIR IIR IIR CDDA FIR FIR IIR 35

39 9. 36

40 . Jaara Baser 37

41 FIR IIR C VHDL 8 FIR #include <stdio.> #include <at.> #include <conio.> #define n /* */ #define 4 /* FIR */ float sfr[+],sfi[+]; float lfr[n],lfi[n]; float pi; void idft int, int ; void ilpf int ; void LPW void ; void ain void { LPW; getc; void idft int N, int { int i,; float oega; for i=; i<=-; ++i { sfr[i]=.; /* */ sfi[i]=.; /* */ 38

42 for =; <=N-; ++ { oega=.*pi*floati*float/floatn; /* */ sfr[i]+=lfr[]*cosoega-lfi[]*sinoega; /* IDFT */ sfi[i]*=lfi[]*cosoega+lfr[]*sinoega; /* IDFT */ for i=; i<=-; ++i /* /N */ { sfr[i]/=floatn; sfi[i]/=floatn; void ilpf int N /* LPF */ { int i; for i=; i<=3; ++i { lfr[i]=.; for i=69; i<=n-; ++i { lfr[i]=.; lfr[3]=.5; lfr[68]=.5; for i=3; i<=67; ++i { lfr[i]=.; for i=; i<=n-; ++i { /* */ lfi[i]=.; void LPW void { int i; 39

43 pi=acos-.; /* */ ilpf n ; /* N */ idft n, + ;/* + */ for i=; i<=; ++i { printf"a%dts = %f = a%dts n",i,sfr[i],*-i; for i=; i<=; ++i { printf"a%dts = %f = a%dts n",i,sfr[i],*-i; oega=.*pi*floati; ap=sfr[]; for =; <=; ++ { ap+=.*sfr[]*cosfloat*oega*ts; ap=sqrtap*ap; printf" H5%d = %f n",i,.*logap; FIR #include <at.> #include <stdio.> #include <conio.> #define 8 void ain void { 4

44 int i,; double,x[+],a[+]; double pi,ts=.4e-4; pi=acos-.; for =; <=; ++ { x[]=.; a[]=.35; a[]=.6599; a[]=.45945; a[3]=.89; a[4]=-.5789; a[5]=-.6585; a[6]=-.7838; a[7]=.78; a[8]=.399; a[9]=.733; a[]=-.455; a[]=-.85; a[]=-.64; a[3]=.695; a[4]=.963; a[5]=.695; a[6]=-.64; a[7]=-.85; a[8]=-.455; a[9]=.733; a[]=.399; a[]=.78; a[]=-.7838; a[3]=-.6585; a[4]=-.5789; a[5]=.89; a[6]=.45945; a[7]=.6599; a[8]=.35; 4

45 for i=; i<=; ++i { x[]=.*sin.*pi**doublei*ts; x[]+=.*sin.*pi**doublei*ts; =.; for =; <=; ++ { +=a[]*x[]; for =; >=; --{ x[]=x[-]; printf"i = %d x = %f = %f n",i,x[],; getc; 4

46 FIR #include <at.> #include <stdio.> #include <conio.> #define 8 void ain void { int i,; double,x[+],a[+]; double pi,ts=.4e-4,freq=.; pi=acos-.; for =; <=; ++ { x[]=.; a[]=.35; a[]=.6599; a[]=.45945; a[3]=.89; a[4]=-.5789; a[5]=-.6585; a[6]=-.7838; a[7]=.78; a[8]=.399; a[9]=.733; a[]=-.455; a[]=-.85; a[]=-.64; a[3]=.695; a[4]=.963; a[5]=.695; a[6]=-.64; a[7]=-.85; 43

47 a[8]=-.455; a[9]=.733; a[]=.399; a[]=.78; a[]=-.7838; a[3]=-.6585; a[4]=-.5789; a[5]=.89; a[6]=.45945; a[7]=.6599; a[8]=.35; for i=; i<=; ++i { if i=={ x[]=.; else { x[]=.; =.; for =; <=; ++ { +=a[]*x[]; for =; >=; --{ x[]=x[-]; printf"i = %d x = %f = %f n",i,x[],; getc; 44

48 IIR #include <stdio.> #include <at.> #include <conio.> void ain void { double pi=3.459; double outp,outr,ts,frequencp,frequencr; printf" Ts [s]= "; scanf"%lf",&ts; printf" p[h] = "; scanf"%lf",&frequencp; printf" r[h] = "; scanf"%lf",&frequencr; outp=/ts*tan*pi*frequencp*ts/; outr=/ts*tan*pi*frequencr*ts/; printf"oega[p] = %f, oega[r] = %f n",outp,outr; getc; 45

49 #include <stdio.> #include <at.> #include <conio.> void ain void { double n,ar,ap,wp,wr,x,; printf" a[r] = "; scanf"%lf",&ar; printf" a[p] = "; scanf"%lf",≈ printf" w[r] = "; scanf"%lf",&wr; printf" w[p] = "; scanf"%lf",&wp; x=pow,ar/; =pow,ap/; n=logx-/-/*logwr/wp; printf" N = %f n",n; getc; 46

50 #include <stdio.> #include <at.> #include <conio.> void ain void { double ap,,n,oega,wp; printf"wp="; scanf"%lf",&wp; printf"ap="; scanf"%lf",≈ printf"n="; scanf"%lf",&n; =wp; /=powpow,ap/-,/*n; oega=; printf"oega= %f n",oega; getc; IIR #include <at.> #include <stdio.> #include <conio.> #define void ain void { int i,; double x,,v[+],a[+],b[+]; double pi,freq,ts=.4e-4; pi=acos-.; 47

51 for =; <=; ++ { v[]=.; a[]=.84; a[]=.4568; a[]=.84; b[]=.458; b[]=.4995; printf" freq = "; scanf"%lf",&freq; for i=; i<=; ++i { if i== { x=.; else { x=.; v[]=x; for =; <=; ++ { v[]+=b[]*v[]; getc; =.; for =; <=; ++{ +=a[]*v[]; for =; >=; --{ v[]=v[-]; printf"i = %d x = %f =%f n",i,x,; 48

52 IIR #include <stdio.> #include <at.> #include <conio.> void ain void { int i; double oega,denoi; double denoi_real,denoi_iagi; double nue; double ap; double pi,freq,ts,pase; pi=acos-.; ts=.4e-4; for i=; i<=48; ++i { freq=doublei*.; oega=.*pi*freq; denoi_real=.595*cosoega*ts-.458; denoi_iagi=.4995*sinoega*ts; denoi=powdenoi_real,.; denoi+=powdenoi_iagi,.; nue=+*cosoega*ts; ap=.84*nue/sqrtdenoi; pase=-atandenoi_iagi/denoi_real; printf" H%5d = %f PHASE= %f n",i,*logap,pase; getc; IIR #include <at.> #include <stdio.> #include <conio.> 49

53 #define void ain void { int i,; double x,,v[+], a[+],b[+]; double pi,ts=.4e-4; pi=acos-.; for =; <=; ++ { v[]=.; a[]=.84; a[]=.4568; a[]=.84; b[]=.458; b[]=.4995; for i=; i<=; ++i { x=.*sin.*pi**doublei*ts; x+=.*sin.*pi**doublei*ts; v[]=x; for =; <=; ++ { v[]+=b[]*v[]; =.; for =; <=; ++{ +=a[]*v[]; for =; >=; --{ v[]=v[- ]; printf"i = %d x = %f =%f n",i,x,; getc; 5

54 FIR VHDL librar IEEE; use IEEE.std_logic_64.all; use IEEE.std_logic_arit.all; entit ultiplier_6x is Port RST : In std_logic; -- reset ACCCLK : In std_logic; -- 9Fs A_IN : In std_logic_vector 5 downto ; B_IN : In std_logic_vector downto ; UL_OUT : Out std_logic_vector 7 downto ; end ultiplier_6x; arcitecture STRUCT of ultiplier_6x is signal coeff_in : signed 5 downto ; signal data_in : signed downto ; signal ul_tp : signed 7 downto ; begin gen_coeff_in : process RST, ACCCLK begin ifrst = '' ten coeff_in <= ""; elsif ACCCLK'event and ACCCLK = '' ten for i in 5 downto loop coeff_ini <= A_INi; end loop; end if; end process gen_coeff_in; 5

55 gen_data_in : process RST, ACCCLK begin ifrst = '' ten data_in <= ""; elsif ACCCLK'event and ACCCLK = '' ten for i in downto loop data_ini <= B_INi; end loop; end if; end process gen_data_in; ul_tp <= coeff_in * data_in; gen_ul_out : process RST, ACCCLK begin -- process gen_ultiplied_out ifrst = '' ten UL_OUT <= ""; elsif ACCCLK'event and ACCCLK = '' ten for i in 7 downto loop UL_OUTi <= ul_tpi; end loop; end if; end process gen_ul_out; end; librar IEEE; use IEEE.std_logic_64.all; use IEEE.std_logic_signed.all; entit accuulator is Port RST : In std_logic; -- reset 5

56 ACCCLK : In std_logic; -- 9Fs C_IN : In std_logic_vector7 downto ; ACC_OUT : Out std_logic_vector7 downto ; end accuulator; arcitecture STRUCTURE of accuulator is signal B_tp,C_tp : std_logic_vector 7 downto ; begin -- arcitecture accuulator processc_in,b_tp variable A_tp:std_logic_vector7 downto ; begin A_tp7 downto :=C_IN; C_tp<=A_tp + B_tp; end process; processaccclk begin ifaccclk=''andaccclk'eventten ifrst=''ten B_tp<=oters=>''; else B_tp<=C_tp; end if; end if; end process; processc_tp begin ACC_OUT<=C_tp; end process; end; librar IEEE; 53

57 use IEEE.std_logic_64.all; entit DFF is port D : in std_logic_vector7 downto ; D_OUT : out std_logic_vector7 downto ; RST : in std_logic; OEN:in std_logic; ACCCLK : in std_logic; end DFF; arcitecture struct of DFF is signal Q:std_logic_vector7 downto ; begin processaccclk begin ifaccclk=''andaccclk'eventten ifrst=''ten Q<=oters=>''; else Q<=D; end if; end if; end process; processq,oen begin case OEN is wen ''=> D_OUT<=oters=>'Z'; wen oters => D_OUT<=Q6 downto &''; end case; end process; end struct; 54

58 librar IEEE; use IEEE.std_logic_64.all; use IEEE.std_logic_arit.all; entit fir_top is Port RST : In std_logic; OEN : In std_logic; A_IN: In std_logic_vector5 downto ; B_IN : In std_logic_vector downto ; ACCCLK : In std_logic; Fs aster cloc D_OUT : Out std_logic_vector7 downto ; end fir_top; arcitecture STRUCTURE of fir_top is signal ul_signal : std_logic_vector7 downto ; signal acc_signal : std_logic_vector7 downto ; coponent ultiplier_6x Port RST : In std_logic; ACCCLK : In std_logic; A_IN : In std_logic_vector 5 downto ; B_IN : In std_logic_vector downto ; UL_OUT : Out std_logic_vector 7 downto ; end coponent; coponent accuulator Port RST : In std_logic; ACCCLK : In std_logic; C_IN : In std_logic_vector7 downto ; ACC_OUT : Out std_logic_vector7 downto ; end coponent; 55

59 coponent DFF Port D : in std_logic_vector7 downto ; D_OUT : out std_logic_vector7 downto ; RST : in std_logic; OEN : in std_logic; ACCCLK : in std_logic; end coponent; begin -- arcitecture fir_top ultiplier_6x_: ultiplier_6x port ap RST => RST, ACCCLK => ACCCLK, A_IN => A_IN, B_IN => B_IN, UL_OUT => ul_signal; accuulator_: accuulator port ap RST => RST, ACCCLK => ACCCLK, C_IN => ul_signal, ACC_OUT => acc_signal; DFF_: DFF port ap D => acc_signal, D_OUT => D_OUT, RST => RST, OEN => OEN, ACCCLK => ACCCLK; end; -- arcitecture fir_top FIR VHDL 56

60 LIBRARY IEEE; USE IEEE.std_logic_64.all; USE IEEE.std_logic_arit.all; LIBRARY ieee; USE IEEE.STD_LOGIC_TEXTIO.ALL; USE STD.TEXTIO.ALL; ENTITY testbenc IS END testbenc; ARCHITECTURE testbenc_arc OF testbenc IS -- If ou get a copiler error on te following line, -- fro te enu do Options->Configuration select VHDL 93 FILE RESULTS: TEXT IS OUT "results.txt"; COPONENT fir_top PORT RST : In std_logic; OEN : In std_logic; A_IN : In std_logic_vector 5 DOWNTO ; B_IN : In std_logic_vector DOWNTO ; ACCCLK : In std_logic; D_OUT : Out std_logic_vector 7 DOWNTO ; END COPONENT; SIGNAL RST : std_logic; SIGNAL OEN : std_logic; SIGNAL A_IN : std_logic_vector 5 DOWNTO ; SIGNAL B_IN : std_logic_vector DOWNTO ; SIGNAL ACCCLK : std_logic; SIGNAL D_OUT : std_logic_vector 7 DOWNTO ; BEGIN UUT : fir_top PORT AP 57

61 ; RST => RST, OEN => OEN, A_IN => A_IN, B_IN => B_IN, ACCCLK => ACCCLK, D_OUT => D_OUT PROCESS VARIABLE TX_OUT : LINE; VARIABLE TX_ERROR : INTEGER := ; code ERROR; PROCEDURE CHECK_D_OUT next_d_out : std_logic_vector 7 DOWNTO ; TX_TIE : INTEGER IS VARIABLE TX_STR : String to 5; VARIABLE TX_LOC : LINE; BEGIN -- If copiler error "/=" is abiguous occurs in te next line of -- cange copiler settings to use explicit declarations onl IF D_OUT /= next_d_out THEN writetx_loc,string'"error at tie="; writetx_loc, TX_TIE; writetx_loc,string'"ns D_OUT="; writetx_loc, D_OUT; writetx_loc, string'", Expected = "; writetx_loc, next_d_out; writetx_loc, string'" "; TX_STRTX_LOC.all'range := TX_LOC.all; writelineresults, TX_LOC; DeallocateTX_LOC; ASSERT FALSE REPORT TX_STR SEVERITY TX_ERROR := TX_ERROR + ; 58

62 END; END IF; BEGIN ACCCLK <= transport ''; RST <= transport ''; OEN <= transport ''; A_IN <= transport std_logic_vector'""; -- B_IN <= transport std_logic_vector'""; -- WAIT FOR ns; -- Tie= ns ACCCLK <= transport ''; WAIT FOR ns; -- Tie= ns WAIT FOR 9 ns; -- Tie= ns ACCCLK <= transport ''; WAIT FOR 9 ns; -- Tie= ns RST <= transport ''; A_IN <= transport std_logic_vector'""; --85 B_IN <= transport std_logic_vector'""; --7FF WAIT FOR ns; -- Tie= ns ACCCLK <= transport ''; WAIT FOR ns; -- Tie= ns WAIT FOR 9 ns; -- Tie=3 ns ACCCLK <= transport ''; WAIT FOR 9 ns; -- Tie=4 ns WAIT FOR ns; -- Tie=4 ns ACCCLK <= transport ''; WAIT FOR ns; -- Tie=4 ns WAIT FOR 9 ns; -- Tie=5 ns ACCCLK <= transport ''; WAIT FOR 9 ns; -- Tie=6 ns OEN <= transport ''; WAIT FOR ns; -- Tie=6 ns ACCCLK <= transport ''; WAIT FOR ns; -- Tie=6 ns WAIT FOR 9 ns; -- Tie=7 ns 59

63 ACCCLK <= transport ''; WAIT FOR 9 ns; -- Tie=8 ns RST <= transport ''; OEN <= transport ''; WAIT FOR ns; -- Tie=8 ns ACCCLK <= transport ''; WAIT FOR ns; -- Tie=8 ns WAIT FOR 9 ns; -- Tie=9 ns ACCCLK <= transport ''; WAIT FOR 9 ns; -- Tie= ns WAIT FOR ns; -- Tie= ns ACCCLK <= transport ''; WAIT FOR ns; -- Tie= ns WAIT FOR 9 ns; -- Tie= ns ACCCLK <= transport ''; WAIT FOR 9 ns; -- Tie= ns WAIT FOR ns; -- Tie= ns ACCCLK <= transport ''; WAIT FOR ns; -- Tie= ns WAIT FOR 9 ns; -- Tie=3 ns ACCCLK <= transport ''; WAIT FOR 9 ns; -- Tie=4 ns RST <= transport ''; A_IN <= transport std_logic_vector'""; --85 B_IN <= transport std_logic_vector'""; -- WAIT FOR ns; -- Tie=4 ns ACCCLK <= transport ''; WAIT FOR ns; -- Tie=4 ns WAIT FOR 9 ns; -- Tie=5 ns ACCCLK <= transport ''; WAIT FOR 9 ns; -- Tie=6 ns A_IN <= transport std_logic_vector'""; --B B_IN <= transport std_logic_vector'""; --7FF WAIT FOR ns; -- Tie=6 ns ACCCLK <= transport ''; WAIT FOR ns; -- Tie=6 ns 6

64 detected. " WAIT FOR 9 ns; -- Tie=7 ns ACCCLK <= transport ''; WAIT FOR 9 ns; -- Tie=8 ns WAIT FOR ns; -- Tie=8 ns ACCCLK <= transport ''; WAIT FOR ns; -- Tie=8 ns WAIT FOR 9 ns; -- Tie=9 ns ACCCLK <= transport ''; WAIT FOR 9 ns; -- Tie= ns OEN <= transport ''; WAIT FOR ns; -- Tie= ns ACCCLK <= transport ''; WAIT FOR ns; -- Tie= ns WAIT FOR 9 ns; -- Tie= ns ACCCLK <= transport ''; WAIT FOR 9 ns; -- Tie= ns RST <= transport ''; OEN <= transport ''; WAIT FOR ns; -- Tie= ns ACCCLK <= transport ''; WAIT FOR ns; -- Tie= ns WAIT FOR 9 ns; -- Tie=3 ns ACCCLK <= transport ''; WAIT FOR 9 ns; -- Tie=4 ns WAIT FOR ns; -- Tie=4 ns ACCCLK <= transport ''; WAIT FOR ns; -- Tie=4 ns IF TX_ERROR = THEN writetx_out,string'"no errors or warnings"; writelineresults, TX_OUT; ASSERT FALSE REPORT "Siulation successful not a failure. No probles SEVERITY FAILURE; ELSE writetx_out, TX_ERROR; 6

65 writetx_out, string' " errors found in siulation"; writelineresults, TX_OUT; ASSERT FALSE REPORT "Errors found during siulation" SEVERITY FAILURE; END IF; END PROCESS; END testbenc_arc; CONFIGURATION fir_top_cfg OF testbenc IS FOR testbenc_arc END FOR; END fir_top_cfg; 6

66 IIR VHDL librar ieee; use ieee.std_logic_64.all; use ieee.std_logic_signed.all; entit ux is port ux_a: in std_logic_vector downto ; ux_b: in std_logic_vector7 downto ; ux_out: out std_logic_vector downto ; s: in std_logic; end ux; arcitecture struct of ux is signal ux_a_tp: std_logic_vector7 downto ; signal ux_b_tp: std_logic_vector7 downto ; signal ux_tp_out: std_logic_vector7 downto ; begin gen_ux_a_tp : processux_a begin for i in downto loop ux_a_tpi+6 <= ux_ai; end loop; end process gen_ux_a_tp; gen_ux_b_tp: processux_b begin ux_b_tp<=ux_b; end process gen_ux_b_tp; processux_a_tp,ux_b_tp,s begin ifs=''ten 63

67 ux_tp_out<=ux_a_tp; else ux_tp_out<=ux_b_tp; end if; end process; gen_ux_out:processux_tp_out begin for i in downto loop ux_outi <= ux_tp_outi+6; end loop; end process; end struct; librar IEEE; use IEEE.std_logic_64.all; use IEEE.std_logic_arit.all; entit ultiplier_6x is Port RST : In std_logic; -- reset ACCCLK : In std_logic; -- 9Fs A_IN : In std_logic_vector 5 downto ; B_IN : In std_logic_vector downto ; UL_OUT : Out std_logic_vector 7 downto ; end ultiplier_6x; arcitecture STRUCT of ultiplier_6x is signal coeff_in : signed 5 downto ; signal data_in : signed downto ; signal ul_tp : signed 7 downto ; begin -- arcitecture ultiplier_6x 64

68 gen_coeff_in : process RST, ACCCLK begin -- process gen_coeff_tp ifrst = '' ten coeff_in <= ""; elsif ACCCLK'event and ACCCLK = '' ten for i in 5 downto loop coeff_ini <= A_INi; end loop; end if; end process gen_coeff_in; gen_data_in : process RST, ACCCLK begin -- process gen_data_tp ifrst = '' ten data_in <= ""; elsif ACCCLK'event and ACCCLK = '' ten for i in downto loop data_ini <= B_INi; end loop; end if; end process gen_data_in; ul_tp <= coeff_in * data_in; gen_ul_out : process RST, ACCCLK begin -- process gen_ultiplied_out ifrst = '' ten UL_OUT <= ""; elsif ACCCLK'event and ACCCLK = '' ten for i in 7 downto loop UL_OUTi <= ul_tpi; 65

69 end loop; end if; end process gen_ul_out; end; librar IEEE; use IEEE.std_logic_64.all; use IEEE.std_logic_signed.all; entit accuulator is Port RST : In std_logic; -- reset ACCCLK : In std_logic; -- 9Fs C_IN : In std_logic_vector7 downto ; ACC_OUT : Out std_logic_vector7 downto ; end accuulator; arcitecture STRUCTURE of accuulator is signal B_tp,C_tp : std_logic_vector 7 downto ; begin processc_in,b_tp variable A_tp:std_logic_vector7 downto ; begin A_tp7 downto :=C_IN; C_tp<=A_tp + B_tp; end process; processaccclk begin ifaccclk=''andaccclk'eventten ifrst=''ten B_tp<=oters=>''; 66

70 else B_tp<=C_tp; end if; end if; end process; processc_tp begin ACC_OUT<=C_tp; end process; end; librar IEEE; use IEEE.std_logic_64.all; entit DFF is port D : in std_logic_vector7 downto ; D_OUT : out std_logic_vector7 downto ; RST : in std_logic; OEN:in std_logic; ACCCLK : in std_logic; end DFF; arcitecture struct of DFF is signal Q:std_logic_vector7 downto ; begin processaccclk begin ifaccclk=''andaccclk'eventten ifrst=''ten Q<=oters=>''; else Q<=D; end if; end if; 67

71 end process; processq,oen begin case OEN is wen ''=> D_OUT<=oters=>'Z'; wen oters => D_OUT<=Q6 downto &''; end case; end process; end struct; librar ieee; use ieee.std_logic_64.all; use ieee.std_logic_signed.all; entit ux is port ux_in_a:in std_logic_vector7 downto ; s:in std_logic; ux_out:out std_logic_vector7 downto ; end ux; arcitecture arc of ux is signal ux_tp_a: std_logic_vector7 downto ; signal ux_tp_b: std_logic_vector7 downto ; signal ux_out_tp: std_logic_vector7 downto ; begin gen_ux_tp_a:processux_in_a begin ux_tp_a<=ux_in_a; end process gen_ux_tp_a; ux_tp_b<=ux_out_tp; 68

72 process ux_tp_a,ux_tp_b,s begin ifs=''ten ux_out_tp<=ux_tp_a; else ux_out_tp<=ux_tp_b; end if; ux_out<=ux_out_tp; end process; end arc; librar ieee; use ieee.std_logic_64.all; use ieee.std_logic_signed.all; entit ux3 is port ux_in_c:in std_logic_vector7 downto ; s3:in std_logic; ux3_out:out std_logic_vector7 downto ; end ux3; arcitecture arc of ux3 is signal ux_tp_c: std_logic_vector7 downto ; signal ux_tp_d: std_logic_vector7 downto ; signal ux3_out_tp: std_logic_vector7 downto ; begin gen_ux_tp_c:processux_in_c begin ux_tp_c<=ux_in_c; end process gen_ux_tp_c; ux_tp_d<=ux3_out_tp; 69

73 process ux_tp_c,ux_tp_d,s3 begin ifs3=''ten ux3_out_tp<=ux_tp_c; else ux3_out_tp<=ux_tp_d; end if; ux3_out<=ux3_out_tp; end process; end arc; librar IEEE; use IEEE.std_logic_64.all; use IEEE.std_logic_arit.all; entit iir_top is Port s: in std_logic; s: in std_logic; s3: in std_logic; RST : In std_logic; OEN : In std_logic; A_IN: In std_logic_vector5 downto ; G_IN : In std_logic_vector downto ; ACCCLK : In std_logic; Fs aster cloc DATA_OUT : Out std_logic_vector7 downto ; end iir_top; arcitecture STRUCTURE of iir_top is signal ul_signal : std_logic_vector7 downto ; signal acc_signal : std_logic_vector7 downto ; signal ux_signal : std_logic_vector downto ; signal ux_signal : std_logic_vector7 downto ; 7

74 signal ux3_signal : std_logic_vector7 downto ; signal D_signal : std_logic_vector7 downto ; coponent ux port ux_a: in std_logic_vector downto ; ux_b: in std_logic_vector7 downto ; ux_out: out std_logic_vector downto ; s: in std_logic; end coponent; coponent ultiplier_6x Port RST : In std_logic; ACCCLK : In std_logic; A_IN : In std_logic_vector 5 downto ; B_IN : In std_logic_vector downto ; UL_OUT : Out std_logic_vector 7 downto ; end coponent; coponent accuulator Port RST : In std_logic; ACCCLK : In std_logic; C_IN : In std_logic_vector7 downto ; ACC_OUT : Out std_logic_vector7 downto ; end coponent; coponent DFF Port D : in std_logic_vector7 downto ; D_OUT : out std_logic_vector7 downto ; RST : in std_logic; OEN : in std_logic; ACCCLK : in std_logic; end coponent; 7

75 coponent ux port ux_in_a:in std_logic_vector7 downto ; s:in std_logic; ux_out:out std_logic_vector7 downto ; end coponent; coponent ux3 port ux_in_c:in std_logic_vector7 downto ; s3:in std_logic; ux3_out:out std_logic_vector7 downto ; end coponent; begin -- arcitecture iir_top ux_ : ux port ap ux_a => G_IN, ux_b =>ux3_signal, s => s, ux_out =>ux_signal; ultiplier_6x_: ultiplier_6x port ap RST => RST, ACCCLK => ACCCLK, A_IN => A_IN, B_IN => ux_signal, UL_OUT => ul_signal; accuulator_: accuulator port ap RST => RST, ACCCLK => ACCCLK, C_IN => ul_signal, ACC_OUT => acc_signal; 7

76 DFF_: DFF port ap D => acc_signal, D_OUT => D_signal, RST => RST, OEN => OEN, ACCCLK => ACCCLK; ux_: ux port ap ux_in_a=>d_signal, s=>s, ux_out=>ux_signal; ux_3 : ux3 port ap ux_in_c=>ux_signal, s3=>s3, ux3_out=>ux3_signal; gen_data_out: processd_signal begin DATA_OUT<=D_signal; end process; end; -- arcitecture iir_top IIR VHDL LIBRARY IEEE; USE IEEE.std_logic_64.all; USE IEEE.std_logic_arit.all; LIBRARY ieee; USE IEEE.STD_LOGIC_TEXTIO.ALL; USE STD.TEXTIO.ALL; ENTITY testbenc IS 73

77 END testbenc; ARCHITECTURE testbenc_arc OF testbenc IS -- If ou get a copiler error on te following line, -- fro te enu do Options->Configuration select VHDL 93 FILE RESULTS: TEXT IS OUT "results.txt"; COPONENT iir_top PORT s : in std_logic; s : in std_logic; s3 : in std_logic; RST : In std_logic; OEN : In std_logic; A_IN : In std_logic_vector 5 DOWNTO ; G_IN : In std_logic_vector DOWNTO ; ACCCLK : In std_logic; DATA_OUT : Out std_logic_vector 7 DOWNTO ; END COPONENT; SIGNAL s : std_logic; SIGNAL s : std_logic; SIGNAL s3 : std_logic; SIGNAL RST : std_logic; SIGNAL OEN : std_logic; SIGNAL A_IN : std_logic_vector 5 DOWNTO ; SIGNAL G_IN : std_logic_vector DOWNTO ; SIGNAL ACCCLK : std_logic; SIGNAL DATA_OUT : std_logic_vector 7 DOWNTO ; BEGIN UUT : iir_top PORT AP s => s, s => s, s3 => s3, 74

78 ; RST => RST, OEN => OEN, A_IN => A_IN, G_IN => G_IN, ACCCLK => ACCCLK, DATA_OUT => DATA_OUT PROCESS VARIABLE TX_OUT : LINE; VARIABLE TX_ERROR : INTEGER := ; code ERROR; PROCEDURE CHECK_DATA_OUT next_data_out : std_logic_vector 7 DOWNTO ; TX_TIE : INTEGER IS VARIABLE TX_STR : String to 5; VARIABLE TX_LOC : LINE; BEGIN -- If copiler error "/=" is abiguous occurs in te next line of -- cange copiler settings to use explicit declarations onl IF DATA_OUT /= next_data_out THEN writetx_loc,string'"error at tie="; writetx_loc, TX_TIE; writetx_loc,string'"ns DATA_OUT="; writetx_loc, DATA_OUT; writetx_loc, string'", Expected = "; writetx_loc, next_data_out; writetx_loc, string'" "; TX_STRTX_LOC.all'range := TX_LOC.all; writelineresults, TX_LOC; DeallocateTX_LOC; ASSERT FALSE REPORT TX_STR SEVERITY TX_ERROR := TX_ERROR + ; 75

79 END; END IF; BEGIN ACCCLK <= transport ''; s <= transport ''; s <= transport ''; s3 <= transport ''; RST <= transport ''; OEN <= transport ''; A_IN <= transport std_logic_vector'""; -- G_IN <= transport std_logic_vector'""; -- WAIT FOR ns; -- Tie= ns ACCCLK <= transport ''; WAIT FOR ns; -- Tie= ns WAIT FOR 9 ns; -- Tie= ns ACCCLK <= transport ''; WAIT FOR 9 ns; -- Tie= ns RST <= transport ''; A_IN <= transport std_logic_vector'""; --9 G_IN <= transport std_logic_vector'""; --7FF WAIT FOR ns; -- Tie= ns ACCCLK <= transport ''; WAIT FOR ns; -- Tie= ns WAIT FOR 9 ns; -- Tie=3 ns ACCCLK <= transport ''; WAIT FOR 9 ns; -- Tie=4 ns RST <= transport ''; WAIT FOR ns; -- Tie=4 ns ACCCLK <= transport ''; WAIT FOR ns; -- Tie=4 ns WAIT FOR 9 ns; -- Tie=5 ns ACCCLK <= transport ''; WAIT FOR 9 ns; -- Tie=6 ns s <= transport ''; 76

80 RST <= transport ''; OEN <= transport ''; WAIT FOR ns; -- Tie=6 ns ACCCLK <= transport ''; WAIT FOR ns; -- Tie=6 ns WAIT FOR 9 ns; -- Tie=7 ns ACCCLK <= transport ''; WAIT FOR 9 ns; -- Tie=8 ns s <= transport ''; s3 <= transport ''; RST <= transport ''; OEN <= transport ''; WAIT FOR ns; -- Tie=8 ns ACCCLK <= transport ''; WAIT FOR ns; -- Tie=8 ns WAIT FOR 9 ns; -- Tie=9 ns ACCCLK <= transport ''; WAIT FOR 9 ns; -- Tie= ns s <= transport ''; s3 <= transport ''; RST <= transport ''; A_IN <= transport std_logic_vector'""; --39D4 WAIT FOR ns; -- Tie= ns ACCCLK <= transport ''; WAIT FOR ns; -- Tie= ns WAIT FOR 9 ns; -- Tie= ns ACCCLK <= transport ''; WAIT FOR 9 ns; -- Tie= ns s <= transport ''; A_IN <= transport std_logic_vector'""; --35 G_IN <= transport std_logic_vector'""; --7FF WAIT FOR ns; -- Tie= ns ACCCLK <= transport ''; WAIT FOR ns; -- Tie= ns WAIT FOR 9 ns; -- Tie=3 ns ACCCLK <= transport ''; 77

81 WAIT FOR 9 ns; -- Tie=4 ns A_IN <= transport std_logic_vector'""; --9 G_IN <= transport std_logic_vector'""; -- WAIT FOR ns; -- Tie=4 ns ACCCLK <= transport ''; WAIT FOR ns; -- Tie=4 ns WAIT FOR 9 ns; -- Tie=5 ns ACCCLK <= transport ''; WAIT FOR 9 ns; -- Tie=6 ns WAIT FOR ns; -- Tie=6 ns ACCCLK <= transport ''; WAIT FOR ns; -- Tie=6 ns WAIT FOR 9 ns; -- Tie=7 ns ACCCLK <= transport ''; WAIT FOR 9 ns; -- Tie=8 ns s <= transport ''; OEN <= transport ''; WAIT FOR ns; -- Tie=8 ns ACCCLK <= transport ''; WAIT FOR ns; -- Tie=8 ns WAIT FOR 9 ns; -- Tie=9 ns ACCCLK <= transport ''; WAIT FOR 9 ns; -- Tie= ns s <= transport ''; RST <= transport ''; OEN <= transport ''; WAIT FOR ns; -- Tie= ns ACCCLK <= transport ''; WAIT FOR ns; -- Tie= ns WAIT FOR 9 ns; -- Tie= ns ACCCLK <= transport ''; WAIT FOR 9 ns; -- Tie= ns s <= transport ''; RST <= transport ''; A_IN <= transport std_logic_vector'""; --3FE WAIT FOR ns; -- Tie= ns 78

82 ACCCLK <= transport ''; WAIT FOR ns; -- Tie= ns WAIT FOR 9 ns; -- Tie=3 ns ACCCLK <= transport ''; WAIT FOR 9 ns; -- Tie=4 ns s <= transport ''; s3 <= transport ''; A_IN <= transport std_logic_vector'""; -- WAIT FOR ns; -- Tie=4 ns ACCCLK <= transport ''; WAIT FOR ns; -- Tie=4 ns WAIT FOR 9 ns; -- Tie=5 ns ACCCLK <= transport ''; WAIT FOR 9 ns; -- Tie=6 ns s <= transport ''; s3 <= transport ''; A_IN <= transport std_logic_vector'""; --39D4 WAIT FOR ns; -- Tie=6 ns ACCCLK <= transport ''; WAIT FOR ns; -- Tie=6 ns WAIT FOR 9 ns; -- Tie=7 ns ACCCLK <= transport ''; WAIT FOR 9 ns; -- Tie=8 ns s <= transport ''; A_IN <= transport std_logic_vector'""; --9 G_IN <= transport std_logic_vector'""; --7FF WAIT FOR ns; -- Tie=8 ns ACCCLK <= transport ''; WAIT FOR ns; -- Tie=8 ns WAIT FOR 9 ns; -- Tie=9 ns ACCCLK <= transport ''; WAIT FOR 9 ns; -- Tie=3 ns A_IN <= transport std_logic_vector'""; --35 G_IN <= transport std_logic_vector'""; -- WAIT FOR ns; -- Tie=3 ns ACCCLK <= transport ''; 79

83 WAIT FOR ns; -- Tie=3 ns WAIT FOR 9 ns; -- Tie=3 ns ACCCLK <= transport ''; WAIT FOR 9 ns; -- Tie=3 ns A_IN <= transport std_logic_vector'""; --9 WAIT FOR ns; -- Tie=3 ns ACCCLK <= transport ''; WAIT FOR ns; -- Tie=3 ns WAIT FOR 9 ns; -- Tie=33 ns ACCCLK <= transport ''; WAIT FOR 9 ns; -- Tie=34 ns WAIT FOR ns; -- Tie=34 ns ACCCLK <= transport ''; WAIT FOR ns; -- Tie=34 ns WAIT FOR 9 ns; -- Tie=35 ns ACCCLK <= transport ''; WAIT FOR 9 ns; -- Tie=36 ns s <= transport ''; OEN <= transport ''; WAIT FOR ns; -- Tie=36 ns ACCCLK <= transport ''; WAIT FOR ns; -- Tie=36 ns WAIT FOR 9 ns; -- Tie=37 ns ACCCLK <= transport ''; WAIT FOR 9 ns; -- Tie=38 ns s <= transport ''; RST <= transport ''; OEN <= transport ''; WAIT FOR ns; -- Tie=38 ns ACCCLK <= transport ''; WAIT FOR ns; -- Tie=38 ns WAIT FOR 9 ns; -- Tie=39 ns ACCCLK <= transport ''; WAIT FOR 9 ns; -- Tie=4 ns s <= transport ''; RST <= transport ''; 8

84 A_IN <= transport std_logic_vector'""; --3FE WAIT FOR ns; -- Tie=4 ns ACCCLK <= transport ''; WAIT FOR ns; -- Tie=4 ns IF TX_ERROR = THEN writetx_out,string'"no errors or warnings"; writelineresults, TX_OUT; ASSERT FALSE REPORT "Siulation successful not a failure. No probles detected. " SEVERITY FAILURE; ELSE writetx_out, TX_ERROR; writetx_out, string' " errors found in siulation"; writelineresults, TX_OUT; ASSERT FALSE REPORT "Errors found during siulation" SEVERITY FAILURE; END IF; END PROCESS; END testbenc_arc; CONFIGURATION iir_top_cfg OF testbenc IS FOR testbenc_arc END FOR; END iir_top_cfg; 8

スライド 1

スライド 1 1 1. 2 2. 3 isplever 4 5 6 7 8 9 VHDL 10 VHDL 4 Decode cnt = "1010" High Low DOUT CLK 25MHz 50MHz clk_inst Cnt[3:0] RST 2 4 1010 11 library ieee; library xp; use xp.components.all; use ieee.std_logic_1164.all;