IPSJ SIG Technical Report Vol.2016-HPC-153 No /3/1 FPGA 1,a) FPGA(Field Programmable Gate Array) FPGA HPC OpenCL FPGA HPC FPGA FEM CG Open

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1 FPGA 1,a) FPGA(Field Programmable Gate Array) FPGA HPC OpenCL FPGA HPC FPGA FEM CG OpenCL FPGA 1. CPU(Central Processing Unit) GPU(Graphics Processing Unit) HPC FPGA (Field Programmable Gate Array) FPGA FPGA FPGA Catapult[1] HPC FPGA [3], [4] FPGA FPGA Verilog FPGA FPGA OpenCL[2] FPGA Verilog OpenCL HPC FPGA [5], [6] CPU GPU [7], [8] FPGA [9], [10] HPC FPGA OpenCL FPGA 2 FPGA 3 OpenCL FPGA 4 1 a) ohshima@cc.u-tokyo.ac.jp c 2016 Information Processing Society of Japan 1

1 FPGA FPGA: Altera Stratix V GS D5 (5SGSMD5K2F40C2) #Logic units (ALMs) 172,600 #RAM blocks (M20K) 2,014 #DSP blocks 1,590 (27 27) : Bittware S5-PCIe-HQ GSMD5 DDR DDR PCIe I/F (4 + 4) MB 25.

1 FPGA OpenCL SDK FPGA Altera Stratix V GS D5 Stratix V Altera FPGA 1 FPGA 1 Adaptive Logic Module (ALM) 172,600 4 2 6 Look Up Table (LUT) 2 FPGA 2,014 20Kbit RAM (M20K) 640bit Memory Logic Array

2 1 FPGA FPGA: Altera Stratix V GS D5 (5SGSMD5K2F40C2) #Logic units (ALMs) 172,600 #RAM blocks (M20K) 2,014 #DSP blocks 1,590 (27 27) : Bittware S5-PCIe-HQ GSMD5 DDR DDR PCIe I/F (4 + 4) MB 25.6 GB/sec Gen3 x8 (OpenCL Gen2 x8 ) Altera Quartus II FPGA 2.1 FPGA OpenCL SDK FPGA Altera Stratix V GS D5 Stratix V Altera FPGA 1 FPGA 1 Adaptive Logic Module (ALM) 172, Look Up Table (LUT) 2 FPGA 2,014 20Kbit RAM (M20K) 640bit Memory Logic Array Block (MLAB) 8,630 Digital Signal Processor (DSP) 27 1,590 DSP Stratix V ALM RAM *1 [11][12] FPGA Bittware PCI Express S5-PCIe-HQ (s5phq d5) ( 1) FPGA Verilog HDL VHDL C Fotran FPGA HPC FPGA *1 Arria 10, Stratix 10 DSP 1 Bittware S5-PCIe-HQ (Bittware QDR II+ ) OpenCL FPGA HPC Altera FPGA Stratix V OpenCL Verilog OpenCL FPGA Altera Stratix V CPU FPGA ARM IP FPGA (Xilinx Zynq, Altera Arria SoC ) OpenCL FPGA CPU PCI Express OpenCL FPGA Altera Stratix V FPGA PCI Express GPU I/O PCI Express *2 PCI Express FPGA OpenCL FPGA PCI Express FPGA (Partial reconfiguration) FPGA PCI Express *2 Intel Altera QPI c 2016 Information Processing Society of Japan 2

3 DDR PCI Express OpenCL OpenCL Verilog HDL IP 1 Intel Xeon E5 (Haswell ) 2 FPGA FPGA --report -c FPGA & 2.2 OpenCL FPGA OpenCL Khronos GPU FPGA DSP(Digital Signal Processor) HPC AMD GPU CPU Xeon Phi NVIDIA GPU OpenCL C/++ (API ) GPU OpenCL CUDA[13] OpenCL 2.0 OpenCL CPU OpenMP 2 FPGA OpenCL GPU CUDA OpenCL FPGA FPGA Altera Altera OpenCL SDK[14] FPGA SDK Stratix V Altera OpenCL Altera 2013 SDK OpenCL ( ) FPGA ( ) GPU API FPGA (FPGA ) 2 OpenCL FPGA FPGA FPGA ( ) kernel global CUDA CUDA Driver API OpenCL CUDA FPGA FPGA OpenCL FPGA GPU OpenCL GPU c 2016 Information Processing Society of Japan 3

4 FPGA GPU OpenCL FPGA GPU 2.3 Altera FPGA Altera [15] [16] (SIMD ) FPGA OpenCL global DDR local RAM ( local ) (SIMD, ) FPGA GPU OpenCL clenqueuendrangekernel FPGA FPGA ID API ID CUDA GPU GPU FPGA OpenCL FPGA attribute num_simd_work_items(4) SIMD 4 num_compute_units(4) OpenCL for while Altera OpenCL Compiler (AOC) 3 for FPGA 1 0 (single stream) for c 2016 Information Processing Society of Japan 4

5 ======================================================================================================================== *** Optimization Report *** ======================================================================================================================== Kernel: cg File:Ln ======================================================================================================================== Loop for.body [1]:30 Pipelined execution inferred Loop for.body5 [1]:37 Pipelined execution inferred. Successive iterations launched every 2 cycles due to: Pipeline structure Loop for.body18 [1]:39 Pipelined execution inferred. Successive iterations launched every 8 cycles due to: Data dependency on variable Largest Critical Path Contributor: 96%: Fadd Operation [1]: Loop for.body37 [1]:45 Pipelined execution inferred. Successive iterations launched every 8 cycles due to: Data dependency on variable BNorm2 [1]:46 Largest Critical Path Contributor: 96%: Fadd Operation [1]:46 3 AOC c 2016 Information Processing Society of Japan 5

6 2.4.1 CPU FPGA OpenCL FPGA [5], [6] Rodinia ppopen-hpc OpenCL FPGA OpenCL FPGA FPGA FPGA OpenCL 2 CG(Conjugate Gradient) C FEM(Finite Element Method) CG (float ) 4 (CG ) 3 7 OpenMP FPGA CPU-FPGA Intel Xeon E5 2 FPGA(Stratix V) 1 {r0} = {b} - [A]{xini} 2 loop 3 solve {z} = [Minv]{r} 4 RHO = {r}{z} 5 if ITER=1 {p} = {z} 6 else BETA = RHO / RHO1 7 {q} = [A]{p} 8 ALPHA = RHO / {p}{q} 9 {x} = {x} + ALPHA * {p} 10 {r} = {r} - ALPHA * {q} 11 endloop 4 CG OpenCL FPGA 3.2 FPGA OpenCL CG kernel CPU-FPGA global OpenCL API (clenqueuereadbuffer, clenqueuewritebuffer) CPU-FPGA global clenqueuendrangekernel API 1 FPGA (FPGA ) -g -W -v --board s5phq_d5 -g -W warning -v --board s5phq_d5 FPGA CPU -O2 OpenCL CPU const restrict const restrict const restrict c 2016 Information Processing Society of Japan 6

5 / 6 local 2 local (MHz) 247.46 269.32 262.

CPU gcc4.4.7 -O2 CPU OpenCL FPGA restrict warning: declaring kernel argument with no restrict may lead to low kernel performance 2 local 1 3.

7 5 / 6 local 2 local (MHz) Logic utilization 60% 68% 39% Dedicated logic registers 31% 34% 18% Memory blocks 61% 71% 34% DSP blocks 2% 2% 2% 5 ( -1 ) 1000 E v2 CPU gcc O2 CPU OpenCL FPGA restrict warning: declaring kernel argument with no restrict may lead to low kernel performance 2 local FPGA DDR global DDR global local global local local OpenCL FPGA local 2 DSP local 3.4 (SIMD ) SIMD FPGA attribute local SIMD SIMD num_simd_work_items reqd_work_group_size attribute CG SIMD c 2016 Information Processing Society of Japan 7

3 (MHz) 269.32 285.3 Logic utilization 68% 63% Dedicated logic registers 34% 31% Memory blocks 71% 68% DSP blocks 2% 2% (msec) 139.190 106.

8 3 (MHz) Logic utilization 68% 63% Dedicated logic registers 34% 31% Memory blocks 71% 68% DSP blocks 2% 2% (msec) SIMD ( ) SIMD Compiler Warning: Kernel Vectorization: branching is thread ID dependent... cannot vectorize. Compiler Warning: Kernel cg : limiting to 2 concurrent work-groups because threads might reach barrier out-of-order ( ) SIMD SIMD num_compute_units attribute 3 SIMD FPGA 2 FPGA SIMD 4. SIMD SIMD FPGA OpenCL CG Compiler Warning: Kernel cg : limiting to 2 concurrent OpenCL work-groups because threads might reach barrier out-of-order. OpenCL FPGA GPU CRS(Compressed Row Storage) SIMD Compiler Warning: Kernel Vectorization: branching is thread ID dependent... cannot vectorize. ID FPGA c 2016 Information Processing Society of Japan 8

9 JST CREST :ppopen-hpc JSPS 15K00166 Quartus II Altera University Program [1] Putnam, A. and Caulfield, A.M. and Chung, E.S. and Chiou, D. and Constantinides, K. and Demme, J. and Esmaeilzadeh, H. and Fowers, J. and Gopal, G.P. and Gray, J. and Haselman, M. and Hauck, S. and Heil, S. and Hormati, A. and Kim, J.-Y. and Lanka, S. and Larus, J. and Peterson, E. and Pope, S. and Smith, A. and Thong, J. and Xiao, P.Y. and Burger, D., A reconfigurable fabric for accelerating large-scale datacenter services, 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA), pp.13-24, [2] OpenCL - The open standard for parallel programming of heterogeneous systems opencl/ [3],,, Alexander Vazhenin, Stanislav Sedukhin: FPGA, (2015-HPC-149), [4],, :, (2015-HPC-151), [5], Hamid Reza Zohouri,, : OpenCL FPGA, (2015-HPC-150), [6] Hamid Reza Zohouri, Naoya Maruyama, Aaron Smith, Motohiko Matsuda, and SatoshiMatsuoka, Optimizing the Rodinia Benchmark for FPGAs (Unrefereed Workshop Manuscript), (2015-HPC- 152), [7] K. Nakajima and M. Satoh and T. Furumura and H. Okuda and T. Iwashita and H. Sakaguchi and T. Katagiri and M. Matsumoto and S. Ohshima and H. Jitsumoto and T. Arakawa and F. Mori and T. Kitayama and A. Ida and M. Y. Matsuo and K. Fujisawa and et al., ppopen-hpc: Open Source Infrastructure for Development and Execution of Large-Scale Scientific Applications on Post-Peta-Scale Supercomputers with Automatic Tuning (AT), Optimization in the Real World, pp.15 35, DOI / , [8] ppopen-hpc Open Source Infrastructure for Development and Execution of Large-Scale Scientific Applications on Post-Peta-Scale Supercomputers with Automatic Tuning (AT) ac.jp/ppopenhpc/ [9] Tightly Coupled Accelerators GPU Vol.6, No.4, pp.14-25, [10] Yuetsu Kodama, Toshihiro Hanawa, Taisuke Boku and Mitsuhisa Sato, PEACH2: FPGA based PCIe network device for Tightly Coupled Accelerators, International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2014), pp. 3-8, Jun [11] Altera Corporation, Floating-Point IP Cores User Guide, UG-01058, [12] Altera, Stratix V Device Handbook, https: // stratix-v/stx5_core.pdf [13] CUDA Dynamic Parallelism, com/cuda/cuda-c-programming-guide/index.html# cuda-dynamic-parallelism [14] Altera Corporation, SDK for OpenCL - design-software/embedded-software-developers/ opencl/overview.html [15] Altera Corporation, Altera SDK for OpenCL Programming Guide 15.1, UG-OCL002, [16] Altera Corporation, Altera SDK for OpenCL Best Practice Guide 15.1, UG-OCL003, c 2016 Information Processing Society of Japan 9

IPSJ SIG Technical Report Vol.2016-HPC-155 No /8/10 FPGA 1,a) FPGA(Field Programmable Gate Array) FPGA OpenCL FPGA FPGA OpenCL FPGA 1. CP

IPSJ SIG Technical Report Vol.2016-HPC-155 No /8/10 FPGA 1,a) FPGA(Field Programmable Gate Array) FPGA OpenCL FPGA FPGA OpenCL FPGA 1. CP FPGA 1,a) 1 1 1 FPGA(Field Programmable Gate Array) FPGA OpenCL FPGA FPGA OpenCL FPGA 1. CPU GPGPU HPC FPGA (Field Programmable Gate Array) FPGA FPGA FPGA Catapult[1] HPC FPGA [3], [4] FPGA Verilog HDL