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1 VHDL

2

3 VHDL BCD REG_B STATE VHDL 5 VHDL

4 1 CPU Hardware Description Language : HDL VHDL VHSIC HDL VHDL 4 3

5 2 complement 1 s complement2 s complem MSBMost Significant 1 Bit MSB LSB Least Significant 1 Bit 2 LSB MSB

6 LSB MSB = = = = 0 ( carry) A B SUM CY_OUT A B SUM CY_OUT

7 B A OUT CY B A SUM = = _ 2.2(a) (b) 2.1(a) (b) carry carry carry carry = + + = + + = + + = + + = + + = + + = + + = + +

8 8 A B CY_IN SUM CY_OUT A B CY_IN SUM CY_OUT SUM = A B CY _ IN CY _ OUT = A CY _ IN + B CY _ IN + A B 2.4(a) (b)

9 2.2(a) (b) LSB Cin 0 1 A B

10 = = 1 ( borrow) = = 0 1 borrow 1 4 A B DIF BR_OUT A B DIF BR_OUT

11 B A OUT BR B A DIF = = _ 2.7(a) (b) 2.4(a) (b) borrow borrow borrow borrow = = = = = = = =

12 8 A B BR_INDIF BR_OUT A B BR_IN DIF BR_OUT DIF = A B BR _ IN BR _ OUT = A B + A BR _ IN + B BR _ IN 2.9(a) (b)

13 2.5(a) (b) LSB Bin 0 1 A B

14 0 0 = = = = 1 AND 1.1 LSB MSB X Y Z AND

15 2.84

16

17 A B A B + B ( A B + B) 2 B

18 B B A B B A B B B A B B B A + = + = + = + 2 ) ( ) ( 2.15(a) MSB LSB LSB (b) 2.5

19 2.11(a) (b) LSB

20 3 register

21

22 LOAD EN RESET LOAD 1 LOAD 0 EN JK J K Q 3.4

23

24 MSB 4 2 MSB

25

26 1 1 AND

27

28 K K+1 K LSB 1 K LSB K K

29 2.5.2 L M MSB LSB L+M L+M MSB 1 LSB M LSB 1 1 LSB NAND AND

30 4 8 BCD = > > 2 = REGA 10 BCD DEC_TO_BIN 27 REG_A 10 CNV_MUL 10 BCD cnv_adder 10 INPUT_SEL

31 10 syncro

32 REG_B REG_B STATE 10 DECIMAL OPE HALT 7 LED LED 10 REG_A DECIMAL REG_B OPE LED HALT 10 COUNT ASMD_SEL ASMD_SELECETLED

33 SEL CAL 4.3 D 3 4.3

34

35 VHDL VHDL library ieee; use ieee.std_logic_1164.all; entity ADD is port(a:in std_logic_vector(26 downto 0); B:in std_logic_vector(28 downto 0); S:out std_logic_vector(28 downto 0); START,CLOCK,RESET_B:in std_logic); end ADD; architecture ADD of ADD is signal ADDER4_OUT:std_logic_vector(4 downto 0); signal BIT_A_OUT:std_logic_vector(3 downto 0); signal BIT_B_OUT:std_logic_vector(3 downto 0); signal BIT_REG_OUT:std_logic_vector(28 downto 0); signal CNT16_OUT:std_logic_vector(4 downto 0); signal JK_FF_K_IN:std_logic; signal JK_FF_Q_OUT:std_logic; component ADDER4 port(a,b:in std_logic_vector(3 downto 0); cin:in std_logic; s:out std_logic_vector(4 downto 0)); component BIT_SHIFT_A port(load,clk,en:in std_logic; A_IN:in std_logic_vector(26 downto 0); Q_A:out std_logic_vector(3 downto 0)); 4.5 VHDL1/3

36 component BIT_SHIFT_B port(load,clk,en:in std_logic; B_IN:in std_logic_vector(28 downto 0); Q_B:out std_logic_vector(3 downto 0)); component BIT_REG port(reset,reset_b,clk,en:in std_logic; PIN:in std_logic_vector(4 downto 0); Q:out std_logic_vector(28 downto 0)); component RS_SYJKFF port(reset_b:in std_logic; SET_B:in std_logic :='1'; J,K,CLK:in std_logic; Q,Q_B:out std_logic); component EN_CNT16 port(q:out std_logic_vector(4 downto 0); EN,CLK,CLR_SY,CLR_USY:in std_logic); JK_FF_K_IN <= not CNT16_OUT(4) and not CNT16_OUT(3) and CNT16_OUT(2) and CNT16_OUT(1) and not CNT16_OUT(0); S <= BIT_REG_OUT; U_A:BIT_SHIFT_A port map(start,clock,jk_ff_q_out,a,bit_a_out); U_B:BIT_SHIFT_B port map(start,clock,jk_ff_q_out,b,bit_b_out); U_ADDER4:ADDER4 port map(bit_a_out,bit_b_out,bit_reg_out(28), ADDER4_OUT); U_REG:BIT_REG port map(reset_b,start,clock,jk_ff_q_out, ADDER4_OUT,BIT_REG_OUT); JK_FF:RS_SYJKFF port map(reset_b,open,start,jk_ff_k_in,clock, JK_FF_Q_OUT,open); 4.5 VHDL2/3

37 CNT8:EN_CNT16 map(cnt16_out,jk_ff_q_out,clock,start,reset_b); end ADD; port 4.5 VHDL3/3 library ieee; use ieee.std_logic_1164.all; entity MUL is port(start,clock,reset_b:in std_logic; MD:in std_logic_vector(28 downto 0); MQ:in std_logic_vector(26 downto 0); ANS:out std_logic_vector(55 downto 0)); end MUL; architecture MUL of MUL is signal MQ_S_OUT:std_logic; signal JK_FF_K_IN:std_logic; signal JK_FF_Q_OUT:std_logic; signal MD_Q_OUT:std_logic_vector(28 downto 0); signal ADDER32_A_IN:std_logic_vector(28 downto 0); signal ADDER32_OUT:std_logic_vector(29 downto 0); signal CNT16_OUT:std_logic_vector(4 downto 0); signal ACC_D_IN:std_logic_vector(56 downto 0); signal ACC_Q_OUT:std_logic_vector(56 downto 0); component ADDER32 port(a,b:in std_logic_vector(28 downto 0); cin:in std_logic :='0'; s:out std_logic_vector(28 downto 0); cout:out std_logic); 4.6 VHDL1/3

38 component REG_MD port(load,clk:in std_logic; D:in std_logic_vector(28 downto 0); Q:out std_logic_vector(28 downto 0)); component EN_REG port(reset,en,clr,clk:in std_logic; D:in std_logic_vector(56 downto 0); Q:out std_logic_vector(56 downto 0)); component BIT_SHIFT port(sin:in std_logic :='0'; EN,LOAD,CLK:in std_logic; D:in std_logic_vector(26 downto 0); SOUT:out std_logic); component RS_SYJKFF port(reset_b:in std_logic; SET_B:in std_logic :='1'; J,K,CLK:in std_logic; Q,Q_B:out std_logic); component EN_CNT16 port(en,clk,clr_sy,clr_usy:in std_logic; Q:out std_logic_vector(4 downto 0)); ADDER32_A_IN <= MD_Q_OUT and (MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT& MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT& MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT& MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT); 4.6 VHDL2/3

39 ACC_D_IN <= ADDER32_OUT & ACC_Q_OUT(27 downto 1); JK_FF_K_IN <= CNT16_OUT(4) and CNT16_OUT(3) and not CNT16_OUT(2) and CNT16_OUT(1) and CNT16_OUT(0); ANS <= ACC_Q_OUT(55 downto 0); U_MD:REG_MD port map(start,clock,md,md_q_out); U_ADDER:ADDER32 port map(adder32_a_in,acc_q_out(56 downto 28), open,adder32_out(28 downto 0),ADDER32_OUT(29)); ACC:EN_REG port map(reset_b,jk_ff_q_out,start,clock, ACC_D_IN,ACC_Q_OUT); U_MQ:BIT_SHIFT port map (open,jk_ff_q_out,start,clock, MQ,MQ_S_OUT); JK_FF:RS_SYJKFF port map(reset_b,open,start,jk_ff_k_in,clock, JK_FF_Q_OUT,open); CNT16:EN_CNT16 port map(jk_ff_q_out,clock,start,reset_b, CNT16_OUT); end MUL; 4.6 VHDL3/3 library IEEE; use IEEE.std_logic_1164.all; entity DIV is port(dd:in std_logic_vector(28 downto 0); DQ:in std_logic_vector(26 downto 0); ANS:out std_logic_vector(28 downto 0); ARE:out std_logic_vector(26 downto 0); START,CLOCK,RESET_B:in std_logic ; ER : out std_logic); end DIV; 4.7 VHDL1/5

40 architecture DIV of DIV is signal DQ_E_OUT:std_logic; signal E_JK_FF_J_IN:std_logic; signal STR:std_logic; signal DQ_SEL_IN:std_logic; signal ACC_SEL_IN:std_logic; signal ACC_EN1:std_logic; signal JK_FF_K_IN: std_logic; signal JK_FF_Q_OUT:std_logic; signal ANS_SIN:std_logic; signal ANS_EN:std_logic; signal LAST:std_logic; signal DQ_Q_OUT:std_logic_vector(26 downto 0); signal DQ_SEL_A_IN:std_logic_vector(27 downto 0); signal DQ_SEL_B_IN:std_logic_vector(27 downto 0); signal DQ_SEL_OUT:std_logic_vector(27 downto 0); signal ADD_SUB_B_IN:std_logic_vector(27 downto 0); signal ADD_SUB_OUT:std_logic_vector(28 downto 0); signal ACC_SEL_A_IN:std_logic_vector(55 downto 0); signal ACC_SEL_B_IN:std_logic_vector(55 downto 0); signal ACC_D_IN:std_logic_vector(56 downto 0); signal ACC_Q_OUT:std_logic_vector(56 downto 0); signal ANS_Q_OUT:std_logic_vector(28 downto 0); signal CNT16_OUT:std_logic_vector(4 downto 0); component ADD_SUB port(a,b:in std_logic_vector(27 downto 0); SUB:in std_logic; S:out std_logic_vector(27 downto 0); CY_BR:out std_logic ); component EN_REG4 port(d:in std_logic_vector(26 downto 0); Q:out std_logic_vector(26 downto 0); 4.7 VHDL2/5

41 EN,CLK:in std_logic); component EN_REG13 port( D:in std_logic_vector(56 downto 0); Q:out std_logic_vector(56 downto 0); RESET,EN,CLK:in std_logic); component EN_SIN_POUT_SHIFT port(sin:in std_logic; Q:out std_logic_vector(28 downto 0); EN,PS,CLK:in std_logic); component RS_SYJKFF port(reset_b:in std_logic; SET_B:in std_logic := '1'; J:in std_logic; K:in std_logic := '0'; CLK:in std_logic; Q,Q_B:out std_logic); component EN_CNT16 port(q:out std_logic_vector(4 downto 0); EN,CLK,CLR_SY,CLR_USY:in std_logic); component SEL5 port(a,b:in std_logic_vector(27 downto 0); O:out std_logic_vector(27 downto 0); SEL:in std_logic); component SEL12 port(a,b:in std_logic_vector(55 downto 0); O:out std_logic_vector(55 downto 0); SEL:in std_logic); 4.7 VHDL3/5

42 DQ_E_OUT <= not DQ(26) and not DQ(25) and not DQ(24) and not DQ(23) and not DQ(22) and not DQ(21) and not DQ(20) and not DQ(19) and not DQ(18) and not DQ(17) and not DQ(16) and not DQ(15) and not DQ(14) and not DQ(13) and not DQ(12) and not DQ(11) and not DQ(10) and not DQ(9) and DQ(8) and not DQ(7) and not DQ(6) and not DQ(5) and not DQ(4) and not DQ(3) and not DQ(2) and not DQ(1) and not DQ(0); E_JK_FF_J_IN <= DQ_E_OUT and START; STR <= START and (not DQ_E_OUT); DQ_SEL_IN <= not JK_FF_K_IN; ACC_SEL_IN <= not STR; ACC_EN1 <= STR or JK_FF_Q_OUT; JK_FF_K_IN <= CNT16_OUT( 4 ) and CNT16_OUT( 3 ) and not CNT16_OUT( 2 ) and CNT16_OUT( 1 ) and CNT16_OUT( 0 ); LAST <= not ( JK_FF_K_IN and ANS_Q_OUT( 0 )); DQ_SEL_A_IN <= '0' & DQ_Q_OUT; DQ_SEL_B_IN <= DQ_Q_OUT & '0'; ADD_SUB_B_IN <= DQ_SEL_OUT and ( LAST & LAST & LAST & LAST & LAST & LAST & LAST & LAST & LAST & LAST & LAST & LAST& LAST & LAST & LAST & LAST& LAST & LAST & LAST & LAST& LAST & LAST & LAST & LAST& LAST & LAST & LAST & LAST ); ACC_SEL_A_IN <= ADD_SUB_OUT( 26 downto 0 ) & ACC_Q_OUT( 25 downto 0 ) & '0'; ACC_SEL_B_IN <= DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD; ACC_D_IN( 54 ) <= ADD_SUB_OUT( 27 ); ANS <= ANS_Q_OUT; ANS_SIN <= ANS_Q_OUT( 0 ) xor ADD_SUB_OUT( 28 ); ANS_EN <= not JK_FF_K_IN and JK_FF_Q_OUT; ARE <= ACC_Q_OUT( 56 downto 30 ); U_ADD_SUB:ADD_SUB port map ( ACC_Q_OUT( 55 downto 28 ), ADD_SUB_B_IN, ANS_Q_OUT( 0 ), ADD_SUB_OUT( 27 downto 0 ), ADD_SUB_OUT( 28 )); U_D:EN_REG4 port map ( DQ, DQ_Q_OUT, STR, CLOCK ); 4.7 VHDL4/5

43 ACC:EN_REG13 port map(acc_d_in,acc_q_out,reset_b, ACC_EN1,CLOCK ); U_ANS:EN_SIN_POUT_SHIFT port map(ans_sin,ans_q_out,ans_en, STR,CLOCK ); JK_FF:RS_SYJKFF port map(reset_b,open,str,jk_ff_k_in, CLOCK, JK_FF_Q_OUT, open ); E_JK_FF:RS_SYJKFF port map(reset_b,open,e_jk_ff_j_in,open, CLOCK,ER,open); CNT16:EN_CNT16 port map(cnt16_out,jk_ff_q_out,clock, STR, RESET_B ); DQ_SEL:SEL5 port map(dq_sel_a_in,dq_sel_b_in, DQ_SEL_OUT,DQ_SEL_IN); ACC_SEL:SEL12 port map(acc_sel_a_in,acc_sel_b_in, ACC_D_IN( 55 downto 0 ),ACC_SEL_IN); end DIV; 4.7 VHDL5/5 library IEEE; use IEEE.std_logic_1164.all; entity DEC_TO_BIN is port(dec:in std_logic_vector(9 downto 0); BIN:out std_logic_vector(3 downto 0)); end DEC_TO_BIN; architecture DEC_TO_BIN of DEC_TO_BIN is process(dec) case DEC is BCD VHDL1/2

44 when " " => BIN <= "0000"; when " " => BIN <= "0001"; when " " => BIN <= "0010"; when " " => BIN <= "0011"; when " " => BIN <= "0100"; when " " => BIN <= "0101"; when " " => BIN <= "0110"; when " " => BIN <= "0111"; when " " => BIN <= "1000"; when " " => BIN <= "1001"; when others => BIN <= "0000"; end case; end process; end DEC_TO_BIN; BCD VHDL2/2 library ieee; use ieee.std_logic_1164.all; entity REGA is port(deci:in std_logic_vector(9 downto 0); KEKKA:out std_logic_vector(26 downto 0); REG_EN,IN_SEL,RST,CLK:in std_logic); end REGA; architecture REGA of REGA is signal BCD:std_logic_vector(3 downto 0); signal ADDER_OUT:std_logic_vector(26 downto 0); signal REG_A_IN:std_logic_vector(26 downto 0); signal REG_A_OUT:std_logic_vector(26 downto 0); 4.9REGA VHDL1/3

45 signal MUL_OUT:std_logic_vector(26 downto 0); component DEC_TO_BIN is port(dec:in std_logic_vector(9 downto 0); BIN:out std_logic_vector(3 downto 0)); component REG_A is port(en,reset_b,clk:in std_logic; PIN:in std_logic_vector(26 downto 0); Q:out std_logic_vector(26 downto 0)); component cnv_mul is port(md:in std_logic_vector(23 downto 0); ANS:out std_logic_vector(26 downto 0); MO:out std_logic); component cnv_adder is port(a:in std_logic_vector(26 downto 0); B:in std_logic_vector(3 downto 0); S:out std_logic_vector(26 downto 0)); component INPUT_SEL is port(a,b:in std_logic_vector(26 downto 0); O:out std_logic_vector(26 downto 0); SEL:in std_logic); KEKKA <= REG_A_OUT; U_ENC:DEC_TO_BIN port map(deci,bcd); U_REG_A:REG_A port map(reg_en,rst,clk,reg_a_in,reg_a_out); U_MUL:cnv_mul port map(reg_a_out(23 downto 0),MUL_OUT,open); U_ADD:cnv_adder port map(mul_out,bcd,adder_out); 4.9REGA VHDL2/3

46 U_SEL:INPUT_SEL port map(adder_out," " & end REGA; BCD,REG_A_IN,IN_SEL); 4.9REGA VHDL3/3 library ieee; use ieee.std_logic_1164.all; entity REGB is port(asmd:in std_logic_vector(1 downto 0); REGA_OUT:in std_logic_vector(26 downto 0); REGB_OUT:out std_logic_vector(26 downto 0); TO_STATE:out std_logic_vector(28 downto 0); CLK,REG_RST,ADD_EN,SUB_EN,MUL_EN,DIV_EN:in std_logic; ERR:out std_logic); end REGB; architecture REGB of REGB is signal REG_B_IN:std_logic_vector(28 downto 0); signal REG_B_OUT:std_logic_vector(28 downto 0); signal HOSU_OUT:std_logic_vector(26 downto 0); signal ADDER_OUT:std_logic_vector(28 downto 0); signal SUB_OUT:std_logic_vector(28 downto 0); signal MUL_OUT:std_logic_vector(55 downto 0); signal DIV_OUT:std_logic_vector(28 downto 0); component REG_B is port(reset_b,clk:in std_logic; PIN:in std_logic_vector(28 downto 0); Q:out std_logic_vector(28 downto 0)); 4.10REGB VHDL1/3

47 component hosu is port(pin:in std_logic_vector(27 downto 0); Q:out std_logic_vector(26 downto 0); CLK:in std_logic); component ASMD_SEL is port(a,s,m,d:in std_logic_vector(28 downto 0); O:out std_logic_vector(28 downto 0); SEL:in std_logic_vector(1 downto 0)); component ADD is port(a:in std_logic_vector(26 downto 0); B:in std_logic_vector(28 downto 0); S:out std_logic_vector(28 downto 0); START,CLOCK,RESET_B:in std_logic); component SUB is port(a:in std_logic_vector(26 downto 0); B:in std_logic_vector(28 downto 0); DIF:out std_logic_vector(28 downto 0); START,CLOCK,RESET_B:in std_logic); component MUL is port(start,clock,reset_b:in std_logic; MD:in std_logic_vector(28 downto 0); MQ:in std_logic_vector(26 downto 0); ANS:out std_logic_vector(55 downto 0)); component DIV is port(dd:in std_logic_vector(28 downto 0); DQ:in std_logic_vector(26 downto 0); ANS:out std_logic_vector(28 downto 0); ARE:out std_logic_vector(26 downto 0); 4.10REGB VHDL2/3

48 REGB_OUT<=HOSU_OUT; TO_STATE <= REG_B_OUT; U_REG_B:REG_B port map(reg_rst,clk,reg_b_in,reg_b_out); U_HOSU:hosu port map(reg_b_out(27 downto 0),HOSU_OUT,CLK); U_SEL:ASMD_SEL port map(adder_out,sub_out, MUL_OUT(28 downto 0),DIV_OUT,REG_B_IN,ASMD); U_ADD:ADD port map(rega_out,reg_b_out,adder_out,add_en, CLK,REG_RST); U_SUB:SUB port map(rega_out,reg_b_out,sub_out,sub_en, CLK,REG_RST); U_MUL:MUL port map(mul_en,clk,reg_rst,reg_b_out,rega_out, MUL_OUT); U_DIV:DIV port map(reg_b_out,rega_out,div_out,open,div_en,clk, REG_RST,ERR); end REGB; 4.10REGB VHDL3/3 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity machine is port(regb:in std_logic_vector(28 downto 0); ASMD:out std_logic_vector(1 downto 0); CLK,RESET,DECI,PLUS,MINUS,KAKERU,WARU,EQUAL,C,CE:in std_logic; SEL,EN,RST_A,RST_B,ADD,SUB,MUL,DIV:out std_logic); end machine; 4.11 VHDL1/5

49 architecture machine of machine is type t_state is (DECIMAL,OPE,HALT); signal state:t_state; signal BR:std_logic; signal B_RST:std_logic; signal COUNT:std_logic_vector(3 downto 0); signal CAL:std_logic_vector(1 downto 0); signal ASMD_SEL:std_logic_vector(1 downto 0); signal ASMD_SELECT:std_logic_vector(3 downto 0); process(clk,reset) if(reset = '0') then COUNT <= "0000"; CAL <= "00"; state <= DECIMAL; elsif(clk'event and CLK ='1') then case state is when DECIMAL => SEL <= '1';BR<='0'; if((deci = '1') and (COUNT < 8)) then B_RST<='0'; COUNT <= COUNT + 1; state <= DECIMAL; elsif(c = '1') then COUNT <= "0000"; state <= DECIMAL; elsif(ce = '1') then COUNT <= "0000"; state <= DECIMAL; elsif((plus or MINUS or KAKERU or WARU or EQUAL) = '1') then 4.11 VHDL2/5

50 if(cal = "00") then ASMD_SELECT <= "0001"; ASMD_SEL<="00"; elsif(cal = "01") then ASMD_SELECT <= "0010"; ASMD_SEL<="01"; elsif(cal = "10") then ASMD_SELECT <= "0100"; ASMD_SEL<="10"; elsif(cal = "11") then ASMD_SELECT <= "1000"; ASMD_SEL<="11"; end if; if(plus = '1')then CAL <= "00"; elsif(minus = '1') then CAL <= "01"; elsif(kakeru = '1') then CAL <= "10"; elsif(waru = '1') then CAL <= "11"; elsif(equal = '1') then CAL <= "00"; BR <= '1'; end if; state <= OPE; end if; when OPE => SEL <= '0'; if(((regb(28) = '1') and (REGB < )) or ((REGB(28) ='0') and (REGB > ))) then state <= HALT; elsif((plus or MINUS or KAKERU or WARU) = '1') then 4.11 VHDL3/5

51 if(plus = '1')then CAL <= "00"; elsif(minus = '1') then CAL <= "01"; elsif(kakeru = '1') then CAL <= "10"; elsif(waru = '1') then CAL <= "11"; end if; state <= OPE; elsif(deci = '1') then if(br = '0') then B_RST <= '0'; COUNT <= "0001"; ASMD_SELECT<="0000"; elsif(br = '1') then B_RST <= '1'; COUNT <= "0001"; ASMD_SELECT<="0000"; end if; state <= DECIMAL; end if; when HALT => if(c = '1') then CAL <= "00"; COUNT <= "0000"; state <=DECIMAL; elsif(ce = '1') then CAL <= "00"; COUNT <= "0000"; state <=DECIMAL; end if; end case; 4.11 VHDL4/5

52 end if; end process; EN<=DECI and not(count(3)and not COUNT(2)and not COUNT(1)and not COUNT(0)); RST_A<=not(CE or C); RST_B<=not (C or B_RST); ADD<=ASMD_SELECT(0); SUB<=ASMD_SELECT(1); MUL<=ASMD_SELECT(2); DIV<=ASMD_SELECT(3); ASMD<=ASMD_SEL; end machine; 4.11 VHDL5/5 library ieee; use ieee.std_logic_1164.all; entity state is port(decimal:in std_logic_vector(9 downto 0); REG_B_OUT:in std_logic_vector(28 downto 0); ASMD:out std_logic_vector(1 downto 0); CLK,RESET,PLUS,MINUS,KAKERU,WARU,EQUAL,C,CE:in std_logic; A_D_SEL,REGA_EN,REGA_RST,REGB_RST,ADD_EN,SUB_EN,MUL_EN,DIV_E N:out std_logic); end state; architecture state of state is signal DEC:std_logic; signal ADD_IN:std_logic; signal SUB_IN:std_logic; 4.12STATE VHDL1/3

53 signal MUL_IN:std_logic; signal DIV_IN:std_logic; signal ADD_OUT:std_logic; signal SUB_OUT:std_logic; signal MUL_OUT:std_logic; signal DIV_OUT:std_logic; signal ASMD_SELECT:std_logic_vector(1 downto 0); component machine is port(regb:in std_logic_vector(28 downto 0); ASMD:out std_logic_vector(1 downto 0); CLK,RESET,DECI,PLUS,MINUS,KAKERU,WARU,EQUAL,C,CE:in std_logic; SEL,EN,RST_A,RST_B,ADD,SUB,MUL,DIV:out std_logic); component ASMD_OUT is port(input,reset,clk:in std_logic; output:out std_logic); component syncro is port(input,reset,clk:in std_logic; output:out std_logic); DEC <= DECIMAL(9) or DECIMAL(8) or DECIMAL(7) or DECIMAL(6) or DECIMAL(5) or DECIMAL(4) or DECIMAL(3) or DECIMAL(2) or DECIMAL(1) or DECIMAL(0); ADD_EN<=ADD_OUT; SUB_EN<=SUB_OUT; MUL_EN<=MUL_OUT; DIV_EN<=DIV_OUT; U_STATE:machine port map(reg_b_out,asmd_select,clk,reset,dec, PLUS,MINUS,KAKERU,WARU,EQUAL,C,CE, A_D_SEL,REGA_EN,REGA_RST,REGB_RST,ADD_IN,SUB_IN,MUL_IN,DIV_IN); 4.12STATE VHDL2/3

54 U_SYNC_A:syncro port map(add_in,reset,clk,add_out); U_SYNC_S:syncro port map(sub_in,reset,clk,sub_out); U_SYNC_M:syncro port map(mul_in,reset,clk,mul_out); U_SYNC_D:syncro port map(div_in,reset,clk,div_out); U_SYNC_ENC0_OUT:ASMD_OUT port map(asmd_select(0), RESET,CLK,ASMD(0)); U_SYNC_ENC1_OUT:ASMD_OUT port map(asmd_select(1),reset, CLK,ASMD(1)); end state; 4.12STATE VHDL3/3 library ieee; use ieee.std_logic_1164.all; entity calc is port(decimal:in std_logic_vector(9 downto 0); OUT_A,OUT_B,ANS:out std_logic_vector(26 downto 0); ANS_BCD8,ANS_BCD7,ANS_BCD6,ANS_BCD5,ANS_BCD4, ANS_BCD3,ANS_BCD2,ANS_BCD1:out std_logic_vector(3 downto 0); CLK,RESET,PLUS,MINUS,KAKERU,WARU,EQUAL,C,CE:in std_logic; SIGN,ERROR_OUT:out std_logic); end calc; architecture calc of calc is signal DECIMAL_IN:std_logic_vector(9 downto 0); signal B_STATE:std_logic_vector(28 downto 0); signal A_OUT:std_logic_vector(26 downto 0); signal B_OUT:std_logic_vector(26 downto 0); signal REG_B_RST:std_logic; 4.13 VHDL1/4

55 signal ENZAN_OUT:std_logic_vector(1 downto 0); signal ANS_BIN:std_logic_vector(26 downto 0); signal ADD_IN:std_logic; signal SUB_IN:std_logic; signal MUL_IN:std_logic; signal DIV_IN:std_logic; signal E_IN:std_logic; signal C_IN:std_logic; signal CE_IN:std_logic; signal ADD:std_logic; signal SUB:std_logic; signal MUL:std_logic; signal DIV:std_logic; signal ANS_SEL:std_logic; component A_S is port(decimal:in std_logic_vector(9 downto 0); OUT_A:out std_logic_vector(26 downto 0); OUT_B:in std_logic_vector(28 downto 0) :=" "; ASMD:out std_logic_vector(1 downto 0); CLK,RESET,PLUS,MINUS,KAKERU,WARU,EQUAL,C,CE:in std_logic; REGB_RST,ENZAN_ADD,ENZAN_SUB,ENZAN_ MUL,ENZAN_DIV,KIRIKAE:out std_logic); component REGB is port(asmd:in std_logic_vector(1 downto 0); REGA_OUT:in std_logic_vector(26 downto 0); REGB_OUT:out std_logic_vector(26 downto 0); TO_STATE:out std_logic_vector(28 downto 0); CLK,REG_RST,ADD_EN,SUB_EN,MUL_EN,DIV_EN:in std_logic; ERR:out std_logic); 4.13 VHDL2/4

56 component LASTSEL is port(a,b:in std_logic_vector(26 downto 0); O:out std_logic_vector(26 downto 0); SEL:in std_logic ); component bintobcd is port(bin:in std_logic_vector(26 downto 0); bcd8,bcd7,bcd6,bcd5,bcd4,bcd3,bcd2,bcd1:out std_logic_vector(3 downto 0)); component syncro is port(input,reset,clk:in std_logic; output:out std_logic); OUT_A<=A_OUT; OUT_B<=B_OUT; ANS<=ANS_BIN; SIGN<=(not ANS_SEL) and B_STATE(27); U_AS:A_S port map(decimal_in,a_out,open,enzan_out,clk, RESET,ADD_IN,SUB_IN,MUL_IN,DIV_IN,E_IN,C_IN, CE_IN,REG_B_RST,ADD,SUB,MUL,DIV,ANS_SEL); U_REGB:REGB port map(enzan_out,a_out,b_out,b_state, CLK,RESET and REG_B_RST,ADD,SUB,MUL,DIV,ERROR_OUT); U_ANS:LASTSEL port map(a_out,b_out,ans_bin,ans_sel); U_BCD:bintobcd port map(ans_bin,ans_bcd8,ans_bcd7,ans_bcd6, ANS_BCD5,ANS_BCD4,ANS_BCD3,ANS_BCD2,ANS_BCD1); U_SYNC_0:syncro port map(decimal(0),reset,clk,decimal_in(0)); U_SYNC_1:syncro port map(decimal(1),reset,clk,decimal_in(1)); U_SYNC_2:syncro port map(decimal(2),reset,clk,decimal_in(2)); U_SYNC_3:syncro port map(decimal(3),reset,clk,decimal_in(3)); U_SYNC_4:syncro port map(decimal(4),reset,clk,decimal_in(4)); U_SYNC_5:syncro port map(decimal(5),reset,clk,decimal_in(5)); 4.13 VHDL3/4

57 U_SYNC_6:syncro port map(decimal(6),reset,clk,decimal_in(6)); U_SYNC_7:syncro port map(decimal(7),reset,clk,decimal_in(7)); U_SYNC_8:syncro port map(decimal(8),reset,clk,decimal_in(8)); U_SYNC_9:syncro port map(decimal(9),reset,clk,decimal_in(9)); U_SYNC_A:syncro port map(plus,reset,clk,add_in); U_SYNC_S:syncro port map(minus,reset,clk,sub_in); U_SYNC_M:syncro port map(kakeru,reset,clk,mul_in); U_SYNC_D:syncro port map(waru,reset,clk,div_in); U_SYNC_E:syncro port map(equal,reset,clk,e_in); U_SYNC_C:syncro port map(c,reset,clk,c_in); U_SYNC_CE:syncro port map(ce,reset,clk,ce_in); end calc; 4.13 VHDL4/4

58 4.13 VHDL OUT_A REG_A OUT_B REGB ANS LED 4.14

59 4.15

60 4.16

61 4.17

62 4.18

63 VHDL FPGA FPGA 2 BCD BCD FPGA BCD 1591 REGA 130

64 5 VHDL VHDL VHDL FPGA FPGA 2 VHDL

65

66 VHDL HDL VLSI VHDL CQ

67 VHDL VHDL library ieee; use ieee.std_logic_1164.all; entity fulladder is port(a,b,cy_in:in std_logic; sum,cy_out:out std_logic); end fulladder; architecture fulladder of fulladder is sum<=a xor b xor cy_in; cy_out<=(a and cy_in) or (b and cy_in) or (a and b); end fulladder; VHDL1/1 ibrary ieee; use ieee.std_logic_1164.all; entity adder4 is port(a,b:in std_logic_vector(3 downto 0); cin:in std_logic; s:out std_logic_vector(4 downto 0)); end adder4; architecture adder4 of adder4 is VHDL1/2

68 signal cy:std_logic_vector(3 downto 0); component fulladder port(a,b,cy_in:in std_logic; sum,cy_out:out std_logic); fa0:fulladder port map(a(0),b(0),cin,s(0),cy(0)); fa1:fulladder port map(a(1),b(1),cy(0),s(1),cy(1)); fa2:fulladder port map(a(2),b(2),cy(1),s(2),cy(2)); fa3:fulladder port map(a(3),b(3),cy(2),s(3),cy(3)); s(4) <= cy(3); end adder4; VHDL2/2 library ieee; use ieee.std_logic_1164.all; entity BIT_SHIFT_A is port(load,clk,en:in std_logic; A_IN:in std_logic_vector(26 downto 0); Q_A:out std_logic_vector(3 downto 0)); end BIT_SHIFT_A; architecture BIT_SHIFT_A of BIT_SHIFT_A is signal REG_Q_A:std_logic_vector(26 downto 0); Q_A <= REG_Q_A(3 downto 0); process(clk) if(clk'event and CLK = '1') then VHDL1/2

69 if(load ='1') then REG_Q_A <= A_IN; elsif(en = '1') then REG_Q_A <= "0000" & REG_Q_A(26 downto 4); end if; end if; end process; end BIT_SHIFT_A; VHDL2/2 library ieee; use ieee.std_logic_1164.all; entity BIT_SHIFT_B is port(load,clk,en:in std_logic; B_IN:in std_logic_vector(28 downto 0); Q_B:out std_logic_vector(3 downto 0)); end BIT_SHIFT_B; architecture BIT_SHIFT_B of BIT_SHIFT_B is signal REG_Q_B:std_logic_vector(28 downto 0); Q_B <= REG_Q_B(3 downto 0); process(clk) if(clk'event and CLK = '1') then if(load ='1') then REG_Q_B <= B_IN; elsif(en = '1') then REG_Q_B <= "0000" & REG_Q_B(28 downto 4); VHDL1/2

70 end if; end if; end process; end BIT_SHIFT_B; VHDL2/2 library ieee; use ieee.std_logic_1164.all; entity BIT_REG is port(reset,reset_b,clk,en:in std_logic; PIN:in std_logic_vector(4 downto 0); Q:out std_logic_vector(28 downto 0)); end BIT_REG; architecture BIT_REG of BIT_REG is signal REG_Q:std_logic_vector(28 downto 0); Q <= REG_Q; process(reset,clk) if(reset = '0') then REG_Q <=(others => '0'); elsif(clk'event and CLK = '1') then if(reset_b = '1') then REG_Q <= (others => '0'); elsif(en = '1') then REG_Q <= PIN & REG_Q(27 downto 4); end if; end if; VHDL1/2

71 end process; end BIT_REG; VHDL2/2 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity EN_CNT16 is port(q:out std_logic_vector(4 downto 0); EN,CLK,CLR_SY,CLR_USY:in std_logic); end EN_CNT16; architecture EN_CNT16 of EN_CNT16 is signal CNT_BUF:std_logic_vector(4 downto 0); Q <= CNT_BUF; process(clk,clr_usy) if(clr_usy = '0') then CNT_BUF <= "00000"; elsif(clk'event and CLK = '1') then if(clr_sy = '1') then CNT_BUF <= "00000"; elsif(en = '1') then CNT_BUF <= CNT_BUF + '1'; end if; end if; end process; end EN_CNT16; VHDL1/1

72 library ieee; use ieee.std_logic_1164.all; entity RS_SYJKFF is port(reset_b,set_b:in std_logic; J,K,CLK:in std_logic; Q,Q_B:out std_logic); end RS_SYJKFF; architecture RS_SYJKFF of RS_SYJKFF is signal FF_Q:std_logic; signal IN_JK:std_logic_vector(1 downto 0); IN_JK <= J & K; Q <= FF_Q; Q_B <= not FF_Q; process(reset_b,set_b,clk) if(reset_b = '0') then FF_Q <= '0'; elsif(set_b = '0') then FF_Q <= '1'; elsif(clk' event and CLK = '1') then case IN_JK is when "01" => FF_Q <= '0'; when "10" => FF_Q <= '1'; when "11" => FF_Q <= not FF_Q; when others => null; end case; end if; end process; end RS_SYJKFF; JK VHDL1/1

73 library ieee; use ieee.std_logic_1164.all; entity ADD is port(a:in std_logic_vector(26 downto 0); B:in std_logic_vector(28 downto 0); S:out std_logic_vector(28 downto 0); START,CLOCK,RESET_B:in std_logic); end ADD; architecture ADD of ADD is signal ADDER4_OUT:std_logic_vector(4 downto 0); signal BIT_A_OUT:std_logic_vector(3 downto 0); signal BIT_B_OUT:std_logic_vector(3 downto 0); signal BIT_REG_OUT:std_logic_vector(28 downto 0); signal CNT16_OUT:std_logic_vector(4 downto 0); signal JK_FF_K_IN:std_logic; signal JK_FF_Q_OUT:std_logic; component ADDER4 port(a,b:in std_logic_vector(3 downto 0); cin:in std_logic; s:out std_logic_vector(4 downto 0)); component BIT_SHIFT_A port(load,clk,en:in std_logic; A_IN:in std_logic_vector(26 downto 0); Q_A:out std_logic_vector(3 downto 0)); component BIT_SHIFT_B port(load,clk,en:in std_logic; B_IN:in std_logic_vector(28 downto 0); Q_B:out std_logic_vector(3 downto 0)); VHDL1/2

74 component BIT_REG port(reset,reset_b,clk,en:in std_logic; PIN:in std_logic_vector(4 downto 0); Q:out std_logic_vector(28 downto 0)); component RS_SYJKFF port(reset_b:in std_logic; SET_B:in std_logic :='1'; J,K,CLK:in std_logic; Q,Q_B:out std_logic); component EN_CNT16 port(q:out std_logic_vector(4 downto 0); EN,CLK,CLR_SY,CLR_USY:in std_logic); JK_FF_K_IN <= not CNT16_OUT(4) and not CNT16_OUT(3) and CNT16_OUT(2) and CNT16_OUT(1) and not CNT16_OUT(0); S <= BIT_REG_OUT; U_A:BIT_SHIFT_A port map(start,clock,jk_ff_q_out,a, BIT_A_OUT); U_B:BIT_SHIFT_B port map(start,clock,jk_ff_q_out,b, BIT_B_OUT); U_ADDER4:ADDER4 port map(bit_a_out,bit_b_out, BIT_REG_OUT(28),ADDER4_OUT); U_REG:BIT_REG port map(reset_b,start,clock, JK_FF_Q_OUT,ADDER4_OUT,BIT_REG_OUT); JK_FF:RS_SYJKFF port map(reset_b,open,start,jk_ff_k_in, CLOCK,JK_FF_Q_OUT,open); CNT8:EN_CNT16 port map(cnt16_out,jk_ff_q_out,clock, START,RESET_B); end ADD; VHDL2/2

75 library ieee; use ieee.std_logic_1164.all; entity fullsub is port(a,b,br_in:in std_logic; dif,br_out:out std_logic); end fullsub; architecture fullsub of fullsub is dif<=a xor b xor br_in; br_out<=(not a and b) or (not a and br_in) or (b and br_in); end fullsub; VHDL1/1 library ieee; use ieee.std_logic_1164.all; entity SUB4 is port(a,b:in std_logic_vector(3 downto 0); bin:in std_logic; dif:out std_logic_vector(3 downto 0); bout:out std_logic); end SUB4; architecture SUB4 of SUB4 is signal br:std_logic_vector(3 downto 0); component fullsub port(a,b,br_in:in std_logic; dif,br_out:out std_logic); 1/2

76 fs0:fullsub port map(a(0),b(0),bin,dif(0),br(0)); fs1:fullsub port map(a(1),b(1),br(0),dif(1),br(1)); fs2:fullsub port map(a(2),b(2),br(1),dif(2),br(2)); fs3:fullsub port map(a(3),b(3),br(2),dif(3),br(3)); bout<=br(3); end SUB4; VHDL2/2 library ieee; use ieee.std_logic_1164.all; entity SUB is port(a:in std_logic_vector(26 downto 0); B:in std_logic_vector(28 downto 0); DIF:out std_logic_vector(28 downto 0); START,CLOCK,RESET_B:in std_logic); end SUB; architecture SUB of SUB is signal SUB4_OUT:std_logic_vector(4 downto 0); signal BIT_A_OUT:std_logic_vector(3 downto 0); signal BIT_B_OUT:std_logic_vector(3 downto 0); signal BIT_REG_OUT:std_logic_vector(28 downto 0); signal CNT16_OUT:std_logic_vector(4 downto 0); signal JK_FF_K_IN:std_logic; signal JK_FF_Q_OUT:std_logic; component SUB4 port(a,b:in std_logic_vector(3 downto 0); VHDL1/3

77 bin:in std_logic; dif:out std_logic_vector(3 downto 0); bout:out std_logic); component BIT_SHIFT_A port(load,clk,en:in std_logic; A_IN:in std_logic_vector(26 downto 0); Q_A:out std_logic_vector(3 downto 0)); component BIT_SHIFT_B port(load,clk,en:in std_logic; B_IN:in std_logic_vector(28 downto 0); Q_B:out std_logic_vector(3 downto 0)); component BIT_REG port(reset,reset_b,clk,en:in std_logic; PIN:in std_logic_vector(4 downto 0); Q:out std_logic_vector(28 downto 0)); component RS_SYJKFF port(reset_b:in std_logic; SET_B:in std_logic :='1'; J,K,CLK:in std_logic; Q,Q_B:out std_logic); component EN_CNT16 port(q:out std_logic_vector(4 downto 0); EN,CLK,CLR_SY,CLR_USY:in std_logic); JK_FF_K_IN <=not CNT16_OUT(4) and not CNT16_OUT(3) and CNT16_OUT(2) and CNT16_OUT(1) and not CNT16_OUT(0); DIF <= BIT_REG_OUT; VHDL2/3

78 U_A:BIT_SHIFT_A port map(start,clock,jk_ff_q_out,a, BIT_A_OUT); U_B:BIT_SHIFT_B port map(start,clock,jk_ff_q_out,b, BIT_B_OUT); U_SUB4:SUB4 port map(bit_b_out,bit_a_out, BIT_REG_OUT(28),SUB4_OUT(3 downto 0),SUB4_OUT(4)); U_BIT_REG:BIT_REG port map(reset_b,start,clock, JK_FF_Q_OUT,SUB4_OUT,BIT_REG_OUT); JK_FF:RS_SYJKFF port map(reset_b,open,start,jk_ff_k_in, CLOCK,JK_FF_Q_OUT,open); CNT8:EN_CNT16 port map(cnt16_out,jk_ff_q_out,clock, START,RESET_B); end SUB; VHDL3/3 library ieee; use ieee.std_logic_1164.all; entity REG_MD is port(load,clk:in std_logic; D:in std_logic_vector(28 downto 0); Q:out std_logic_vector(28 downto 0)); end REG_MD; architecture REG_MD of REG_MD is signal REG_Q:std_logic_vector(28 downto 0); Q <= REG_Q; process(clk) VHDL1/2

79 if(clk'event and CLK = '1') then if(load = '1') then REG_Q <= D; end if; end if; end process; end REG_MD; VHDL2/2 library ieee; use ieee.std_logic_1164.all; entity BIT_SHIFT is port(sin,en,load,clk:in std_logic; D:in std_logic_vector(26 downto 0); SOUT:out std_logic); end BIT_SHIFT; architecture BIT_SHIFT of BIT_SHIFT is signal REG_Q:std_logic_vector(26 downto 0); SOUT <= REG_Q(0); process(clk) if(clk'event and CLK = '1') then if(load = '1') then REG_Q <= D; elsif(en = '1') then REG_Q(26 downto 0) <= SIN & REG_Q(26 downto 1); end if; VHDL1/2

80 end if; end process; end BIT_SHIFT; VHDL2/2 library ieee; use ieee.std_logic_1164.all; entity ADDER32 is port(a,b:in std_logic_vector(28 downto 0); cin:in std_logic; s:out std_logic_vector(28 downto 0); cout:out std_logic); end ADDER32; architecture ADDER32 of ADDER32 is signal cy:std_logic_vector(28 downto 0); component fulladder port(a,b,cy_in:in std_logic; sum,cy_out:out std_logic); fa00:fulladder port map(a(0),b(0),cin,s(0),cy(0)); fa01:fulladder port map(a(1),b(1),cy(0),s(1),cy(1)); fa02:fulladder port map(a(2),b(2),cy(1),s(2),cy(2)); fa03:fulladder port map(a(3),b(3),cy(2),s(3),cy(3)); fa08:fulladder port map(a(8),b(8),cy(7),s(8),cy(8)); fa09:fulladder port map(a(9),b(9),cy(8),s(9),cy(9)); fa10:fulladder port map(a(10),b(10),cy(9),s(10),cy(10)); 29 VHDL1/2

81 fa11:fulladder port map(a(11),b(11),cy(10),s(11),cy(11)); fa12:fulladder port map(a(12),b(12),cy(11),s(12),cy(12)); fa13:fulladder port map(a(13),b(13),cy(12),s(13),cy(13)); fa14:fulladder port map(a(14),b(14),cy(13),s(14),cy(14)); fa15:fulladder port map(a(15),b(15),cy(14),s(15),cy(15)); fa16:fulladder port map(a(16),b(16),cy(15),s(16),cy(16)); fa17:fulladder port map(a(17),b(17),cy(16),s(17),cy(17)); fa18:fulladder port map(a(18),b(18),cy(17),s(18),cy(18)); fa19:fulladder port map(a(19),b(19),cy(18),s(19),cy(19)); fa20:fulladder port map(a(20),b(20),cy(19),s(20),cy(20)); fa21:fulladder port map(a(21),b(21),cy(20),s(21),cy(21)); fa22:fulladder port map(a(22),b(22),cy(21),s(22),cy(22)); fa23:fulladder port map(a(23),b(23),cy(22),s(23),cy(23)); fa24:fulladder port map(a(24),b(24),cy(23),s(24),cy(24)); fa25:fulladder port map(a(25),b(25),cy(24),s(25),cy(25)); fa26:fulladder port map(a(26),b(26),cy(25),s(26),cy(26)); fa27:fulladder port map(a(27),b(27),cy(26),s(27),cy(27)); fa28:fulladder port map(a(28),b(28),cy(27),s(28),cy(28)); cout<=cy(28); end ADDER32; 29 VHDL2/2 library ieee; use ieee.std_logic_1164.all; entity EN_REG is VHDL1/2

82 port(reset,en,clr,clk:in std_logic; D:in std_logic_vector(56 downto 0); Q:out std_logic_vector(56 downto 0)); end EN_REG; architecture EN_REG of EN_REG is process(reset,clk) if(reset = '0') then Q <= (others => '0'); elsif(clk'event and CLK = '1') then if(clr = '1') then Q <= (others => '0'); elsif(en = '1') then Q <= D; end if; end if; end process; end EN_REG; VHDL2/2 library ieee; use ieee.std_logic_1164.all; entity MUL is port(start,clock,reset_b:in std_logic; end MUL; MD:in std_logic_vector(28 downto 0); MQ:in std_logic_vector(26 downto 0); ANS:out std_logic_vector(55 downto 0)); VHDL1/3

83 architecture MUL of MUL is signal MQ_S_OUT:std_logic; signal JK_FF_K_IN:std_logic; signal JK_FF_Q_OUT:std_logic; signal MD_Q_OUT:std_logic_vector(28 downto 0); signal ADDER32_A_IN:std_logic_vector(28 downto 0); signal ADDER32_OUT:std_logic_vector(29 downto 0); signal CNT16_OUT:std_logic_vector(4 downto 0); signal ACC_D_IN:std_logic_vector(56 downto 0); signal ACC_Q_OUT:std_logic_vector(56 downto 0); component ADDER32 port(a,b:in std_logic_vector(28 downto 0); cin:in std_logic :='0'; s:out std_logic_vector(28 downto 0); cout:out std_logic); component REG_MD port(load,clk:in std_logic; D:in std_logic_vector(28 downto 0); Q:out std_logic_vector(28 downto 0)); component EN_REG port(reset,en,clr,clk:in std_logic; D:in std_logic_vector(56 downto 0); Q:out std_logic_vector(56 downto 0)); component BIT_SHIFT port(sin:in std_logic :='0'; EN,LOAD,CLK:in std_logic; D:in std_logic_vector(26 downto 0); SOUT:out std_logic); component RS_SYJKFF VHDL2/3

84 port(reset_b:in std_logic; SET_B:in std_logic := '1'; J,K,CLK:in std_logic; Q,Q_B:out std_logic); component EN_CNT16 port(en,clk,clr_sy,clr_usy:in std_logic; Q:out std_logic_vector(4 downto 0)); ADDER32_A_IN <= MD_Q_OUT and (MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT & MQ_S_OUT); ACC_D_IN <= ADDER32_OUT & ACC_Q_OUT(27 downto 1); JK_FF_K_IN <= CNT16_OUT(4) and CNT16_OUT(3) and not CNT16_OUT(2) and CNT16_OUT(1) and CNT16_OUT(0); ANS <= ACC_Q_OUT(55 downto 0); U_MD:REG_MD port map(start,clock,md,md_q_out); U_ADDER:ADDER32 port map(adder32_a_in, ACC_Q_OUT(56 downto 28),open,ADDER32_OUT(28 downto 0), ADDER32_OUT(29)); ACC:EN_REG port map(reset_b,jk_ff_q_out,start,clock, ACC_D_IN,ACC_Q_OUT); U_MQ:BIT_SHIFT port map (open,jk_ff_q_out,start,clock, MQ,MQ_S_OUT); JK_FF:RS_SYJKFF port map(reset_b,open,start,jk_ff_k_in, CLOCK,JK_FF_Q_OUT,open); CNT16:EN_CNT16 port map(jk_ff_q_out,clock,start, end MUL; VHDL3/3 RESET_B,CNT16_OUT);

85 library ieee; use ieee.std_logic_1164.all; entity EN_REG4 is port(d:in std_logic_vector(26 downto 0); Q:out std_logic_vector(26 downto 0); EN,CLK:in std_logic); end EN_REG4; architecture EN_REG4 of EN_REG4 is process(clk) if(clk'event and CLK = '1') then if(en = '1') then Q <= D; end if; end if; end process; end EN_REG4; VHDL1/1 library ieee; use ieee.std_logic_1164.all; entity EN_SIN_POUT_SHIFT is port(sin:in std_logic; Q:out std_logic_vector(26 downto 0); EN,PS,CLK:in std_logic); end EN_SIN_POUT_SHIFT; VHDL1/2

86 architecture EN_SIN_POUT_SHIFT of EN_SIN_POUT_SHIFT is signal SFT_BUF : std_logic_vector(26 downto 0); Q <= SFT_BUF; process (CLK) if(clk'event and CLK = '1') then if(ps = '1') then SFT_BUF(0) <= '1'; elsif(en = '1') then SFT_BUF <= SFT_BUF(25 downto 0) & SIN; end if; end if; end process; end EN_SIN_POUT_SHIFT; VHDL2/2 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity ADD_SUB is port(a,b:in std_logic_vector(27 downto 0); SUB:in std_logic; S:out std_logic_vector(27 downto 0); CY_BR:out std_logic ); end ADD_SUB; architecture ADD_SUB of ADD_SUB is signal TOTAL:std_logic_vector(28 downto 0); VHDL1/2

87 process(a,b,sub) if(sub = '1') then TOTAL <= ('0' & A) - ('0' & B); else TOTAL <= ('0' & A) + ('0' & B); end if; end process; S <= TOTAL(27 downto 0); CY_BR <= TOTAL(28); end ADD_SUB; VHDL2/2 library ieee; use ieee.std_logic_1164.all; entity SEL5 is port(a,b:in std_logic_vector(27 downto 0); O:out std_logic_vector(27 downto 0); SEL:in std_logic ); end SEL5; architecture SEL5 of SEL5 is process(a,b,sel) if(sel = '1') then O <= A; else 1/2

88 O <= B; end if; end process; end SEL5; 2/2 library ieee; use ieee.std_logic_1164.all; entity SEL12 is port(a,b:in std_logic_vector(55 downto 0); O:out std_logic_vector(55 downto 0); SEL:in std_logic ); end SEL12; architecture SEL12 of SEL12 is process(a,b,sel) if(sel = '1') then O <= A; else O <= B; end if; end process; end SEL12; 2/2

89 library ieee; use ieee.std_logic_1164.all; entity EN_REG13 is port(d:in std_logic_vector(56 downto 0); Q:out std_logic_vector(56 downto 0); RESET,EN,CLK:in std_logic); end EN_REG13; architecture EN_REG13 of EN_REG13 is process(reset,clk) if(reset = '0') then Q <=(others => '0'); elsif(clk'event and CLK = '1') then if(en = '1') then Q <= D; end if; end if; end process; end EN_REG13; 1/1 library ieee; use ieee.std_logic_1164.all; entity DIV is port (DD:in std_logic_vector(28 downto 0); DQ:in std_logic_vector(26 downto 0); VHDL1/5

90 ANS:out std_logic_vector(28 downto 0); ARE:out std_logic_vector(26 downto 0); START, CLOCK, RESET_B:in std_logic ; ER:out std_logic); end DIV; architecture DIV of DIV is signal DQ_E_OUT:std_logic; signal E_JK_FF_J_IN:std_logic; signal STR:std_logic; signal DQ_SEL_IN:std_logic; signal ACC_SEL_IN:std_logic; signal ACC_EN:std_logic; signal JK_FF_K_IN:std_logic; signal JK_FF_Q_OUT:std_logic; signal ANS_SIN:std_logic; signal ANS_EN:std_logic; signal LAST:std_logic; signal DQ_Q_OUT:std_logic_vector(26 downto 0); signal DQ_SEL_A_IN:std_logic_vector(27 downto 0); signal DQ_SEL_B_IN:std_logic_vector(27 downto 0); signal DQ_SEL_OUT:std_logic_vector(27 downto 0); signal ADD_SUB_B_IN:std_logic_vector(27 downto 0); signal ADD_SUB_OUT:std_logic_vector(28 downto 0); signal ACC_SEL_A_IN:std_logic_vector(55 downto 0); signal ACC_SEL_B_IN:std_logic_vector(55 downto 0); signal ACC_D_IN:std_logic_vector(56 downto 0); signal ACC_Q_OUT:std_logic_vector(56 downto 0); signal ANS_Q_OUT:std_logic_vector(28 downto 0); signal CNT16_OUT:std_logic_vector(4 downto 0); component ADD_SUB port(a,b:in std_logic_vector(27 downto 0); SUB:in std_logic; VHDL2/5

91 S:out std_logic_vector(27 downto 0); CY_BR:out std_logic); component EN_REG4 port(d:in std_logic_vector(26 downto 0); Q:out std_logic_vector(26 downto 0); EN,CLK:in std_logic); component EN_REG13 port(d:in std_logic_vector(56 downto 0); Q:out std_logic_vector(56 downto 0); RESET,EN,CLK:in std_logic); component EN_SIN_POUT_SHIFT port(sin:in std_logic; Q:out std_logic_vector(28 downto 0); EN,PS,CLK:in std_logic); component RS_SYJKFF port(reset_b:in std_logic; SET_B:in std_logic := '1'; J:in std_logic; K:in std_logic := '0'; CLK:in std_logic; Q, Q_B:out std_logic); component EN_CNT16 port(q:out std_logic_vector(4 downto 0); EN,CLK,CLR_SY,CLR_USY:in std_logic); component SEL5 port(a,b:in std_logic_vector(27 downto 0); O:out std_logic_vector(27 downto 0); VHDL3/5

92 SEL:in std_logic); component SEL12 port(a,b:in std_logic_vector(55 downto 0); O:out std_logic_vector(55 downto 0); SEL:in std_logic); DQ_E_OUT <= not DQ(26) and not DQ(25) and not DQ(24) and not DQ(23) and not DQ(22) and not DQ(21) and not DQ(20) and not DQ(19) and not DQ(18) and not DQ(17) and not DQ(16) and not DQ(15) and not DQ(14) and not DQ(13) and not DQ(12) and not DQ(11) and not DQ(10) and not DQ(9) and DQ(8) and not DQ(7) and not DQ(6) and not DQ(5) and not DQ(4) and not DQ(3) and not DQ(2) and not DQ(1) and not DQ(0); E_JK_FF_J_IN <= DQ_E_OUT and START; STR <= START and (not DQ_E_OUT); DQ_SEL_IN <= not JK_FF_K_IN; ACC_SEL_IN <= not STR; ACC_EN1 <= STR or JK_FF_Q_OUT; JK_FF_K_IN <= CNT16_OUT( 4 ) and CNT16_OUT( 3 ) and not CNT16_OUT( 2 ) and CNT16_OUT( 1 ) and CNT16_OUT( 0 ); LAST <= not ( JK_FF_K_IN and ANS_Q_OUT( 0 )); DQ_SEL_A_IN <= '0' & DQ_Q_OUT; DQ_SEL_B_IN <= DQ_Q_OUT & '0'; ADD_SUB_B_IN <= DQ_SEL_OUT and ( LAST & LAST & LAST & LAST & LAST & LAST & LAST & LAST & LAST & LAST & LAST & LAST& LAST & LAST & LAST & LAST& LAST & LAST & LAST & LAST& LAST & LAST & LAST & LAST& LAST & LAST & LAST & LAST ); ACC_SEL_A_IN <= ADD_SUB_OUT( 26 downto 0 ) & ACC_Q_OUT( 25 downto 0 ) & '0'; ACC_SEL_B_IN <= DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD(28)& DD; ACC_D_IN( 54 ) <= ADD_SUB_OUT( 27 ); VHDL4/5

93 ANS <= ANS_Q_OUT; ANS_SIN <= ANS_Q_OUT(0) xor ADD_SUB_OUT(28); ANS_EN <= not JK_FF_K_IN and JK_FF_Q_OUT; ARE <= ACC_Q_OUT(54 downto 28); U_ADD_SUB:ADD_SUB port map(acc_q_out(53 downto 26), ADD_SUB_B_IN,ANS_Q_OUT(0),ADD_SUB_OUT(27 downto 0), ADD_SUB_OUT(28)); U_DQ:EN_REG4 port map(dq,dq_q_out,str,clock ); ACC:EN_REG13 port map(acc_d_in,acc_q_out,reset_b, ACC_EN1,CLOCK ); U_ANS:EN_SIN_POUT_SHIFT port map(ans_sin,ans_q_out, ANS_EN,STR,CLOCK); JK_FF:RS_SYJKFF port map(reset_b, open, STR, JK_FF_K_IN, CLOCK,JK_FF_Q_OUT,open); E_JK_FF:RS_SYJKFF port map(reset_b,open,e_jk_ff_j_in, open,clock,er,open); CNT16:EN_CNT16 port map(cnt16_out,jk_ff_q_out,clock, STR,RESET_B); DQ_SEL: SEL5 port map(dq_sel_a_in,dq_sel_b_in, DQ_SEL_OUT,DQ_SEL_IN); ACC_SEL:SEL12 port map(acc_sel_a_in,acc_sel_b_in, ACC_D_IN(53 downto 0),ACC_SEL_IN); end DIV; VHDL5/5 library ieee; use ieee.std_logic_1164.all; entity DEC_TO_BIN is port(dec:in std_logic_vector(9 downto 0); 10 2 VHDL1/2

94 BIN:out std_logic_vector(3 downto 0)); end DEC_TO_BIN; architecture DEC_TO_BIN of DEC_TO_BIN is process(dec) case DEC is when " " => BIN <= "0000"; when " " => BIN <= "0001"; when " " => BIN <= "0010"; when " " => BIN <= "0011"; when " " => BIN <= "0100"; when " " => BIN <= "0101"; when " " => BIN <= "0110"; when " " => BIN <= "0111"; when " " => BIN <= "1000"; when " " => BIN <= "1001"; when others => BIN <= "0000"; end case; end process; end DEC_TO_BIN; 10 2 VHDL2/2 library ieee; use ieee.std_logic_1164.all; entity REG_A is port(en,reset_b,clk:in std_logic; PIN:in std_logic_vector(26 downto 0); VHDL1/2

95 end REG_A; Q:out std_logic_vector(26 downto 0)); architecture REG_A of REG_A is process(clk,reset_b) if(reset_b = '0') then Q <= (others => '0'); elsif (CLK'event and CLK = '1') then if(en = '1') then Q <= PIN; end if; end if; end process; end REG_A; VHDL2/2 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cnv_adder is port (A:in std_logic_vector(26 downto 0); B:in std_logic_vector(3 downto 0); S:out std_logic_vector(26 downto 0); O:out std_logic); end cnv_adder; architecture cnv_adder of cnv_adder is VHDL1/2

96 signal ADDER_OUT:std_logic_vector(27 downto 0); ADDER_OUT <= ('0' & A ) + ( '0' & B ); S <= ADDER_OUT(26 downto 0); O <= ADDER_OUT(27); end cnv_adder; VHDL2/2 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity CNV_MUL is port(md:in std_logic_vector(23 downto 0); ANS:out std_logic_vector(26 downto 0); MO:out std_logic); end CNV_MUL; architecture CNV_MUL of CNV_MUL is signal MUL_OUT:std_logic_vector(27 downto 0); MUL_OUT <= MD * "1010"; ANS <= MUL_OUT(26 downto 0); MO <= MUL_OUT(27); end CNV_MUL; 10 VHDL1/1

97 library ieee; use ieee.std_logic_1164.all; entity INPUT_SEL is port(a,b:in std_logic_vector(26 downto 0); O:out std_logic_vector(26 downto 0); SEL:in std_logic); end INPUT_SEL; architecture INPUT_SEL of INPUT_SEL is process(a,b,sel) if(sel = '1') then O <= A; else O <= B; end if; end process; end INPUT_SEL; VHDL1/1 library ieee; use ieee.std_logic_1164.all; entity REGA is port(deci:in std_logic_vector(9 downto 0); KEKKA:out std_logic_vector(26 downto 0); REG_EN,IN_SEL,RST,CLK:in std_logic); end REGA; 2 VHDL1/3

98 signal BCD:std_logic_vector(3 downto 0); signal ADDER_OUT:std_logic_vector(26 downto 0); signal REG_A_IN:std_logic_vector(26 downto 0); signal REG_A_OUT:std_logic_vector(26 downto 0); signal MUL_OUT:std_logic_vector(26 downto 0); component DEC_TO_BIN is port(dec:in std_logic_vector(9 downto 0); BIN:out std_logic_vector(3 downto 0)); component REG_A is port(en,reset_b,clk:in std_logic; PIN:in std_logic_vector(26 downto 0); Q:out std_logic_vector(26 downto 0)); component cnv_mul is port(md:in std_logic_vector(23 downto 0); ANS:out std_logic_vector(26 downto 0); MO:out std_logic); component cnv_adder is port(a:in std_logic_vector(26 downto 0); B:in std_logic_vector(3 downto 0); S:out std_logic_vector(26 downto 0)); component INPUT_SEL is port(a,b:in std_logic_vector(26 downto 0); O:out std_logic_vector(26 downto 0); SEL:in std_logic); KEKKA <= REG_A_OUT; U_ENC:DEC_TO_BIN port map(deci,bcd); 2 VHDL2/3

99 U_REG_A:REG_A port map(reg_en,rst,clk,reg_a_in, REG_A_OUT); U_MUL:cnv_mul port map(reg_a_out(23 downto 0), MUL_OUT,open); U_ADD:cnv_adder port map(mul_out,bcd,adder_out); U_SEL:INPUT_SEL port map(adder_out, " " & BCD,REG_A_IN,IN_SEL); end REGA; 2 VHDL3/3 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity REG_B is port(reset_b,clk:in std_logic; PIN:in std_logic_vector(28 downto 0); Q:out std_logic_vector(28 downto 0)); end REG_B; architecture REG_B of REG_B is process(clk,reset_b) if(reset_b = '0') then Q <= (others => '0'); elsif (CLK'event and CLK = '1') then Q <= PIN; end if; end process; end REG_B; VHDL1/1

100 library ieee; use ieee.std_logic_1164.all; entity ASMD_SEL is port(a,s,m,d:in std_logic_vector(28 downto 0); O:out std_logic_vector(28 downto 0); SEL:in std_logic_vector(1 downto 0)); end ASMD_SEL; architecture ASMD_SEL of ASMD_SEL is process(a,s,m,d,sel) if(sel = "00") then O <= A; elsif(sel = "01") then O <= S; elsif(sel = "10") then O <= M; elsif(sel = "11") then O <= D; end if; end process; end ASMD_SEL; VHDL1/1 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; 2 VHDL1/2

101 entity hosu_adder is port (A:in std_logic_vector(26 downto 0); B,CLK:in std_logic; S:out std_logic_vector(26 downto 0)); end hosu_adder; architecture hosu_adder of hosu_adder is process(clk) if(clk'event and CLK = '1') then S <= A + B; end if; end process; end hosu_adder; 2 VHDL2/2 library ieee; use ieee.std_logic_1164.all; entity hosu is port(pin:in std_logic_vector(27 downto 0); Q:out std_logic_vector(26 downto 0); CLK:in std_logic); end hosu; architecture hosu of hosu is signal ADDER_IN:std_logic_vector(26 downto 0); component hosu_adder is port (A:in std_logic_vector(26 downto 0); 2 VHDL1/2

102 B,CLK:in std_logic; S:out std_logic_vector(26 downto 0)); ADDER_IN <= PIN(26 downto 0) xor (PIN(27) & PIN(27) & PIN(27) & PIN(27) & PIN(27) & PIN(27) & PIN(27) & PIN(27) & PIN(27) & PIN(27) & PIN(27) & PIN(27) & PIN(27) & PIN(27) & PIN(27) & PIN(27) PIN(27) & PIN(27) & PIN(27) & PIN(27) & PIN(27) & PIN(27) & PIN(27) & PIN(27) PIN(27) & PIN(27) &PIN(27)); U_ADD:hosu_adder port map(adder_in,pin(27),clk,q); end hosu; 2 VHDL2/2 library ieee; use ieee.std_logic_1164.all; entity REGB is port(asmd:in std_logic_vector(1 downto 0); REGA_OUT:in std_logic_vector(26 downto 0); REGB_OUT:out std_logic_vector(26 downto 0); TO_STATE:out std_logic_vector(28 downto 0); CLK,REG_RST,ADD_EN,SUB_EN,MUL_EN,DIV_EN:in std_logic; ERR:out std_logic); end REGB; architecture REGB of REGB is signal REG_B_IN:std_logic_vector(28 downto 0); signal REG_B_OUT:std_logic_vector(28 downto 0); signal HOSU_OUT:std_logic_vector(26 downto 0); signal ADDER_OUT:std_logic_vector(28 downto 0); VHDL1/3