電気回路の構成
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1 A_Matsuzawa_Titech
2 A_Matsuzawa_Titech
3 A_Matsuzawa_Titech 3 RFCMOS RFCMOS Global Wire Signal processing On chip inductor for resonator Transmission line On chip antenna Millimeter Digital Mixed signal RF nterface to outside wireless On chip inductor for energy storage Proximity data link 3D structure nductor coupling Transformer Power processing Power Power Trans.
4 A_Matsuzawa_Titech 4
5 A_Matsuzawa_Titech 5 Scaling S /S L, W, Tox Scaling Factor /S S /S /S /S /S (
6 f T, A_Matsuzawa_Titech Design rule f T f T vs π L v s : L: 00 0 Operating Voltage
7 A_Matsuzawa_Titech 7 OP V dd V eff G = ( ) n g m r ds n: V in+ V in v outv out+ V sig_max V dd 4V eff GBW gm = π C L SNR SNR C L V sig C L V eff P V d dd ds
8 ) : g m Veff =V gs V T : 0.V0.5V ds gm Veff g m ) :r ds V ds V A r ds VA =, ds V A r ds s ) L S:.4 G = G ( ) n g m r ds n s A_Matsuzawa_Titech 8 V A g g G = g ds m ds ds V = V eff A 350nm 80nm 50nm 30nm 90nm
9 ADC A_Matsuzawa_Titech 9 ADCADC OP bit: >8 db (db)>6n+0 4 bit, >94dB ADC 0.75 st out nd out stage stage
10 A_Matsuzawa_Titech 0 V A DC r ds = g ds V A ds Gain = g m r ds = g g m ds V V eff A /5! D, Buss, et al., EEE, Tran on ED, Vol. 50, pp A.J. Annema, JSC 005, pp343
11 A_Matsuzawa_Titech Halo Halo M. Boulemnakher, E. Andre, J. Roux, F. Paillardet, A.V 4.5mW 0b, 00MS/s Pipeline ADC in a 65nm CMOS, EEE SSCC 008, Dig. of Tech. Papers, pp.505, Feb Halo
12 A_Matsuzawa_Titech Ron [Ohms] M. Boulemnakher, E. Andre, J. Roux, F. Paillardet, A.V 4.5mW 0b, 00MS/s Pipeline ADC in a 65nm CMOS, EEE SSCC 008, Dig. of Tech. Papers, pp.505, Feb Ron versus input (Vin) w=cste 0,3 0,5 0,7 0,9 Vin [V] Ron HPA Ron LVT Vt [V] 0,75 0,65 0,55 0,45 0,35 0,5 0,5 Lmin (HPA)=0.4um Vt versus length ( L) 0 0, 0,4 0,6 0,8 L [ µ m] HPA LVT
13 A_Matsuzawa_Titech 3 SA ADC6fJ/Conv. stepfom Resolution Sampling speed nput range Power Consumption SNDR DNL NL Active area Technology 0 bit 00MS/s.0Vppd 4.5mW 59dB +/0. LSB +/0. LSB 0.07mm^ ST CMOS 65nm M. Boulemnakher, E. Andre, J. Roux, F. Paillardet, A.V 4.5mW 0b, 00MS/s Pipeline ADC in a 65nm CMOS, EEE SSCC 008, Dig. of Tech. Papers, pp.505, Feb FoM= 6fJ/conv.step Tech VDD Fs Power SNDR FOM References (nm) (V) (MHz) (mw) (db) (pj/step) B.Hemes SSCC R.Wang SSCC G.Geelen SSCC K.Honda JSSCC M.Yoshioka SSCC This work
14 A_Matsuzawa_Titech 4 SNR ) C p CoxLW s = GBW GBW g πc m = = gm πc L p s s s s W L C ox R R R R Relative bandwidth sink sink Feature size ( µm )
15 Cgd D ds Cdb V eff, ds G Cgs Csb B V eff =0.75V (a)w N,W P [m/ma],v A_N, V A_P [V] DR 000 S C db L W = C V ox eff ds Cap. [ff/ma],f T [GHz] W[m/mA] 00 0 C gs W C gd f T / S S: Scaling factor (b)c pi_n, C pi_p, C po [ff/ma], p_n, p_p [GHz] DR L[m] A_Matsuzawa_Titech 5
16 SNR, SNR SNR C ) L C V L V kt sig SNR P V d sig dd s ds a) C L b) C L SNR SNR a) g m C L P d s C p P d s b) 3 ds g m GBW C L s P d s A_Matsuzawa_Titech 6
17 A_Matsuzawa_Titech 7 SNR SNR SNR R CV kt v n C L C L FS v out = ( ),, SNR (db) ( ),, ( ) 3,, ( ) 5,, bit bit n= n: configuration coefficient CV = FS SNR( db ) 0 log 8nkT 0bit V FS =5V V FS =3V V FS =V V FS =V dω = 4kTR + π vn = kt ( ωcr ) C Capacitance (pf)
18 A_Matsuzawa_Titech 8 SNR V in+ Output signal Gain v out range Boost + V dd 4V amp. eff v V out in V eff V dd C o bit bit V N 9 sig C o [pf] 0bit V eff bit 90nm 0.3m 0.8m 0.5m 0.35m V dd.v.5v.8v.5v 3.3V V sig_pp.0v.6v.v 3.6V 5.V DR[m]
19 A_Matsuzawa_Titech 9 ADC bit 0bit bit 4bit
20 A_Matsuzawa_Titech 0 ADC バイナリーサーチのアルゴリズムを用いたものが逐次比較型 ADC である OP 6bit OP V DAC V in V FS + 4 V FS V FS + V FS + V 8 6 FS C C C 4 C 8 C 6 C 6 V FS V FS + 8 V FS CMP in b = b = b =0 b = b 3 = b = b 3 = b 4 = b =0 b =0
21 A_Matsuzawa_Titech SA ADC FoM/00 FoM = FoM /00 Courtesy Y. Kuramochi 0000 SAR ADC Power vs Sampling Freq. 000 FoM 000 Power[mW] SSCC008 4bit bit FoM[fJ/conv.step] 09bit 75bit 00 0 / Sampling Freq.[MSps] Year
22 A_Matsuzawa_Titech V QP, V QN Np V TP C TP V QP C SP M= N 4 J. Craninckx and G. Van der Plas, A 65fJ/ConversionStep 0to0.7mW 9b Charge Sharing SAR ADC in 90nm Digital CMOS, EEE SSCC 0007, Dig. of Tech. Papers, pp.4647, Feb Q REF = i i C U V DD C U C TN C SN Nn V TN V QN cn cp CLK Track Sample Reset cp[0..n] Precharge Comp cn[0..n] Result SAR Controller B[0..N]
23 . C sp, C sn V QP, V QN MSB. MSB8CuC sp, C sn 3. MSB bit V QP C SP c0n c0p 8C U C SN V QN c0p c0n Precharge Precharge Track Sample Precharge Compare c0n c0p VQn CS Q = VN VQp 8 C C U VDD S Q = VN 8 CU VDD + 64 CU VDD A_Matsuzawa_Titech ±... 3
24 A_Matsuzawa_Titech 4 k 0k 00k M 0M nput frequency [Hz] ENOB Fs = 50MS/s P = 75µW 0MHz 7.8bit 90nm CMOS V Yes Yes CSSAR This work Yes No SAR Flash PL.7 No No SAR PLCBSC Subr PL. No No Σ 3.4 Yes Yes CT Σ 3. Dec. Clock Ref. FoM includes FoM [fj] P [mw] ENOB Fs [MS/s] Arch. SSCC06 Paper # Yes Yes CSSAR This work Yes No SAR Flash PL.7 No No SAR PLCBSC Subr PL. No No Σ 3.4 Yes Yes CT Σ 3. Dec. Clock Ref. FoM includes FoM [fj] P [mw] ENOB Fs [MS/s] Arch. SSCC06 Paper #
25 A_Matsuzawa_Titech 5 ADC DAC M. Hesener, A. Hanneberg, D. Herbison, F. Kuttner, and H. Wenske, A 4b 40MS/s Redundant DAR ADC with 480MHz Clock in 0.3um, EEE SSCC 0007, Dig. of Tech. Papers, pp.4849, Feb. 007.
26 A_Matsuzawa_Titech 6 40MHz3.5bit66mW FoM=40fJ/step 0.3um CMOS Supply voltage nput range Sample frequency nternal clock frequency Analog power Digital power Total power.5v ±0.9V diff. 40MHz 480MHz 49mW 7mW 66mW
27 A_Matsuzawa_Titech 7
28 A_Matsuzawa_Titech 8 MOS の V T ばらつき係数は飽和する /f ノイズ係数は穏やかに減少
29 A_Matsuzawa_Titech 9 V T VT Vt =5758mV Vt =6867mV
30 A_Matsuzawa_Titech 30 V T V T δ V T (mv) 00 0 δ V T 0.3um: Morifuji, et al., EDM um : My data ( VT ) V T TOX LW T ox LW δ 0.4um Nch 0.3um Nch Boron, w. Halo 0.3um Nch n w/o Halo* LW ( µ m )
31 A_Matsuzawa_Titech 3 V T ミスマッチは電流ミスマッチを引き起こす 高分解能のものほど小さなミスマッチが不可欠 + i 0 i + + i + i N Van den Bosch,.. Kluwer 004 σ( ) N: resolution C N C: Constant determined by NL yield Current mismatch (%),,,, 0 0% 50% 90% 99.7% NL yield σ( ) N Resolution (bit)
32 A_Matsuzawa_Titech 3 ( ) T gs ds V V L W K' = + + = L W L W K' K' V V ds ds T T ds ds + + = L W L W K' K' V V V T gs T ds ds WL K' VT T L W A L W L W LW A K' K' LW A V + = = L W K' V V ds T gs Mismatch WL K ds VT ds ds L W A WL A L A 4K' =
33 A_Matsuzawa_Titech 33 ADCSARADC ADC C C < N C C ( σ) = 0 C 4 ( pf ) V o V in V DAC Mismatch (%) bit bit 4 bit V o V o C s C s V in + C f C f C C s f = V Cs C f V DAC ( V ) in DAC Capacitance (pf)
34 A_Matsuzawa_Titech 34 Large Large Power Power dissipation Large capacitance High High precision circuits Small Small mismatch Large Large Gate Gate size size Expensive cost cost Large area Low Low cutoff cutoff frequency Large capacitance
35 LS A_Matsuzawa_Titech um : Wafer cost increases.3x for one generation /O Analog Digital Chip cost Chip area
36 A_Matsuzawa_Titech 36 /50, /0 ADC 4bit DAC 4b 00MS/s DAC.5V, 7mW, 0.mm, 0.3um Before SFDR=8dB at 0.9MHz, 6dB at 4.5MHz Area: /50 Pd: /0 NL +/ 9 LSB DNL +/ 5 LSB After +/ 0.4 LSB +/ 0.35 LSB Y. Cong and R. L. Geiger, owa state university, SSCC 003
37 A_Matsuzawa_Titech 37 4bit 00MHz DAC External ADC Y. Cong and R. L. Geiger, owa state university, SSCC 003 Compensation circuits
38 A_Matsuzawa_Titech 38 i = Nature of binary weighted values + m m + n = m + i 4 5 n = ) Measure LSB value by CAL DAC with certain accuracy. N ' δ o m = m ) Measure the error of each current source n = by comparator with binary search. ' o δ3 = 3 3) Compensate the errors by digitally ' o δ = Y. keda, A. Matsuzawa, et al., ASSCC 007. R L m o 4 o 3 o m+ n + 6 o 4 o 4 o N o N o 4 Comparator + 8 V out Logic ± o o 4 o ± ± N o ± ± o ± o N N j + N j + ± o N j + i ± o N j + i Main DAC Cal DAC Data in
39 A_Matsuzawa_Titech 39 Yusuke keda, Matthias Frey, and Akira Matsuzawa "A 4bit 00MS/s Digitally Calibrated Binary Weighted CurrentSteering CMOS DAC without Calibration ADC" ASSCC, 33, pp , Korea, Jeju, Nov, 007.
40 4dB NL (LSB) DNL (LSB) Before Calibration After Calibration NL>6LSB 0. NL<0.5LSB code code DNL>6LSB 6 0. DNL>0.3LSB NL(LSB) DNL(LSB) code NL(LSB) DNL(LSB) code 4 db UP A_Matsuzawa_Titech 40
41 A_Matsuzawa_Titech 4 30mVmV Comp_out Latched CMP C CAL V Logic C s V max V min V max V com V in + V in A 90nm CMOS.V 6b GS/s TwoStep Subranging ADC Pedro M. Figueiredo, et al., SSCC 006 V com CAL circuits C CAL C s C CAL =0 C s V min
42 /f A_Matsuzawa_Titech 4 /f S K V G = CoxWL f Gate Oxide Trap Si Gate Oxide Trap Si Drain current time
43 A_Matsuzawa_Titech 43 /f Signal Chopped noise Signal Signal + Noise Signal is reconstructed Noise is filtered out /f noise Signal C. C. Enz, E. A. Vittoz, and F. Krummenacher, EEE Journal of SolidState Circuits, Vol., No. 3, pp , June 987 Chopper freq.=khz W/O chopper Signal Chopper freq. W/ chopper LPF /f noise S Nout ( f = ) π n n = n : odd G( f nf s ) S Nin ( f nf ) s
44 A_Matsuzawa_Titech 44 微細化とともに熱雑音係数は増大 アナログ性能を劣化させる
45 A_Matsuzawa_Titech 45 nm. S&HSCF EOT = ε SiO ε thickness EOT (Equivalent Oxide Thickness) A. Hokazono et al., EDM 0, p.639
46 A_Matsuzawa_Titech 46
47 A_Matsuzawa_Titech 47 0
48 多層配線を用いた容量 配線の多層化に伴い 配線を用いた容量も現実的になった 櫛歯型等多種類利用される z MMにくらべ ばらつき(ミスマッチ)が小さい z M. Boulemnakher, et al., SSCC 008. Pipeline ADCで利用 Capacitor characteristic: ff/um² (5 stacked metal layers) ΔC/C = /5000 A_Matsuzawa_Titech 48
49 RF A_Matsuzawa_Titech 49 RFQ Q0 L R l C ω 0 = Q( ω) = π LC E magnetic E Q = ωl R l E loss / cycle electric V o V c L C L C V o Phase noise Sφ Q Resonator On chip inductor V b Current Q
50 A_Matsuzawa_Titech 50 High L/R and L/C ratio is needed nductor
51 オンチップインダクタの進歩 A_Matsuzawa_Titech 5
52 A_Matsuzawa_Titech 5 (WLCSP) C K. toi, et al., EEE MTTS MS, pp. 9700, 004.
53 A_Matsuzawa_Titech 53 WLP WLPQ TSMC 0.8um RF option M6() Al layer Q max : 0 M() Cu layer 540um, turn Q max :40 ():008
54 A_Matsuzawa_Titech 54 WLP WLP.9GHz CMOS7dB 80% CMOS0.8µm ():008
55 i i M v v v di di = L + M dt dt di di = M + L dt dt v di M dt L L v M L x L 3 N. Miura, et. al., EEE, Journal of SolidState Circuits, Vol. 4, No., pp. 334, Jan A_Matsuzawa_Titech 55
56 A_Matsuzawa_Titech 56 Data rate: Gbps/ch Energy consumption:40fj/b N. Miura, et. al., EEE, Journal of SolidState Circuits, Vol. 4, No., pp. 334, Jan. 006.
57 A_Matsuzawa_Titech 57 00MHz CTRL T on V in L V out L C R L V E out = T on Ton + T off V in L = L, PL = f L Lf L Q = π fl R T off L µ r = 900, = 50ns R G. Schrom, et. al., Proc. SLPED 04, pp. 6368, 004.
58 A_Matsuzawa_Titech 58 CMOS60GHz B. Razavi A mmwave CMOS Heterodyne Receiver with OnChip LO and Driver, EEE SSCC 0007, Dig. of Tech. Papers, pp.8889, Feb. 007.
59 A_Matsuzawa_Titech 59 Z in Z o Z L Z in = Z 0 Z Z l 0 + jz + jz 0 l tanβd tanβd d Z in λ 4 = Z Z 0 l Z λ = 4 resonator when = 0 in Z l Coplanar transmission line
60 A_Matsuzawa_Titech 60 mm A. Natarajan, et. al., EEE, Journal of SolidState Circuits, Vol. 40, No., pp. 5054, Dec A. Natarajan, et. al., EEE, Journal of SolidState Circuits, Vol. 4, No., pp , Dec. 006.
61 nterconnection Wire line Metallization Wire Wireless (EM wave) Resonator Energy conversion Antenna Wireless (Magnetic) Transmission line Transformer Z in Z o Z L A_Matsuzawa_Titech 6 d
62 A_Matsuzawa_Titech 6
63 A_Matsuzawa_Titech 63
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CMOS 376-851511 0277 (30) 1788 0277 (30)1707 e-mail: k_haruo@el.gunma-u.ac.jp AD AD AD [] AD AD AD [] ISSCC 2007 TSMC ISSCC2007 ISSCC2007 /DAC (regulation) (AGC) ADC/DAC AD AD AD [] AD CMOS SAR ADC Gr),,
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Application Report JAJA206 V+ R 5 V BIAS Q 6 Q R R 2 Q 2 Q 4 R 4 R 3 Q 3 V BIAS2 Q 5 R 6 V Ω Q V GS + R Q 4 V+ Q 2 Q 3 + V BE V R 2 Q 5 R Op Amp + Q 6 V BE R 3 Q 7 R 4 R 2 A A 2 Buffer 2 ± Ω Ω R G V+ Q.4.2
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µ CBUSY ANALOG INPUT 10V TO 10V 2. 2. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 V DIG V ANA PWRD BUSY CS R/C TAG SB/BTC DATA EXT/INT DATACLK DGND SY 28 27 26 25 24 23 22 21 20 19 18 17 16 15 10µF 0.1µF SERIAL INTERFACE
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1 CMOS 0.35um CMOS, 3V CMOS 2 RF CMOS RF CMOS RF CMOS RFCMOS (ADC Fabless 3 RF CMOS 1990 Abidi (UCLA): Fabless RF CMOS CMOS 90% 4 5 f T [GHz] 450 400 350 300 250 200 150 Technology loadmap L[nm] f T [GHz]
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( ) (mm) (GHz)=300( ) 30 300GHz=1 10mm ( 2GHz2Mbps) Gbps= Mbps ( m),? S G=P/Pi30dB=1000 Gm=4πS/λ 2, S= 80λ 2 Gm=30dB η=g/gm, S= 80λ 2,G=27dB η=50% (GHz) 80 70 60 50 40 30 20 10 16 19 22 25 28 31 34 37
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