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1 ATLAS Takashi Kuwabara

2 Abstract CERN ATLAS 1 LHC Large Hadron Collider ATLAS LHC 1 ATLAS 3 LVL1 LVL2 EF LVL1 LVL2 EF LVL1 TGC TGC TGC

3 Contents 1 LHC LHC ATLAS Experiment ATLAS Higgs Higgs ATLAS ATLAS &DAQ ATLAS &DAQ LVL LVL EF TGC TGC EI/FI TGC TGC TGC overlap TGC p T TGC TGC ii

4 ASD Board PP ASIC SLB ASIC JRC DCS PS Board SPP Board PS Pack HPT SL SSW ROD HSC CCI Online Online TGC PSB-DCS SSW HPT SL PT PT S-Link HDL SSW S-Link HDL CTM HDL CTM HDL HDL Manual TGC ATLAS TGC TGC ToDo iii

5 Delay Scan Online LVDS IC Online JTAG TGC PS PIN ATLAS PIT A PSB 100 A.1 SLB register A.2 PP register B Data Format 102 B.1 ROD Data Format B.2 PSB Data Format B.3 SSW Data Format iv

6 List of Figures LHC LHC CMS Alice LHC-B Higgs Higgs Higgs Higgs 10fb Higgs 30fb Higgs ATLAS R-Z MDT CSC RPC TGC η X-Y z=10.5m Trigger & DAQ LVL TTCpartition R-Z TGC M3 pivot TGC EI/FI TGC TGC TGC TGC Triplet doublet v

7 3.9 TGC TGC overlap p T TGC TGC TGC TGC TGC TGC PS Pack TGC TGC R-Z ASD Board ASD ASIC PP ASIC SLB AISC Wire Doublet JRC DCS PS Board PS Board Service Patch Pane PS Pack HPT HPT HPT Board SL SL SL SSW Test ROD HSC CCI Online Soft DAQ GUI Controll Line TGCJSegment PSB-DCS PSB-DCS PSB GUI DCS GUI vi

8 5.5 PSB-DCS TP Trigger L1A PT PT PT5 data G-Link SSW ROS ROD G-Link CTM HDL LVDS ATLAS Building180 ATLAS PIT L1A Delay Delay C-Side M T7/T DCS GUI Delay Scan ASD LVDS IC EWD1 JRC HV T9/T T7/T T5/T T9/T T7/T T5/T T2 PIN vii

9 6.29 1/ IP Side TGC M1 Layer B.1 Test ROD B.2 PS B.3 SSW viii

10 List of Tables 1.1 LHC ATLAS TTC PS PT5 FPGA PSB SSW RxFGPGA A.1 SLB ASIC A.2 PP ASIC ix

11 Abbreviations ADC: Analog-Digital Converter ALICE: A Large Ion Collider Experiment ASD: Amplifier Shaper Discriminator ASIC: Application Specific Integrated Circuit ATLAS: A Toroidal LHC AppratuS BCID: Bunch Crossing IDentifier BGA: Ball Grid Array CAN: Controller Area Network CASTOR: CERN Advanced STORage CCI: Crate Control Interface CLB: Configurable Logic Block CMS: the Compact Muon Solenoid COTS: Component Off The Shelf CPLD: Complex Programmable Logic Device CSC: Cathod Strip Chamber CTM: Commissioning Trigger Module CTP: Central Trigger Processor DAC: Digital-Analog Converter DCS: Detector Control System EF: Event Filter EI: Endcap Inner elmb: embeded Local Monitor Box FElink: Front End link FI: Forward Inner FPGA: Field Programmable Gate Array G-link: Gigabit rate optical link HPT: High-Pt Board HSC: High-Pt Star Switch Controller x

12 I2C: Inter Integrated Circuit IP: Interaction Point JRC: JTAG Route Controller JTAG: Joint Test Action Group (Boundary scan) L1A: Level-1 trigger Accept L1ID: Level-1 trigger IDentifier LEP: Large Electron Positron collider LHC: Large Hadron Collider LVDS: Low Voltage Differential Signaling LSlink: Local Slave link LUT: Look Up Table MDT: Monitor Drift Tube MUCTPI: Muon Central Trigger Processor Interface PP: Patch Panel PPG: Pulse Pattern Generator PSB: Patch panel Slave board Board PT4: ProtoType module version.4 PT5: ProtoType module version.5 QFP: Quad Flat Package QGP: Quark Gluon Plasma RCD: ROD Crate DAQ ROB: Read Out Buffer ROD: Read Out Driver RoI: Region of Interest ROS: Read Out System RPC: Resistive Plate Chamber RTC: Radiation Tolerance Criteria SCT: SemiConductor Tracker SD: Strip Doublet chamber SEE: Single Event Effect SEU: Single Event Upset SEL: Single Event Latchup SL: Sector Logic SLAC: Stanford Linear Accelerator Center SLB: Slave Board SLC: SLAC Linear Collider SPP: Service Patch Panel xi

13 SRAM: Static Random Access Memory SRL: Simulated Radiation Level SSC: Sub-Sector Cluster SSW: Star Switch ST: Strip Triplet chamber TGC: Thin Gap Chamber TID: Total Ionizing Dose TRT: Transition Radiation Tracker TTC: Timing Trigger Control TTL: Transistor-Transistor Logic VME: Versa Module Europe WD: Wire Doublet chamber WT: Wire Triplet chamber xii

14 1 LHC LHC Large Hadron Collider LEP Large Electron Positron collider SLC SLAC Linear Collider Tevatron 3 Higgs Higgs 1.1 Higgs TeV LHC 1.1: Higgs [1] 1.2: [1] 1

15 1.2 LHC LHC 2007 CERN 100m 2000 LEP LHC 27Km 1.3 LHC 1.3: LHC PS Proton Synchrotron SPS Super Proton Synchrotron 450GeV LHC 7TeV [2] LHC 14TeV LHC 14TeV LHC 8.4T 7TeV Higgs 100GeV 1TeV TeV 40.08MHz LHC 1.1 γ 4 /ρ 2 γ = E/mc 2 ρ

16 1.1: LHC 26.66km + 7.0TeV+7.0TeV cm 2 sec cm 2 sec GeV 40.08MHz 24.95nsec mm μm 200μrad 1.4 LHC 4 ATLAS A Toroidal LHC AppratuS ATLAS CMS the Compact Muon Solenoid 1.5 ALICE A Large Ion Collider Experiment 1.6 B-Physics LHC-B : LHC 4 LHC ATLAS CMS Alice LHC-B [2] 1.5: CMS 1.6: Alice 1.7: LHC-B [2] QGP Quark Gluon Plasma [2] B CP [2] 3

17 2 ATLAS Experiment LHC ATLAS ATLAS ATLAS 1 LHC ATLAS ATLAS TGC 3 ATLAS TGC LVL1 ATLAS 2.1 ATLAS Higgs ATLAS Higgs Higgs Higgs ATLAS Higgs ATLAS 100GeV 1TeV Higgs Higgs Higgs gg H gluon fusion 4

18 Higgs p T H γγ,zz( llll),w + W (lνlν) 2. qq qqh W/Z fusion Higgs p T 2 2 QCD Higgs 3. qq (W/Z)H W/Z associate production Higgs W/Z 4. qq/gg tth top associate production Higgs QCD Higgs 2.1: Higgs Higgs 5

19 [pb] gg H (pp H+X) pb s = 14 TeV M t = 175 GeV CTEQ4M qq _ HW qq Hqq (VBF) M H gg,qq _ Hbb _ qq _ gg,qq _ GeV HZ Htt _ 2.2: Higgs Higgs gluon fusion [3] Higgs Higgs 2.3 Higgs 1. H γγ m H <150 GeV b b c c τ + τ QCD H γγ M γγ Higgs 2. H ττ m H <150 GeV Higgs γγ W/Z fusion Higgs Z τ ET miss 3. H ZZ 4l ± 120GeV 180GeV m z Z 6

20 ZZ Zγ t t Zb b ZZ Zγ t t Zb b Z Z 4. H ZZ 4l ± 180GeV 800GeV m Z Higgs 5. H ZZ llνν 400GeV H ZZ 4l ± 6 νν ET miss 6. H WW lν jj,h ZZ ll jj 600GeV H ZZ 4l ± H WW lν jj 150 H ZZ ll jj 20 Higgs W/Z 2.3: Higgs Higgs [3] LHC fb 1 30fb 1 ATLAS Higgs ATLAS 115GeV 1TeV 5σ Higgs 7

21 Signal significance 10 2 L dt = 10 fb -1 (no K-factors) ATLAS qqh qq WW (*) qqh qq VBF, combined VBF, + + tth(bb) + ZZ * Signal significance 10 2 L dt = 30 fb -1 (no K-factors) ATLAS H tth (H bb) H ZZ (*) 4 l H WW (*) l l qqh qq WW (*) qqh qq Total significance m H (GeV/c 2 ) m H (GeV/c 2 ) 2.4: Higgs 10fb 1 Higgs 1 run LHC 10fb 1 ATLAS [4] 2.5: Higgs 30fb 1 Higgs 3 run LHC 30fb 1 ATLAS [4] SUSY LEP 1.2 1/2 q l glhc R χ 2,3,4 0 χ± 1,2 LSP Lightest SUSY Particle LSP χ 1 0 ET miss ET miss 1. Multijets+E miss T g q q χ 1 0 jets + ET miss q q χ 1 0 jets + ET miss 8

22 g 2(q q χ ± i ) 2(q q W ± χ 0 1 ) 2(jets + l ± + E miss T ) 3. 3 χ ± 1 χ0 2 lν χ ll χ 0 1 3l + E miss T Higgs MSSM Minimal Supersymmetric extension of Standard Model 2 Higgs 2 5 Higgs 5 H ± h H A Higgs 2 tanβ m A MSSM Higgs 1. H/A ττ Higgs MSSM τ 2 2. H/A μμ H/A ττ (m μ /m τ ) 2 ττ 3. H hh hh bb b b hh γγ b b 2 Higgs 4. A Zh 2 Higgs Zh llb b Z Higgs Higgs 120GeV Higgs 150GeV Higgs 9

23 Events/0.6 GeV = 2.3 GeV H o reconstructed mass (GeV) 2.6: 4 Higgs Higgs H ZZ μ + μ μ + μ Higgs 150GeV μ Z [5] 2.2 ATLAS ATLAS ATLAS 22m 44m 7000t 2.7 LHC E T miss ATLAS 10

24 22m 44m Y R X Z 2.7: ATLAS ATLAS 22m 44m [2] ET miss p T high-p T p T > 20GeV η φ Toroidal Magnet p T 10 ATLAS η < 1 1 < η 2 η θ η = ln(tanθ/2) η 11

25 1 < η < 1.9 Endcap η > 1.9 Forward T 2.8 Pixel SCTTRT μm 300μm SCT TRT 4mm 2.8: SCT TRT [5] γ ATLAS 4 2 η 2.9 Endcap Forward 2 γ 12

26 / 2.9 EM Accordion Calorimeters Hadronic Tile Calorimeters Forward LAr Calorimeters Hadronic LAr End Cap Calorimeters 2.9: 2 [5] ATLAS MDT Monitor Drift Tube CSC Cathod Strip Chamber RPC Resistive Plate Chamber TGC Thin Gap Chamber 4 ATLAS 2.10 MDT CSC Forward RPC TGC 13

27 Resistive plate chambers Cathode strip chambers Thin gap chambers Monitored drift tube chambers 2.10: MDT CSC RPC TGC [5] 12 m 10 Barrel toroid coil 8 6 End-cap toroid 4 Radiation shield m 2.11: R-Z MDT CSC Forward RPC TGC [5] 2.11 R-Z 3 φ φ R-Z 3 R-Z R 1 φ R-Z φ 2 TGC RPC φ

28 2.1: ATLAS η MDT R-Z mmφ σ x = 60μm CSC 3-dim MWPC σ x = 50μm RPC φ σ t = 1ns TGC φ σ t = 4ns MDT MDT R-Z mm 50μm 60μm 30 Cross plate Multilayer In-plane alignment Longitudinal beam 2.12: MDT 30mm [5] CSC CSC η 2 MWPC mm 5.08mm 30nsec 60μm 15

29 Rohacell Wires Strips Nomex honeycomb 0.5 mm G10 laminates Cathode read-out Spacer bar Sealing rubber Gas inlet/ outlet Anode read-out HV capacitor Conductive epoxy Wire fixation bar Epoxy 2.13: CSC MWPC [5] RPC RPC η < 1.05 R-Z R-φ ±0.02mm RPC : RPC 2 [5] TGC TGC TGC μm 1.8mm 1.4mm

30 Copper Strip 2.8mm Carbon FR4 1.8mm ASD(Wire Out) 1 2m +HV R 1 2m ASD(Strip Out) 2.15: TGC ATLAS Tm 4 8Tm η 2.17 φ R : [5] 17

31 Bdl (Tm) Barrel region = /8 Transition region End-cap region 2.5 = : η 1 6Tm 4 8Tm [5] 2.18: X-Y z=10.5m R [5] 2.3 ATLAS &DAQ LHC 40.08MHz 23 1GHz 1 1.5MByte 300Mbyte/s 1GHz ATLAS 3 200Hz DAQ LVL1 TGC ATLAS &DAQ ATLAS 2.19 LVL1 LVL2 EF 3 18

32 Interaction rate ~1 GHz Bunch crossing rate 40 MHz LEVEL 1 TRIGGER LVL1 < 75 (100) khz L1A RoIs RoI Builder LVL2 Supervisor RoIB L2SV CALO MUON TRACKING ROD ROD ROD ROB ROB ROB Pipeline memories Derandomizers Readout drivers (RODs) Read Out Links (ROLs) Read Out Systems (ROSs) latency 2.5 s 10ms LEVEL 2 TRIGGER ~ 2kHz L2Ps LVL2 Processors LVL2 & Event Builder Networks SFIs DFM Data Flow Manager Sub Farm Input 1sec EVENT FILTER ~ 200 Hz SFOs Sub Farm Output Mass Strage Data recording 2.19: Trigger & DAQ ATLAS 3 LVL1 LVL2 EF [7] LVL1 L1A LVL1 RPC TGC L1A 2.5μs 100 L1A Derandomizer L1A ROD Read Out Driver BCID ID L1A L1ID LVL1ID ROD BCID L1ID S-Link Simple Link Interface ROL Read Out Link ROB Read 19

33 Out Buffer ROB ROS Read Out System ROB LVL2 LVL2 RoI Region Of Interest 10ms ROB EF EF 1s LVL1 LVL MHz 75kHz 2.20 LVL1 TGC RPC MUCTPI Muon Trigger to CTP Interface CTP Central Trigger Processor TTC Timing Trigger and Control distribution system 75kHz 100kHz e/γ ET miss τ Jet p T CTP 2.5μsec RPC TGC p T CTP L1A Level1 Accept L1A TTC Calorimeter Trigger Muon Trigger Front-end Preprocessor Endcap Muon Trigger (TGC based) Barrel Muon Trigger (RPC based) Cluster Processor (electron/photon and hadron/tau triggers) Jet/Energy-sum Processor Muon Trigger / CTP Interface Central Trigger Processor RoI Builder TTC 2.20: LVL1 LVL1 CTP TTC ATLAS [6] 20

34 Cluster Processor & Jet/Energy-sum Processor Calorimeter Processor BCID Cluster Processor Jet/Energy-sum Processor Cluster Processor high-p T e/γ /τ Jet/Enerty-sum Processor Jet high-e T ET miss 6 8 Jet Jet CTP MUCTPI MUCTPI TGC RPC CTP RPC TGC p T MUCTPI TGC Forward 24 Endcap 48 1 RoI Region of Interest p T MUCTPI CTP LVL2 RoIB RoIBuilder CTP CTP Level1 e/γ τ/ p T CTP 96 CTP L1A CTP TTC L1A CTP 4 100nsec TTC TTC BC clock L1A TTC 2.2 TTC TGC RPC 21

35 2.2: TTC BC Clock L1A BCR ECR EVID L1ID BCID Bunch-Crossing signal LHC 40.08MHz Level 1 Accept CTP Bunch Counter Reset BCID BCID Event Counter Reset L1ID L1A EVent IDentifier ROD ROB L1ID LVL1ID Bunch-Crossing IDentifier ROD ROB Level1ID TTC ATLAS partition TGC 2 partition partition ROD partition 2 ROD Trigger Word 1 TTCpartition TTCvi VME TTC clock orbit TTCvi partition test run partition TTCpartition TTCvi LTP Local Trigger Processor TTCvx RODbusy TTCpartition LTP partition TTC LHC 40.08MHz BC μsec ORBIT CTP L1A L1A ORBIT TTCvi TTCvx TTCvi L1A TTCvx TTCvx TTCrx ASIC Application Specific Integrated Circuit TTCvi TTCvx A-Channel B-Channel 2 A-Channel L1A B-Channel TTCrx TTCrx RODbusy TTCpartition ROD busy LTP LTP busy CTP 22

36 2.21: TTCpartition TTCpartition TTCvi LTP TTCvx RODbusy LVL2 LVL2 75kHz 3kHz MDT LVL1 RoI Region of Interest RoI LVL1 RoIB RoI Builder RoI RoI LVL1 L2SV LVL2 SuperVisor L2SV RoI LVL1 LVL2 L2P LVL2 Processor L2P LVL2 ROS LVL2 LVL2 Accept L2SV DFM Data Flow Manager LVL2 3kHz L2P 500 PC LVL2 1 10msec LVL2 10msec LVL2 LVL2 Accept DFM DFM SFI Sub Farm Input buffer SFI LVL2 ROS EF SFI EF EF Event Filter 200Hz EF EF 1600 PC EF sub farm EF sub farm SFI EF sub farm EFD EF Data flow control program SFI 23

37 EFD SFI EF 200Hz EF sub farm 1 1sec EF SFI EF sub farm EF Accept EFD SFO Sub Farm Output buffer SFO Disk 1.5MByte 300MByte/s 24

38 3 TGC ATLAS TGC LVL1 R φ TGC TGC TGC TGC 3.1 TGC ATLAS TGC 3700 R 22 φ TGC M1 M2 middle M3 pivot EI Endcap Inner FI Forward Inner 5 M1 3 Triplet M2 M3 2 Doublet 7 M1 T1 T2 T3 M2 D4 D5 M3 D6 D7 ATLAS R(mm) M2(middle) middle MDT M3(pivot) M EI Inner MDT 4000 FI end-cap forward Z (mm) 3.1: R-Z TGC TGC M1 M2 M3 EI FI 32 [5] 25

39 3.1.1 M1 M2 M < η < 2.7 η < 1.9 Endcap η > 1.9 Forward 1/12 TGC φ / / Endcap φ 4 Forward φ φ 1 Endcap η 37 φ 4 Forward η 16 φ EI/FI EI/FI 1.05 < η < EI/FI 1 1/8 EI acceptance 70% Sub-sector Trigger Sector 1/ T9 T8 T7 T T5 T mete rs 0 Forward meters : M3 pivot TGC 1/12 φ [5] 3.3: EI/FI TGC 1/8 1 EI acceptance 70% [8] 26

40 3.2 TGC TGC TGC MHz TGC CO 2 /n-pentane 55/45 2.9kV 3.4(a) 1 Drift 2 3.4(b) Drift 3.4(c) 3.4(d) 3.4(e) TGC 3.4: 2 [9] TGC TGC 1 2m TGC TGC MWPC Multi-wire Proportional Chamber mm 1.8mm 25nsec 27

41 50μm 1MΩ cm TGC mm 32 Endcap 4mrad Forward 8mrad mm 1 TGC 2 R φ Graphite layer Pick-up strip HV 50 μm wire 1.8 mm 1.4 mm : TGC 2 3.6: TGC 1.6 mm G mm 1.6mm[5] Gas In Gas=CO2(55):n-pentane(45) 1.5m Gas Out HV=2.9kV AuW wire m Sn/Zn Solder FR4 parts 30cm Carbon Surface 1MΩ /cm 2 FR4 wire support width7mm ceramics button type wire support 7mm 3.7: ATLAS TGC 1 singlet Doublet 3 Triplet Doublet 2 2 Triplet

42 2 1/2 1/ : TGC Triplet doublet ATLAS TGC Triplet Doublet 2 Triplet 3 2 Doublet 2 2 [5] TGC Doublet TGC Triplet Readout Segments Readout Segments 3.9: TGC Triplet 1/3 Doublet 1/ TGC TGC 25nsec LHC 1 25nsec 3.10 TGC TGC 3GeV π nsec 25nsec 29

43 140nsec 0 TGC 25nsec 45 15nsec TGC nsec 3.10: TGC 25ns [5] overlap R φ overlap R OR double count φ OR double count

44 double count Strips not used for trigger decision in pivot plane IP doublet strips 3.11: overlap φ overlap double count [6] 3.3 TGC p T 3.12 p T Pivot Doublet Infinite Momentum Linep T Middle Doublet Triplet Infinite Momentum Line R φ δr δφ p T φ δφ = 0 R φ δφ Low-p T High-p T 2 p T Low-p T 6GeV High-p T 20GeV Middle Doublet Triplet δr δφ δr δφ Middle Doublet Low-p T Pt Triplet High-p T p T 31

45 muon path magnetic field Inf PT line beam line triplet Z=~13m pivot middle Z=~14.5m Z=~14m R Interaction Point 3.12: p T Pivot Doublet IP Interaction Point 32

46 4 TGC TGC TGC Online 4.1 TGC 3 25nsec L1A TGC TGC TGC 4.1 ASD Amplifier Shaper Discriminator PS PP ASIC Patch Panel ASIC PP ASIC Delay SLB ASIC Slave Board ASICSLB ASIC HPT High-Pt Board HPT SLB ASIC 1 HPT R φ SL Sector Logic SL R φ MUCTPI L1A TTC SLB ASIC 1 SLB ASIC SSW Star Switch SSW ROD Readout Driver ROB HSC High-pT Star-switch Controller Board CCI Control Configuration Interface Board 3 33

47 M1 M2 M3 ASD ASD On TGC chambers PS-Board PP delay BCID PP delay BCID Doublets PP delay BCID SLB ASIC 3/4 Coin. Readout elmb JRC DCS SLB ASIC 2/3 Coin. Readout Big Wheel edge Counting Room HSC(VME) crate H-Pt wire H-Pt strip SSW VME64 crates Trigger crate Sector Logic Readout crate ROD Control crate Trigger MUCTPI Readout ROB PP delay BCID JRC HSC CCI Control Triplet elmb DCS TTCvi TTC CTP Service PP CAN TTC signal fan-out to PS-Boards TTCrq DCS LCS 4.1: TGC TGC 3 [10] ASD PP ASIC SLB ASIC HPT SL 4.2 TGC ASD LVDS Low Voltage Differential Signaling PP ASIC PP ASIC TOF Time of Flight SLB ASIC PP ASIC 4 pivot middle Doublet 3 out of 4 Triplet :2 out-of 3:1 out-of 2 HPT SLB ASIC Doublet Triplet p T SL TGC p T 2 SL MUCTPI RPC

48 ASD ASD PP SLB HPT VME VME64x SL MUCTPI Trigger 4.2: TGC ASD PS LVDS PS HPT CAT6 10m 15m HPT SL HPT SL SLB ASIC M2 middle Doublet M3 pivot Doublet Strip( ) 3/4 HPT SL M1 Triplet Wire(R) 3/4 R- Trigger Wire(R) 2/3 Strip( ) 1/ 4.3: TGC SLB ASIC HPT R φ SL R φ PP ASIC SLB ASIC 1 L1A SSW SSW SLB ASIC G-Link ROD PS SLB ASIC SSW ROD ROD SSW TTC ROB

49 L1A CTP ASD ASD PP TTC rx SLB SSW VME VME64x ROD ROB Readout LVL1 Buffer Derandomizer 4.4: TGC LVL1 SLB ASIC SSW SSW SLB ASIC ROD B U S 4.5: TGC ASD PS SSW SSW SLB ASIC ROD ATLAS DCS Detector Control System 4.6 ADC Analog-Digital Converter DAC Digital-AnalogConverter elmb embedded Local Monitor Box PS HPT/SSW VME HSC CCI HSC PS PP ASIC/SLB ASIC SSW TGC DCS SSW PP ASIC/SLB ASIC elmb PS JTAG PP ASIC/SLB ASIC VME Versa Module Europe IEEE 96 DIN 32 50MB/sec IC 1 JTAG IC JTAG 36

50 JRC JTAG Routing Controller 4.6: TGC SSW HPT PC CCI HSC SSW JRC PS JRC elmb ASD ROD SL PC 4.2 TGC TGC TGC ASD PS Pack 4.7 Triplet Doublet pivot HSC HPT SSW HSC VME HSC 1 1/ UXA15 IC ASIC Antifuse FPGA Field Programmable Gate Array SRAM base FPGA m USA15 VME64x CCI SL ROD TAP Test Access Port 5 37

51 4.7: PS Pack PS Pack 1/12 [6] HSC Crate ROD/SL PS Pack 4.8: TGC PS Pack HSC USA15 VME64x CCI SL ROD 38

52 HSC CCI ROD/ROB HSC SSW 4.9: TGC R-Z Triplet PS Pack IP Doublet PS Pack IP ASD Board ASD TGC 4 ASD ASIC ASD ASIC TGC LVDS ASD TGC ASD PP ASIC PS PS ASD ASD ASD ASIC SW 2 i A B Cf = 1 pf R f = 16 k INV NON-INV Cf Rf Cb i G 7 Vth offset setting comparator preamplifier SW-position C b NON-INV > INV B discharged by i NON-INV < INV A charged-up by i 4.10: ASD Board 4.11: ASD ASIC ASD [12] 39

53 4.3.2 PP ASIC ASD TOF PP ASIC ASD LVDS LVDS CMOS variable delay 0 25ns Delay Delay 0.8ns =25ns/31 BCID ID TTC LHC clock TGC OR SLB ASIC PP ASIC ASD JTAG PP ASIC PP ASIC TTL input LVDS input Debug Line 32 Step Variable Delay 32 Step Variable Delay MASK BCID Bypass 32 Step Variable Delay MASK BCID Bypass LVDS Recciver Bypass 32 Step Variable Delay MASK BCID Charge Pomp Filter 32 Step Variable Delay (PPL CLK) 32 Step Variable Delay ( BCID Delay ) CLK Phase Detector 1/2 32 Step Variable Delay ( BCID Gate ) 32 Step Variable Delay ( TPG Fine Delay ) Test Pulse Generator TP Trigger TPG Coarse Delay JTAG TDO TDI TMS TCK 4.12: PP ASIC PP ASIC Delay 1 PP ASIC 32 [11] SLB ASIC SLB ASIC 4.13 SLB ASIC 40

54 Control P art Instruction Data Registers JTAG Tap D C B A BSC 160ch Delay Delay Mask1 Test P ulse P attern Selector Mask2 DEMUX matrix WD matrix SD matrix WT matrix ST matrix EI/FI MUX BSC 40 Input P art Trigger P art Module T ype TTC BSC 4 TPG T rigtest P ulse L1A Delay ECR BCR Input Data Trigger Output Data CLK Event Counter 4bit BCID Counter 12bit L1B (BCID) 160bit Level 1 Buffer (Input Data, 160ch) 40bit L1B (Trigger) Derandomizer 126bit Start bit Stop bit PSC (NXT-BC) [EVID(4) BCID(12) I nputdata(160) T rigger(40)] PSC (CUR-BC) [EVID(4) BCID(12) I nputdata(160) T rigger(40)] PSC (PRV-BC) [EVID(4) BCID(12) I nputdata(160) T rigger(40)] BSC 4 PSC (Status) [SLBID(5) MTYPE(3) OVFLW (8) SE U(1) 199 b0] Read O ut P art 4.13: SLB AISC PP Doublet Triplet 5 Doublet Doublet Triplet Triplet EI/FI ±7 ±3channel 4.14 Triplet Doublet 2/3 Strip 1/2 3/4 PP ASIC 1/2clock : 4.15 SLB ASIC JTAG 41

55 12x2 (middle doublet) inputs 4x2 (pivot doublet) inputs OR ed Y 8 outputs to encoder section a b c C D AB C C = a & b & c + a & b & c Y X = Y = A & C + A & D + B & D X R OR ed X Coincidence W indow(-7-+7) 4.14: Wire Doublet ±7 [6] 4.15: 1 [6] LVL1 LVL1 LVL1 212bit bit 160bit 40bit 12bit CTP L1A L1A 1 3 4bit 3 SSW 42

56 4.3.4 JRC JRC JTAG TRST TCK TMS TDI TDO 5 2 SSW elmb 4.16 CA JTAG CB JTAG JRC Q1 Q7 1 DA JTAG DB JTAG JRC PP ASIC/SLB ASIC PP ASIC/SLB ASIC JRC 7 4 PP ASIC 3 SLB ASIC JRC Antifuse FPGA /DA_TRST DA_TCK DA_TMS DA_TDI CA_JTAG Q1 /Q2_TRST Q2_TCK Q2_TMS Q2_TDI Q2_TDO DA_TDO Q3 Q4 DB_JTAG Q5 Q6 Q7 CB_JTAG 4.16: JRC [13] DCS DCS elmb ADC Analog-DigitalConverter DAC Digital-Analog Converter TGC HV High Voltage ASD elmb CAN 4.17 DCS CAN Controller Area Network 43

57 4.17: DCS PS Board PS 4.18 PP ASIC SLB ASIC JRC elmb PS ASD LVDS PP ASIC TGC overlap OR SLB ASIC SLB ASIC HPT SSW LVDS SSW elmb PP ASIC/SLB ASIC JTAG JRC PS ASIC PS ASD PS SPP Service Patch Panel TTC Timing Trigger Control LHC clock Reset 4.19 PS Service Patch Panel PS Board L1A CAN elmb ASD ASD Patch Panel Variable Delay Variable Delay Variable Delay BCID BCID Patch Panel BCID OR JTAG Route Controller Slave Board SSW HPT Variable Delay BCID LVL1 Buffer Derandomizer 4.18: PS Board PS PP ASIC SLB ASIC : PS Board 44

58 4.3.7 SPP Board SPP TTC TTCrx TTC LHC clock L1A BCR ECR Test Pulse Trigger PS SPP TTCrx I 2 C CAT6 6 HPT SPP PS Pack PS SPP 4.21 PS Pack Triplet Doublet PS Pack 1/ SPP PS Triplet 10 Doublet : Service Patch Pane TTC PS 4.21: PS Pack 1 PS Pack 2 PS HPT HPT Doublet Triplet HPT HPT PS LVDS HPT SLB ASIC Doublet Triplet HPT Triplet 2 Doublet Doublet Triplet p T HPT δr δφ m USA15 SL HPT 45

59 3 3 4 HPT ASIC 4.24 HPT from 4 wire triplet Slave Boards Phase adjust Phase adjust Phase adjust Phase adjust Clock from 3 wire doublet Slave Boards Phase adjust Phase adjust Phase adjust Decoder Decoder 192 x fold Coin. Matrix window size: + 20 H/L Pt hit position δr x 2 track selector SOS063V11 Position + δ R 7-bit x 6 Position + δ R 10-bit x : HPT ±20 from strip triplet Slave Boards Phase adjust Phase adjust Phase adjust Clock Decoder OR Decoder OR Decoder OR from 3 strip doublet Slave Boards Phase adjust Phase adjust Phase adjust Clock Decoder x 64 2-fold Coin. Matrix OR OFF H/L Pt hit position δϕ x 2 KHA010V04 Position + δϕ 6-bit x 6 track selector Position + δϕ 9-bit x : HPT ± SL SL Sector Logic TGC 2 SL R-φ SL HPT HPT R φ HPT R-φ 46

60 SSC Sub-Sector Cluster:R 2 φ 4 Sub-Sector 6 p T p T 6GeV Look-Up Table LUT6 p T p T p T 2 6 p T MUCTPI FPGA SL HPT SL SL SLB USA15 SSW SL SLB JRC 4.25 SL SL 4.25: SL SL FPGA LUT 4.24: HPT Board 47

61 from Hi-Pt board (strip) 9bit x4 decoder BCR ECR FE_BCID counter FE_L1ID counter L1 buffer Derandomizer LS-Link from Hi-Pt board (wire) from EI/FI 10bit x7 14bit decoder Clock R-? coincidence Clock EI/FI coincidence Pre-Selector Clock Track Selector L1A 2 highst Pt Track BCR Clock FE_BCID counter Encoder to MUCTPI Clock Clock Clock Clock 4.26: SL SL R φ MUCTPI Trigger Sector (End Cap) Truck Pre-Selector Truck Selector SubSector Cluster(SSC) 1 candidate/ssc # #18 SubSector # To MUCTPI #1 1 6 RI : SL p T SSW SSW Star Switch SLB ASIC ROD cell 8bit cell cell TGC 1 SSW 23 SLB ASIC SSW SLB ASIC LVDS 48

62 SSWrx SSWtx m ROD SSW PS PP ASIC SLB ASIC JTAG I 2 C SPP TTCrx 4.28 SSW ROD ROD Read Out Driver TGC ROD SSW G-Link SSW FIFO S-Link CERN ROB TTC ROD TTCrx TTC ROD 100kHz ROD 4.29 Test ROD 4.29: Test ROD 4.28: SSW ROD Test ROD SLB 49

63 HSC HSC High-pT Star-switch Controller Board HPT SSW VME HSC VME CCI CCI CCI HPT SSW HSC VME HPT SSW VME JTAG HSC CCI 2 PPE Primary Protocol Encoder JTAG JTAG SPE Secondary Protocol Encoder VME VME 4.30 HSC CCI CCI Control Configuration Interface Board HSC HSC VME VME 4.31 CCI 4.30: HSC HSC CCI PC HSC CCI SSW HPT 4.31: CCI CCI PC HSC 4.4 Online Online Online Online ATLAS 25ns 50

64 ATLAS Online Online Online 4.32 Online 4.33 DAQ GUI state segment Detector O N L I N E S O F T W A R E Datector Control System LVL1 Trigger DATA FLOW High Level Trigger ROD Crate DAQ 4.32: Online Soft 4.33: DAQ GUI Online GUI state segment DCS Online RCD ROD Crete DAQ Online RCD RCD Online state state Boot Boot configure configure Boot start start state stop stop state 51

65 RCD RCD Online ROD ATLAS DAQ RCD segment segment Class segment xml Online state RCD TGC TGC 25ns RUN RUN RUN TGC RUN 1. TTC CCI SSW PS CCI-HSC SSW SSW PS 4. TTC 5. ROD FIFO SSW 4.34 TGC ECR TTC JTAG VME SBC Single Board Computer VME 52

66 4.34: Controll Line SBC TGC SBC CCI HSC SSW JRC RCD TGC TGCRCDFEConfiguration TGCRCDFEModules TGCModules 3 RCD 4.35 ROOT Controller Database(XML) TGCJSegment TGCRCDFEConfiguration TGCModules TGCRCDFEModules VME Api (VMEHB, CCISSW ) Modules (Boards & Chips) 4.35: TGCJSegment TGCRCDFEConfiguration Local Controller process xml 53

67 RCD process TGCRCDFEModules TGCRCDFEModules RCD process state state TGCModules TGCRCDFEModules IS Information Service TGCModules Read Write IC Chip Class Module UniversalPS SSW Chip Chip API Chip Module Chip Read Write API VME 4.1 API Chip 4.1: Access module vmehb VME ROD SL TTC ccihsc CCI VME HPT SSW ccissw CCI SSW JTAG PS 54

68 5 TGC TGC TGC PT5 ProtoType module version.5 CTM Commissioning Trigger Module PT5 CTM HDL SLB ASIC 5.1 TGC TGC 3 M1 M2 M3 Triplet Doublet PS Triplet Doublet PS SLB ASIC PP ASIC IC PS 5.2 PS PS SSW ROD Doublet TGC 2 M2 M3 5.1: ASD PSB DCS SSW HPT SL HSC CCI ROD Done In Progress In progress Not yet Not yet Done Done Not yet 55

69 5.2: PS Triplet Doublet Endcap Wire EWT0,1,2 EWD0,1,2,3,4 Endcap Strip EST ESD0,1 Forward Wire FT0,1 Strip FWD0,1 Forward Strip FSD 5.1 ASD PS 4.2 PS PS Pack PS PS DCS DCS PS ASD PS PS PS Pack PS PP ASIC SLB ASIC JRC IC PC 1 GUI PS PSB-DCS bit3 SSW TTC PT4 ProtoType module version.4 SPP TTC PS SSW DCS PC CAN PS SLB ASIC PP ASIC JTAG SSW JTAG PS SSW-PSB JRC JRC IC SLB ASIC SLB TP SLB ASIC SLB ASIC SLB ASIC bit 1clk SSW SSW PT4 PT4 FIFO FIFO PC ASD TP ASD PP ASIC bit3 PC VME PC PT4 PT5 PT5 CPLD FPGA 56

70 PP ASIC overlap OR PP ASIC OR PP ASIC PP ASIC OR PP ASIC SLB ASIC bit EWD0 EWD1 PS PS PS ASD TP ASD TP SLB ASIC CTM Commissionig Trigger Module CTM FIFO CTM 5.4 DCS PS Pack JRC SLBTP SLB ASIC ASDTP PP ASIC IC SLB ASIC DCS OK PS Pack FAIL 5.1: PSB-DCS PS IC PS Pack TGC t1me t1me SLB ASIC SL HPT 57

71 Control PC Control PC TTCVi TTCVx SPP PT4 ASD DCS Board CTM PS Board SSW bit3 CAT6 LVDS G-Link TTC signal LVDS SPP signal CAN bus bit3 VME Crate 5.2: PSB-DCS VME TTC SSW bit3 PC DCS PC CAN ROOT GUI 5.3TTC PT4 GUI OK GUI DCS GUI

72 5.3: PSB GUI 5.4: DCS GUI 5.5: PSB-DCS SLB TP ASD TP SLB TP ASD TP 6.3 1/12 2 SLB ASIC PP ASIC SSW ROD SLB ASIC L1A ASD PS Delay SLB 3 out-of 4 SLB ASIC 59

73 TTC Test Pulse Trigger L1A 2 SLB ASIC Test Pulse VETO 5.6 TTCL1A NOT VETO SLB ASIC Test Pulse TTC Test Pulse Trigger SLB ASIC Test Pulse VETO SLB ASIC ReadOut VETO ASD Test Pulse 5.6: Test Pulse Trigger L1A 5.7 TTC Test Pulse Trigger SLB TP L1A ASD TP Test Pulse Trigger PP ASIC ASD ASD PS PP ASIC SLB ASIC L1A SLB TP L1A SLB TP ASD TP SLB assert TP PP issues command to ASD that assert TP ASD send TP to PP PP send TP to SLB Pipe line memory Derandomizer Test Pulse Trigger time L1A 5.7: TP Trigger L1A 60

74 5.1.2 CERN PS SLB ASIC < 1% CERN 90% SSW HPT SL SSW SSW Antifuse FPGA IC HPT SL 5.2 PT5 TGC PT5 PT5 FPGA VME ATLAS TGC PT5 FPGA FPGA ROD SSW S-Link ROS PT

75 VME A32D32 5.8: PT5 5.9: PT PT5 PT5 40.8MHz 40.08MHz NIM VME6U A32D32 FPGA 2 2 CMC Common Mzzanine Card Slot 2 DPM 16bit 16addr 5.10 PT5 VME CPLD Complex Programmable Logic Device CPLD FPGA CMC FPGA VME FPGA FPGA IC CMC VME PC [15] CERN S-Link CMC 62

76 VME BUF_A [31:18] COMPARATOR MATCH X2 BUF_A[7:1] D_DATA[7:0] CPLD CHIP SELECT SELECT WSTR RSTR IA[5:2] FPGA X2 MC_ DATA[42:0] MC BUSYR,CER, RWR,OER D_DATA[31:0] BUF_A[17:2] DPM X2 DPM_A[15:0] DPM_DATA [15:0] BUSYL,CEL, RWL,OEL MC_ DATA[42:0] MC D_DATA [31:0] BP_DATA[17:0] FPGA_ TEST CHAIN_DATA[15:0] TEST PIN 5.10: PT5 data VME CPLD CPLD FPGA FPGA 1 1 CPLD VME IC CPLD Xilinx CPLD XC2C256-PQ208PIN CPLD 2 1 VME FPGA FPGA Xilinx FPGA Spartan3-XC3S400-FG320PIN 2 IC 5.3 FPGA PT5 1 CMC Slot 1 FPGA FPGA PT G-Link 2. S-Link PC 3. G-Link 4. LVDS 1 2 ROD FPGA 16bit CLB Configurable Logic Block 63

77 5.3: PT5 FPGA CLB RAM RAM IO 400K K 288K 221 FPGA 1 1 Slot 2 PT5 G-Link 2 S-Link CERN PT4 LVDS / CAT6 PS PS IC National Semiconductor DS92LV1023/1224 LVDS input/output ASD DS90LV047A/DS90LV048A G-Link / SSW SL ROD IC Agilent Technology HDMP1032/1034 SSW IC G-Link 2 SSW2 HDMP FPGA /12 G-Link 2 SSW 5.4 1/12 M1 SSW 1 M φ

78 5.4: PSB SSW SSW Mouth No. M1 M3 ODDφ EVENφ 0 EWT1 ODDφ EWD0 EWD0 1 EWT1 EVENφ EWD1 EWD1 2 EWT2 ODDφ EWD2 EWD2 3 EWT2 EVENφ EWD3 EWD3 4 EST ODDφ EWD4 EWD4 5 EST EVENφ ESD0 ESD0 6 FT0 FWD0 7 EWT0 ODDφ FWD1 8 EWT0 EVENφ ESD1 ESD1 9 FT1 FSD 5.11: G-Link S-Link HDL ROD TGC Test ROD Test ROD 1kHz ROS CMC PT5 S-Link SSW 2 SSW M1 SSW SSW B.3 Triplet 65

79 M1 1 SSW 1/ π m2 2000Hz 2 SSW 4000Hz 1 SSW 1 1 SSW 16bit 40word 2SSW SSW 16bit 250word 2SSW SSW2 ROS SSW G-Link 2. SSW bit 32bit 6. ROS SSW PT5 Multiplexer Header & Trailer CPLD G-Link Card FPGA0 S-Link Card FPGA1 Event counter Bit transfer G-Link ROS 5.12: SSW ROS SSW2 SSW ROD S-Link 66

80 SSW G-Link FPGA Rx ROS S-Link FPGA Tx Rx FPGA G-Link2 1. G-Link FIFO FIFO = FIFO SSW FIFO 3. FIFO FIFO SSW 4. 1 FIFO FIFO 10 ROD Rx FPGA ROD Tx FPGA Tx FPGA SSW 16bit 32bit G-Link 16bit S-Link 32bit S-Link

81 SSW HEAD SSW DATA1 SSW DATA2 SSW DATAn-1 SSW DATAn SSW TRAIL Data ROD HEAD & STATUS1 ROD HEAD & STATUS12 SSW DATA1 SSW DATA2 SSW DATA3 SSW DATA4 SSW DATAn-1 SSW DATAn ROD TRAIL1 DATA COUNT(TRAIL2) ROD TRAIL3 DATA COUNT 5.13: ROD S-Link HDL 5.14 SSW ROD HDL Xilinx ISE ISE SSW ROD Rx 100MHz Tx 135MHz 40.08MHz G-Link bit 32bit 40kHz SSW 16bit 100word 2SSW S-Link 68

82 format_data sum_out 5.14: sum out SSW format data SSW sum out ROD SSW PT5 G-Link Tx SSW dummy data PT5 Multiplexer Header & Trailer G-Link Tx G-Link Rx G-Link Tx PT5 Event counter Read Data G-Link Rx 5.15: G-Link 69

83 5.4 CTM HDL TGC TGC HPT 2 HPT M1 M2 M3 CERN Blding180 HPT IP Interaction Point HPT CTM CTM HPT IC CPLD FPGA 5.16 CPLD TxFPGA RxFPGA 5.16: CTM IC CPLD VME CPLD CPLD PT5 XC2C256-PQ208PIN IC VME 70

84 RxFPGA PS FPGA CTM 10 FPGA Xilinx XC2S50E-TQ144PIN IC 5.5 CTM CAT6 LVDS 10 1 FPGA FPGA M2 M3 1/12 1/4 5.5: RxFGPGA CLB RAM RAM IO 50K K 32K 102 TxFPGA RxFPGA FPGA CTM RxFPGA TxFPGA Xilinx XC2S50E- PQ208PIN IC RxFPGA IC IO IO 146PIN TxFPGA NIM NIM HDL SLB ASIC HDL 5.17 PS LVDS RxFPGA TxFPGA HDL 71

85 5.17: HDL RxFPGA RxFPGA 3 Independent CLK FIFO FIFO FIFO LVDS FIFO Idle CAT6 CAT ,2 3,6 4,5 7,8 PS PS 4 72

86 1,2 pair 3,6 pair 4,5 pair 7,8 pair 5.18: LVDS TxFPGA TxFPGA RxFPGA RxFPGA RxFPGA RxFPGA OR HDL 5.19 Independent CLK FIFO PS xin rcvclk dump_out 5.19: FIFO rcvclk xin dbclk dump out 2 73

87 5.5 Manual Online 4.4 Manual SBC Manual TGCModules TGCRCDFEModules Online PT5 CTM bit3 SBC Online SBC Manual PT5 CTM ManualSSW ManualPS ManualTtc ManualPT5 ManualTRG CTM ManualPT5 ManualTRG SL HPT Manual 74

88 6 TGC TGC ATLAS TGC TGC 2 PS PS TGC PIT ATLAS ATLAS TGC 6.1 ATLAS TGC ATLAS TGC ToDo ATLAS LHC C-Side M2 ATLAS A-Side C-Side 75

89 Sep '06 Oct '06 Feb '07 Mar '07 Apr '07 May '07 Jun '07 Jul '07 Aug '07 Oct '07 Nov ' BT test Nov '06 Dec '06 Jan '07 Sep '07 Full Magnet test Dec '07 Side A Barrel Barrel Muon A services J N ID barrel connection and testing services installation BW-A (tooling +M1) opening ID A LAr A cool down Cold tests BW-A (MDT) Endcap Toroid A ECT on half truck JT IDA connection and testing Access from sector 13 IDC connection and testing LAr C cool down BW-A (M2) Cold tests Small Wheel A VA VT BW-A (M3) Access restrictions once toroid in place Pixel connection and testing Limited access Global Commissioning JF global tests, pump down & bake out JF VJ EO, side A Global Commissioning UX15 & LHC closing Beam 450 GeV + collisions Side A Barrel Side C Big Wheel (M1) Big Wheel (MDT) BIG WHEEL (M2) opening ID C ID C Truck Big Wheel (M3) opening Pixel Muon Barrel C JT VA Endcap Toroid Small C Wheel C Big Wheels in park position VT JF VJ JF ECT- C cooldown & test EO, side C Side C Sep '06 Oct '06 Nov '06 Dec '06 Jan '07 Feb '07 Mar '07 Apr '07 May '07 Jun '07 Jul '07 Aug '07 Sep '07 Oct '07 Nov '07 Dec '07 6.1: ATLAS ATLAS [14] TGC ToDo TGC TGC 1. TGC 2. TGC HV 3. TGC 4. ATLAS PIT TGC CERN Building /12 C-Side M1 ATLAS PIT 76

90 C-Side M1 M2 M3 A-Side M1 ATLAS PIT Sector assembly site ( Building 180 ) 6.2: Building180 ATLAS PIT CERN MAP Building180 ATLAS PIT / (a) LV/HV (b) : 6.4: 77

91 6.5: 6.6: /12 HV/LV ASD ASD 2 1 ASD PP ASIC LVDS PSB-SWW CAT6 JTAG PSB SSW 6.5 Delay TGC

92 Online Online Online M1 M2 M3 6.7 SLB TP ASD TP Test ROD TGC ASD test pulse PP delay BCID PP delay BCID Triplet SLB ASIC 2/3 Coin. Readout elmb JRC DCS SSW HSC Readout crate test ROD Control crate CCI Readout Slink Receiver Control TTCvi Service PP CAN TTC signal fanout to PS-Boards TTCrq DCS LCS L1A, reset, test pulse 6.7: SSW Test ROD M2 PS M2 PS M2 PS Universal Board DAQ 1. Delay 2. JTAG JRC CAT6 3. SLB TP SLB ASIC 4. ASD TP ASD PP ASIC LVDS DCS DCS Universal Board Triplet Doublet PS ASIC 79

93 PS SSW ROD SLB TP ASD TP Delay TTC L1A Delay Delay 1. L1A SLB ASIC 6.8 L1A 2. SLB TP 3. ASD PP ASIC Delay 4. ASD TP Delay : L1A L1A 250ns 80

94 M3_T9 wire layer1 bunch1 No. of events M3_T9 wire l1 b1 Entries 2287 Mean RMS M3_T8 wire layer1 bunch1 No. of events M3_T8 wire l1 b1 Entries 4312 Mean RMS Channel Channel M3_T9 wire layer2 bunch1 No. of events M3_T9 wire l2 b1 Entries 2612 Mean RMS M3_T8 wire layer2 bunch1 No. of events M3_T8 wire l2 b1 Entries 3147 Mean RMS Channel Channel 6.9: Delay M3_T9 wire layer1 bunch1 M3_T9 wire l1 b1 Entries Mean 16.5 RMS Channel No. of events M3_T9 wire layer2 bunch1 M3_T9 wire l2 b1 Entries Mean 16.5 RMS Channel No. of events M3_T8 wire layer1 bunch1 M3_T8 wire l1 b1 Entries Mean 16 RMS Channel No. of events M3_T8 wire layer2 bunch1 M3_T8 wire l2 b1 Entries Mean 16 RMS Channel No. of events 6.10: Delay M3 T9 T8 Delay Delay C-Side M3 φ3 Endcap φ2 Forward C-Side M η φ φ3 [16] 81

95 φ L1A 1 1 M φ0 Beam Direction φ1 φ0 φ2 φ3 T9 T8 T7 Endcap T6 T5 T2 Forward φ2 6.11: C-Side M3 DCS ASD TP DCS DCS DCS GUI BCID 82

96 M3_T7 strip layer1 bunch1 No. of events M3_T7 strip l1 b1 Entries 6064 Mean RMS M3_T6 strip layer1 bunch1 No. of events M3_T6 strip l1 b1 Entries 1533 Mean RMS Channel Channel M3_T7 strip layer2 bunch1 No. of events M3_T7 strip l2 b1 Entries 4218 Mean RMS M3_T6 strip layer2 bunch1 No. of events M3_T6 strip l2 b1 Entries 955 Mean RMS Channel Channel 6.12: T7/T6 T7 T6 T7 DCS T6 BCID Threshold High T hreshold L ow Timing is different! 6.13: 6.14: DCS GUI Delay Scan PP ASIC Delay ASD TP Delay

97 Current bunch Previous bunch Next bunch 6.15: Delay Scan ns 0 Delay BCID Delay Scan ASD PP ASIC Delay PS Online 1/12 RCD Online 2006 Online ver state ver state 6.1 initial Load configure start ver Boot configure start 6.1: 84

98 Load state Boot Load Load TTC state Load state Online Boot state configure state 6.4 IC M3 2 1 LVDS IC 1 JTAG ASD M3 T9 2 M3_T9 wire layer1 bunch1 No. of events M3_T9 wire l1 b1 Entries 6386 Mean 16.5 RMS M3_T8 wire layer1 bunch1 No. of events M3_T8 wire l1 b1 Entries 6180 Mean 16 RMS Channel Channel M3_T9 wire layer2 bunch1 No. of events M3_T9 wire l2 b1 Entries 6180 Mean RMS M3_T8 wire layer2 bunch1 No. of events M3_T8 wire l2 b1 Entries 6180 Mean 16 RMS Channel Channel 6.16: ASD M3 T9 T8 PP TP M3 T9 2 1 bit 85

99 ASD. PS PP ASIC SLB ASIC 1. ASD ASD ASD 2. PP ASIC ASD 3. PP ASIC PS LVDS IC M3 PS LVDS IC LVDS 3 4 elosc0.kek.jp 4 Dec :57: : LVDS IC IC IC LVDS 3 LVDS IC M1 86

100 CERN IC CAT6 CAT6 CAT6 CAT6 ON/OFF CAT6 CAT6 M3 15m CAT6 IC CAT6 PS CAT6 LVDS IC PS IC Online JTAG Online PS EWD1 JTAG PP ASIC JTAG Online configure JTAG Manual 5.5 JTAG EWD1 Online JTAG Manual JTAG JTAG Manual Online Online Manual JTAG TCK TDI TMS Online Manual 87

101 7 6 5 JRC NONE SLB SLB PP PP PP PP PP PP PP PP PP 6.18: EWD1 JRC EWD1 JRC SLB ASIC PP ASIC PP ASIC TGC TGC Building180 TGC ATLAS LVL CTM 6.19 M3 φ2 Forward φ3 Endcap 88

102 1/12 Sector PS Pack PS Board DCS Control PC CAT6 LVDS Optical fiber G-Link TTC signal S-Link LVDS LAN NIM signal CAN bus HPT Crate TGC Control PC SSW bit3 ROD SSW Control PC SPP CTM ROD Crate TTC Crate CTM HSC CCI TTCVx TTCVi HV SBC CO2 Gas NIM OR NIM Crate 6.19: M3 HV SLB ASIC CTM L1A SLB TP TGC CO 2 /n-pentane CO 2 DCS -70mV 70mV HV 2.9kV SLB TP SLB ASIC L1A ASD PP ASIC Delay ASD TP 89

103 - 25ns ASD TP Delay ASD PP ASIC Delay SLB ASIC CTM M3 1/12 SLB ASIC 3 out-of 4 SLB ASIC M2 3 out-of 4 M3 2 out-of 2 1 out-of 2 2 out-of 2 1 out-of 2 ASD TP 1 2 CTM 1 out-of 2 ASD PP ASIC LVDS M PP ASIC 2 2 ASD TP Delay TGC p T 1 out-of 2 HV 1 HV HV 1 out-of 2 90

104 Channel M3_T9 wire layer1 bunch No. of events M3_T9 wire l1 b1 Entries 1740 Mean 16.6 RMS M3_T8 wire layer1 bunch No. of events M3_T8 wire l1 b1 Entries 11 Mean RMS M3_T7 wire layer1 bunch No. of events M3_T7 wire l1 b1 Entries 7 Mean RMS Channel Channel M3_T9 wire layer2 bunch No. of events M3_T9 wire l2 b1 Entries 108 Mean 31.2 RMS M3_T8 wire layer2 bunch No. of events M3_T8 wire l2 b1 Entries 2140 Mean 15.6 RMS M3_T7 wire layer2 bunch No. of events M3_T7 wire l2 b1 Entries 2336 Mean RMS Channel Channel Channel 6.20: 2 HV T9/T8/T7 T9 HV HV ASD PP ASIC LVDS ASD CO 2 M3 φ2 Forward φ3 Endcap 1/ π m Hz 2 out-of 2 70Hz 2 out-of 2 70Hz out-of 2 30 η 2 91

105 No. of events M3_T9 wire layer1 bunch M3_T9 wire l1 b1 Entries Mean RMS No. of events M3_T8 wire layer1 bunch M3_T8 wire l1 b1 Entries Mean RMS Channel Channel No. of events M3_T9 wire layer2 bunch M3_T9 wire l2 b1 Entries Mean RMS 9.1 No. of events M3_T8 wire layer2 bunch M3_T8 wire l2 b1 Entries Mean RMS Channel Channel 6.21: T9/T8 No. of events M3_T7 wire layer1 bunch M3_T7 wire l1 b1 Entries Mean RMS No. of events M3_T6 wire layer1 bunch M3_T6 wire l1 b1 Entries Mean RMS Channel Channel No. of events M3_T7 wire layer2 bunch M3_T7 wire l2 b1 Entries Mean RMS No. of events M3_T6 wire layer2 bunch M3_T6 wire l2 b1 Entries Mean 49.4 RMS Channel Channel 6.22: T7/T6 92

106 No. of events M3_T5 wire layer1 bunch M3_T5 wire l1 b1 Entries Mean RMS No. of events M3_T2 wire layer1 bunch M3_T2 wire l1 b1 Entries Mean RMS Channel Channel No. of events M3_T5 wire layer2 bunch M3_T5 wire l2 b1 Entries Mean RMS 28.1 No. of events M3_T2 wire layer2 bunch M3_T2 wire l2 b1 Entries Mean RMS Channel Channel 6.23: T5/T2 M3_T9 strip layer1 bunch1 No. of events M3_T9 strip l1 b1 Entries Mean 16.8 RMS M3_T8 strip layer1 bunch1 No. of events M3_T8 strip l1 b1 Entries Mean RMS Channel Channel M3_T9 strip layer2 bunch1 No. of events M3_T9 strip l2 b1 Entries Mean 17.4 RMS 9.64 M3_T8 strip layer2 bunch1 No. of events M3_T8 strip l2 b1 Entries Mean RMS Channel Channel 6.24: T9/T8 93

107 M3_T7 strip layer1 bunch1 No. of events M3_T7 strip l1 b1 Entries 1257 Mean RMS M3_T6 strip layer1 bunch1 No. of events M3_T6 strip l1 b1 Entries 1469 Mean RMS Channel Channel M3_T7 strip layer2 bunch1 No. of events M3_T7 strip l2 b1 Entries 1250 Mean RMS M3_T6 strip layer2 bunch1 No. of events M3_T6 strip l2 b1 Entries 1541 Mean RMS Channel Channel 6.25: T7/T6 M3_T5 strip layer1 bunch1 No. of events M3_T5 strip l1 b1 Entries 1415 Mean RMS M3_T2 strip layer1 bunch1 No. of events M3_T2 strip l1 b1 Entries Mean RMS Channel Channel M3_T5 strip layer2 bunch1 No. of events M3_T5 strip l2 b1 Entries 1291 Mean RMS M3_T2 strip layer2 bunch1 No. of events M3_T2 strip l2 b1 Entries Mean RMS Channel Channel 6.26: T5/T2 2 out-of 2 T8 70mV T2 BCID 25% 2 out-of 2 ASD 1 94

108 T7/T6/T5 PP ASIC SLB ASIC HV ASD CTM T2 PS xml η T7/T6/T5 BCID T8 1 95

109 T8 strip phi eta wire 6.27: 2 2 BCID 2 out-of PS PIN 6.23 T2 3 PS PIN PIN 6.28 Forward Doublet PS FWD0 FWD1 96

110 Database Lack of bits! Blank ASD channels Chamber Blank ASD channels Dead channel! η 6.28: T2 PIN 6.6 ATLAS PIT 1/12 ATLAS PIT 6.29ATLAS PIT HO IP 6.30 C-Side M1 IP 6.31 C-SIDE M1 ATLAS PIT ATLAS PIT C-Side M2 TGC 6.29: 1/12 97

111 M 1 M 1 HAD IP Side HAD HO Side EM LAr Cal AEJ JM FCAL JNose TAS QUAD 48 ACCESS Rails 6.30: IP Side ATLAS PIT R-Z HO 1/12 IP 6.31: TGC M1 Layer 98

112 7 ATLAS TGC 1/12 TGC TGC Test ROD PT5 99

113 A PSB A.1 SLB register SLB ASIC register x = 1 write mode x = 0 read mode name Bit R/W Instruction Default notes DEPTH 21 RW x Depth of L1 Buffer: (Input[20:14] Trigger[13:7] BCID[6:0]) TESTPULSE 5 RW x Set delay of Test Pulse Trigger DELAY 4 RW x All 0 Set delay of input(obsolete, not connected) DELAY A 3 RW x All 0 Set delay of A-row input DELAY B 3 RW x All 0 Set delay of B-row input DELAY C 3 RW x All 0 Set delay of C-row input DELAY D 3 RW x All 0 Set delay of D-row input SCHEME 1 RW x 0 Low : 3 out-of 4, High : 4 out-of 4 L1VETO 1 RW x 0 Low : through, High : L1A = 0 CLKINV 1 RW x 1 Low : order, High : invert RESET 1 RW x 0 Put Internal ECR & BCR(Positive Active) DRDRST 1 RW x 0 Derandomizer Rest(Positive Active) DCVETO 1 RW x 0 Low : DC balanced, High : Normal SEU 1 RO (0) SEU Flag(indicates any SEU(s) happen) MODULE 8 RO Indicate Module Type and Module Address OVERFLOW 8 RO (All 0) Indicate Derandomizer Overflow ID 32 RO chipid: MASK1P 160 RW x All 0 Mask Pattern for Readout and Matrix MASK1 160 RW x All 0 Mask Enable for Readout and Matrix MASK2P 160 RW x All 0 Mask Pattern for Matrix only MASK2 160 RW x All 0 Mask Enable for Matrix only TPP 160 RW x All 0 Test Pulse Pattern BSR 48 RO Boundary Scan Cell A.1: SLB ASIC 100

114 A.2 PP register PP ASIC register x = 1 write mode x = 0 read mode name Bit R/W Instruction Default notes BCID MASKA 16 RW x All 1 BCID Mask register (Port-A) 0 signal masks an input signal and 1 signal un-masks an input signal. LSB corresponds to INA0. BCID MASKB 16 RW x All 1 About Port-B. Notes are same as Port-A. TPG AMPA 4 RW x All 1 Test Pulse Amplitude register (Port-A) Data=0 sets no signal output. TPG AMPB 4 RW x All 1 About Port-B. Notes are same as Port-A. TPG FINEA 5 RW x All 1 Fine-Delay register for Test Pulse (Port-A) Data[4:3] : MUST NOT be set. Sub-nano sectond step (25/31ns) TPG FINEB 5 RW x All 1 About Port-B. Notes are same as Port-A. TPG COARSEA 5 RW x All 1 Test Pulse Coarse-Delay register (Port-A) Data[4:3] defines the timing when the Test Pulse Trigger (TP Trigger) signal is taken. Data[4:3]=0x00, 0x11 : The TP Trigger signal is taken at failling or rising edge of the clock. Data[4:3]=0x01, 0x10 : MUST NOT be set. Data[2:0] sets the Coarse-Delay (25ns step) TPG COARSEB 5 RW x All 1 About Port-B. Notes same as Port-A. SIGNAL DELA 5 RW x All 1 Hit Signal Delay register (Port-A) Sub-nano sectond step (25/31ns) SIGNAL DELB 5 RW x All 1 About Port-B. Notes same as Port-A. BCID DELA 5 RW x All 1 Delay register for BCID clock (Port-A) Sub-nano sectond step (25/31ns) BCID DELB 5 RW x All 1 About Port-B. Notes same as Port-A. BCID GATEA 5 RW x All 1 Delay register for BCID gate width (Port-A) Sub-nano sectond step (25/31ns) The effective gate width can be set at approximately from 26ns to 48ns. BCID GATEB 5 RW x All 1 About Port-B. Notes same as Port-A. DEBUG DEL 5 RW x All 1 Delay register for debug signal. Sub-nano sectond step (25/31ns) SEU 1 RO (0) Monitoring SEU flag. Data=1 means SEU of the registers is observed. By re-writing the registe, the flag is reset. A.2: PP ASIC 101

115 B Data Format B.1 ROD Data Format Data word Comments Frame x B0F0xxxx event frame word (control mode word) Hdr 0 x E E1234EE start of header marker for R OD data Hdr 1 reserved reserved header size = 8 words (excluding x B0F0xxxx word) Hdr 2 A TL A S format version=2 TGC format version=2 Hdr 3 x 62 or x 63 module type = 0 Hdr 4 Level-1ID Hdr 5 reserved reserved Bunch crossing ID[11..0] Hdr 6 reserved reserved reserved Trigger type 0 octant[7..0] source id: x 62 / x 63 = A/ C endcap; module type = 0 for ROD Hdr 7 Detector event type not used yet Status Global status word 0 means event is not OK. Status reserved Star Switch timeout status one bit per SSW ; 1 means timeout Status L ocal status word presence Presence is a pattern indicating which of the following data fragments are present a Status orbit count or other means of determining time-ofday in run. 32 bits give >100 hrs Data Fragment ID raw data word count fragment ID =1, length in words Data Fragment ID readout format hit data word count fragment ID =2, length in words Data Fragment ID readout format tracklet data word fragment ID =3, length in words count ( tracklet =3/4or 2/3coincidence) Data Fragment ID chamber format hit data word count fragment ID =4, length in words Data Fragment ID chamber format tracklet data word count fragment ID =5, length in words Data FragmentID R, hit data word count fragment ID =6, length in words Data Fragment ID R, tracklet data word count fragment ID =7, length in words Data Fragment ID H ipt output word count fragment ID =8, length in words Data Fragment ID Sector L ogic word count fragment ID =9, length in words Data raw data, hit, tracklet, sector logic, etc. fragments, in the order of the word counts. Data... Data last raw data, hit or tracklet word Trail 0 number of status elements = 4 Trail 1 number of data elements Trail 2 Status block position = 0, i.e. data follows status Frame x E0F0xxxx event frame word (control mode word) a. The number off ragment ID W C words and fragments is equal to the number of Hi bits in this pattern. B.1: Test ROD 102